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JPS5569830A - Intelligent terminal - Google Patents

Intelligent terminal

Info

Publication number
JPS5569830A
JPS5569830A JP14314078A JP14314078A JPS5569830A JP S5569830 A JPS5569830 A JP S5569830A JP 14314078 A JP14314078 A JP 14314078A JP 14314078 A JP14314078 A JP 14314078A JP S5569830 A JPS5569830 A JP S5569830A
Authority
JP
Japan
Prior art keywords
peripheral equipment
terminal
controller
arithmetic unit
intelligent terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14314078A
Other languages
English (en)
Inventor
Yoshimori Obata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14314078A priority Critical patent/JPS5569830A/ja
Publication of JPS5569830A publication Critical patent/JPS5569830A/ja
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)
JP14314078A 1978-11-20 1978-11-20 Intelligent terminal Pending JPS5569830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14314078A JPS5569830A (en) 1978-11-20 1978-11-20 Intelligent terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14314078A JPS5569830A (en) 1978-11-20 1978-11-20 Intelligent terminal

Publications (1)

Publication Number Publication Date
JPS5569830A true JPS5569830A (en) 1980-05-26

Family

ID=15331853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14314078A Pending JPS5569830A (en) 1978-11-20 1978-11-20 Intelligent terminal

Country Status (1)

Country Link
JP (1) JPS5569830A (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872939A (en) * 1996-06-05 1999-02-16 Compaq Computer Corporation Bus arbitration
US5872941A (en) * 1996-06-05 1999-02-16 Compaq Computer Corp. Providing data from a bridge to a requesting device while the bridge is receiving the data
US5903906A (en) * 1996-06-05 1999-05-11 Compaq Computer Corporation Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
US5987539A (en) * 1996-06-05 1999-11-16 Compaq Computer Corporation Method and apparatus for flushing a bridge device read buffer
US6021480A (en) * 1996-06-05 2000-02-01 Compaq Computer Corporation Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line
US6035362A (en) * 1996-06-05 2000-03-07 Goodrum; Alan L. Storing data associated with one request while continuing to store data associated with a previous request from the same device
US6052513A (en) * 1996-06-05 2000-04-18 Compaq Computer Corporation Multi-threaded bus master
US6055590A (en) * 1996-06-05 2000-04-25 Compaq Computer Corporation Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size
US6070209A (en) * 1996-12-31 2000-05-30 Compaq Computer Corporations Delivering transactions between data buses in a computer system
US6075929A (en) * 1996-06-05 2000-06-13 Compaq Computer Corporation Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction
US6108741A (en) * 1996-06-05 2000-08-22 Maclaren; John M. Ordering transactions

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872939A (en) * 1996-06-05 1999-02-16 Compaq Computer Corporation Bus arbitration
US5872941A (en) * 1996-06-05 1999-02-16 Compaq Computer Corp. Providing data from a bridge to a requesting device while the bridge is receiving the data
US5903906A (en) * 1996-06-05 1999-05-11 Compaq Computer Corporation Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
US5987539A (en) * 1996-06-05 1999-11-16 Compaq Computer Corporation Method and apparatus for flushing a bridge device read buffer
US6021480A (en) * 1996-06-05 2000-02-01 Compaq Computer Corporation Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line
US6035362A (en) * 1996-06-05 2000-03-07 Goodrum; Alan L. Storing data associated with one request while continuing to store data associated with a previous request from the same device
US6052513A (en) * 1996-06-05 2000-04-18 Compaq Computer Corporation Multi-threaded bus master
US6055590A (en) * 1996-06-05 2000-04-25 Compaq Computer Corporation Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size
US6075929A (en) * 1996-06-05 2000-06-13 Compaq Computer Corporation Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction
US6108741A (en) * 1996-06-05 2000-08-22 Maclaren; John M. Ordering transactions
US6070209A (en) * 1996-12-31 2000-05-30 Compaq Computer Corporations Delivering transactions between data buses in a computer system
US6138192A (en) * 1996-12-31 2000-10-24 Compaq Computer Corporation Delivering a request to write or read data before delivering an earlier write request

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