JPS5569830A - Intelligent terminal - Google Patents
Intelligent terminalInfo
- Publication number
- JPS5569830A JPS5569830A JP14314078A JP14314078A JPS5569830A JP S5569830 A JPS5569830 A JP S5569830A JP 14314078 A JP14314078 A JP 14314078A JP 14314078 A JP14314078 A JP 14314078A JP S5569830 A JPS5569830 A JP S5569830A
- Authority
- JP
- Japan
- Prior art keywords
- peripheral equipment
- terminal
- controller
- arithmetic unit
- intelligent terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Programmable Controllers (AREA)
Abstract
PURPOSE: To make it possible to introduce freely a desired peripheral equipment, by providing an intelligent terminal equipped with a central arithmetic unit and memory part and a magnetic tape between a sequential controller and peripheral equipments.
CONSTITUTION: Intelligent terminal 13 and desired peripheral equipment 12 are connected together via cable 14. From magnetic tape 15, a desired sequence program is loaded to sequential controller 11 and a control program as to peripheral equipment 12 corresponding to memory part 13C of terminal 13 is also loaded. Consequently, data can be transferred between controller 11 and peripheral equipment 12 through terminal 13. In this case, central arithmetic unit 13A controls equipment 12 to transfer only needed data between controller 11 and terminal 13, so that an increase in load on central arithmetic unit 11A will extremely be slight. Any peripheral equipment can therefore be used and various peripheral equipments can adequately be used for proper purposes.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14314078A JPS5569830A (en) | 1978-11-20 | 1978-11-20 | Intelligent terminal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14314078A JPS5569830A (en) | 1978-11-20 | 1978-11-20 | Intelligent terminal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5569830A true JPS5569830A (en) | 1980-05-26 |
Family
ID=15331853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14314078A Pending JPS5569830A (en) | 1978-11-20 | 1978-11-20 | Intelligent terminal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5569830A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872939A (en) * | 1996-06-05 | 1999-02-16 | Compaq Computer Corporation | Bus arbitration |
US5872941A (en) * | 1996-06-05 | 1999-02-16 | Compaq Computer Corp. | Providing data from a bridge to a requesting device while the bridge is receiving the data |
US5903906A (en) * | 1996-06-05 | 1999-05-11 | Compaq Computer Corporation | Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written |
US5987539A (en) * | 1996-06-05 | 1999-11-16 | Compaq Computer Corporation | Method and apparatus for flushing a bridge device read buffer |
US6021480A (en) * | 1996-06-05 | 2000-02-01 | Compaq Computer Corporation | Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line |
US6035362A (en) * | 1996-06-05 | 2000-03-07 | Goodrum; Alan L. | Storing data associated with one request while continuing to store data associated with a previous request from the same device |
US6052513A (en) * | 1996-06-05 | 2000-04-18 | Compaq Computer Corporation | Multi-threaded bus master |
US6055590A (en) * | 1996-06-05 | 2000-04-25 | Compaq Computer Corporation | Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size |
US6070209A (en) * | 1996-12-31 | 2000-05-30 | Compaq Computer Corporations | Delivering transactions between data buses in a computer system |
US6075929A (en) * | 1996-06-05 | 2000-06-13 | Compaq Computer Corporation | Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction |
US6108741A (en) * | 1996-06-05 | 2000-08-22 | Maclaren; John M. | Ordering transactions |
-
1978
- 1978-11-20 JP JP14314078A patent/JPS5569830A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872939A (en) * | 1996-06-05 | 1999-02-16 | Compaq Computer Corporation | Bus arbitration |
US5872941A (en) * | 1996-06-05 | 1999-02-16 | Compaq Computer Corp. | Providing data from a bridge to a requesting device while the bridge is receiving the data |
US5903906A (en) * | 1996-06-05 | 1999-05-11 | Compaq Computer Corporation | Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written |
US5987539A (en) * | 1996-06-05 | 1999-11-16 | Compaq Computer Corporation | Method and apparatus for flushing a bridge device read buffer |
US6021480A (en) * | 1996-06-05 | 2000-02-01 | Compaq Computer Corporation | Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line |
US6035362A (en) * | 1996-06-05 | 2000-03-07 | Goodrum; Alan L. | Storing data associated with one request while continuing to store data associated with a previous request from the same device |
US6052513A (en) * | 1996-06-05 | 2000-04-18 | Compaq Computer Corporation | Multi-threaded bus master |
US6055590A (en) * | 1996-06-05 | 2000-04-25 | Compaq Computer Corporation | Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size |
US6075929A (en) * | 1996-06-05 | 2000-06-13 | Compaq Computer Corporation | Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction |
US6108741A (en) * | 1996-06-05 | 2000-08-22 | Maclaren; John M. | Ordering transactions |
US6070209A (en) * | 1996-12-31 | 2000-05-30 | Compaq Computer Corporations | Delivering transactions between data buses in a computer system |
US6138192A (en) * | 1996-12-31 | 2000-10-24 | Compaq Computer Corporation | Delivering a request to write or read data before delivering an earlier write request |
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