JPS5553443A - Formation of electrode of semiconductor device - Google Patents
Formation of electrode of semiconductor deviceInfo
- Publication number
- JPS5553443A JPS5553443A JP12704678A JP12704678A JPS5553443A JP S5553443 A JPS5553443 A JP S5553443A JP 12704678 A JP12704678 A JP 12704678A JP 12704678 A JP12704678 A JP 12704678A JP S5553443 A JPS5553443 A JP S5553443A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal
- resist
- exposed
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To eliminate the generation of defective electrode by treating the surface of a wafer with O2 plasma and removing the remaining photoresist by reducing it to ashes when covering with the resist a lower metal layer provided on a semiconductor substrate; selectively removing the resist; and plating the exposed metal in the lower layer with metal.
CONSTITUTION: After covering with a SiO2 layer 4 a Si wafer on which a semiconductor region has been formed, thence after making a contact hole 3 for taking an electrode out at a location corresponding to the region, an Au layer 6, which is a plated metal, is placed on a Ti-W alloy layer 5, or metal in the lower layer in such a manner that both the layers touch the region too. Next the whole surface is coated with photoresist 7, removing the specified regions, so as to make metal 8 adhere to an exposed layer 6 by means of plating. In this case, the reamining resist 7 left on the exposed layer 6 is treated with the O2 plasma at first so as to reduce the resist into ashes for removal before the exposed layer is coated with metal. After the layer is provided with the metal, the resist and unnecessary portions of the layers 6 and 5 are removed by etching the wafer.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12704678A JPS5553443A (en) | 1978-10-16 | 1978-10-16 | Formation of electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12704678A JPS5553443A (en) | 1978-10-16 | 1978-10-16 | Formation of electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5553443A true JPS5553443A (en) | 1980-04-18 |
Family
ID=14950265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12704678A Pending JPS5553443A (en) | 1978-10-16 | 1978-10-16 | Formation of electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5553443A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175729A (en) * | 1987-12-29 | 1989-07-12 | Nec Corp | Manufacture of semiconductor device |
| US5266835A (en) * | 1988-02-02 | 1993-11-30 | National Semiconductor Corporation | Semiconductor structure having a barrier layer disposed within openings of a dielectric layer |
| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
-
1978
- 1978-10-16 JP JP12704678A patent/JPS5553443A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175729A (en) * | 1987-12-29 | 1989-07-12 | Nec Corp | Manufacture of semiconductor device |
| US5266835A (en) * | 1988-02-02 | 1993-11-30 | National Semiconductor Corporation | Semiconductor structure having a barrier layer disposed within openings of a dielectric layer |
| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
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