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JPS55108040A - Terminal control unit in data communication - Google Patents

Terminal control unit in data communication

Info

Publication number
JPS55108040A
JPS55108040A JP1518579A JP1518579A JPS55108040A JP S55108040 A JPS55108040 A JP S55108040A JP 1518579 A JP1518579 A JP 1518579A JP 1518579 A JP1518579 A JP 1518579A JP S55108040 A JPS55108040 A JP S55108040A
Authority
JP
Japan
Prior art keywords
signal
circuit
data
failure
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1518579A
Other languages
Japanese (ja)
Inventor
Yuji Nakamae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1518579A priority Critical patent/JPS55108040A/en
Publication of JPS55108040A publication Critical patent/JPS55108040A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To enable to transmit the content of status register to the communication line, when failure signal of the data processor is outputted, by storing the state of failure of data processing at terminal to the status register.
CONSTITUTION: When a failure is taken place to the data processing unit 1, the failure signal 9 is converted into the pulse signal 20, the gate circuit 8a is open and the transmission start command data of the data memory circuit 5 is fed to the input and output bus 2. After the signal 20 is delayed at the delay circuit 11, the gate circuit 8b is open and the text head data of the memory circuit 6 is fed to the bus 2. Further, the transmission of data of the circuit 6 is finished, the transmission end signal 12 is made from the communication control unit 3, the signal 12 is the decode signal 17 at the shift register circuit 15 to open the gate circuit 8c and the data of the failure state register 4 is fed to the bus 2. When the transmission from the register 4 is finished, signal 12 is made from the unit 5, and it is the decode signal 18 at the circuit 15 to open the gate circuit 8d, and the transmission end command data of the memory circuit 7 is fed to the bus 2.
COPYRIGHT: (C)1980,JPO&Japio
JP1518579A 1979-02-13 1979-02-13 Terminal control unit in data communication Pending JPS55108040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1518579A JPS55108040A (en) 1979-02-13 1979-02-13 Terminal control unit in data communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1518579A JPS55108040A (en) 1979-02-13 1979-02-13 Terminal control unit in data communication

Publications (1)

Publication Number Publication Date
JPS55108040A true JPS55108040A (en) 1980-08-19

Family

ID=11881765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1518579A Pending JPS55108040A (en) 1979-02-13 1979-02-13 Terminal control unit in data communication

Country Status (1)

Country Link
JP (1) JPS55108040A (en)

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