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JPS55107337A - Semiconductor integrated circuit device of mos type - Google Patents

Semiconductor integrated circuit device of mos type

Info

Publication number
JPS55107337A
JPS55107337A JP1389279A JP1389279A JPS55107337A JP S55107337 A JPS55107337 A JP S55107337A JP 1389279 A JP1389279 A JP 1389279A JP 1389279 A JP1389279 A JP 1389279A JP S55107337 A JPS55107337 A JP S55107337A
Authority
JP
Japan
Prior art keywords
type
output
output terminal
constitution
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1389279A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Kenji Matsuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1389279A priority Critical patent/JPS55107337A/en
Priority to US06/116,556 priority patent/US4389582A/en
Publication of JPS55107337A publication Critical patent/JPS55107337A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain FF circuit of MOS type IC of high speed operation, by providing Tr of synchronizing signal supply to the output terminal from Tr of input signal supply, in FF circuit with IC of C-MOS transistor Tr constitution. CONSTITUTION:P-type MOSTr11-13 and Tr14-16 are connected in series between the power supply VDD and the output terminal Q's, N-type MOSTr 18, 19 are connected in series between the terminal Q's and ground, and Tr 17, 18 are connected in parallel. With this constitution, P-type MOSTr 12 and N-type MOSTr 19 to which the clock pulse CP is fed are provided at the output terminal Q's from Tr 18, 13, 16 fed with the input signals QM, Qs. When the signal QM is at H level and the output Q's is at L level, if the clock CP moves from L to H level, P-type MOSTr12, 15 are OFF, being not contributed to the trailing of the output Q's N- type MOSTr18, 19 are ON, the charge of the capacitor between the output terminal Q's and ground is immediately discharged, the leading of the output Q's is made faster to enable high speed operation.
JP1389279A 1979-02-09 1979-02-09 Semiconductor integrated circuit device of mos type Pending JPS55107337A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1389279A JPS55107337A (en) 1979-02-09 1979-02-09 Semiconductor integrated circuit device of mos type
US06/116,556 US4389582A (en) 1979-02-09 1980-01-29 MOS Integrated logic circuit device with improved switching speed characteristics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1389279A JPS55107337A (en) 1979-02-09 1979-02-09 Semiconductor integrated circuit device of mos type

Publications (1)

Publication Number Publication Date
JPS55107337A true JPS55107337A (en) 1980-08-18

Family

ID=11845827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1389279A Pending JPS55107337A (en) 1979-02-09 1979-02-09 Semiconductor integrated circuit device of mos type

Country Status (1)

Country Link
JP (1) JPS55107337A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187227B2 (en) 2002-08-07 2007-03-06 Nippon Telegraph And Telephone Corporation Driver circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915849B1 (en) * 1967-10-21 1974-04-18
JPS5226857A (en) * 1975-08-25 1977-02-28 Toshiba Corp Minimum width measuring device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4915849B1 (en) * 1967-10-21 1974-04-18
JPS5226857A (en) * 1975-08-25 1977-02-28 Toshiba Corp Minimum width measuring device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7187227B2 (en) 2002-08-07 2007-03-06 Nippon Telegraph And Telephone Corporation Driver circuit
US7511539B2 (en) 2002-08-07 2009-03-31 Nippon Telegraph And Telephone Corporation Driver circuit

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