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JPS5448128A - Buffer memory unit - Google Patents

Buffer memory unit

Info

Publication number
JPS5448128A
JPS5448128A JP11484877A JP11484877A JPS5448128A JP S5448128 A JPS5448128 A JP S5448128A JP 11484877 A JP11484877 A JP 11484877A JP 11484877 A JP11484877 A JP 11484877A JP S5448128 A JPS5448128 A JP S5448128A
Authority
JP
Japan
Prior art keywords
reading
word
checked
operand
order word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11484877A
Other languages
Japanese (ja)
Inventor
Koemon Nigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11484877A priority Critical patent/JPS5448128A/en
Publication of JPS5448128A publication Critical patent/JPS5448128A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the process speed with a comparatively small amount of hardware increment by constituting the buffer memory unit so that the access request for both the order word and the operand word may be processed in the same cycle.
CONSTITUTION: When the reading request of the order word and the reading or writing requst of the operand word occur at address register 1 and addres register 2 respectively in a time, the coincidence is checked through comparator 4 between both addresses. In case no coincidence is obtained, whether the reading of the order word is possible with no index of directory memory part 5 is checked through check circuit 15. If the reading is possible, whether the reading of both the order word and the operand word are against the same compartment is checked through check circiut 14. In case they are not to the same compartment, the reading or writing of the order word and the operand word are processed simultaneously by giving addresses independently to compartments 6aW6d of the data memory part through switch circuits 7aW7d
COPYRIGHT: (C)1979,JPO&Japio
JP11484877A 1977-09-22 1977-09-22 Buffer memory unit Pending JPS5448128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11484877A JPS5448128A (en) 1977-09-22 1977-09-22 Buffer memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11484877A JPS5448128A (en) 1977-09-22 1977-09-22 Buffer memory unit

Publications (1)

Publication Number Publication Date
JPS5448128A true JPS5448128A (en) 1979-04-16

Family

ID=14648212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11484877A Pending JPS5448128A (en) 1977-09-22 1977-09-22 Buffer memory unit

Country Status (1)

Country Link
JP (1) JPS5448128A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139855A (en) * 1984-12-11 1986-06-27 Nec Corp Buffer storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139855A (en) * 1984-12-11 1986-06-27 Nec Corp Buffer storage device
JPH0438015B2 (en) * 1984-12-11 1992-06-23 Nippon Electric Co

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