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JPH1168025A - Multi-chip module substrate - Google Patents

Multi-chip module substrate

Info

Publication number
JPH1168025A
JPH1168025A JP22394997A JP22394997A JPH1168025A JP H1168025 A JPH1168025 A JP H1168025A JP 22394997 A JP22394997 A JP 22394997A JP 22394997 A JP22394997 A JP 22394997A JP H1168025 A JPH1168025 A JP H1168025A
Authority
JP
Japan
Prior art keywords
layer
resin
chip module
module substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22394997A
Other languages
Japanese (ja)
Inventor
Hidekatsu Sekine
秀克 関根
Sotaro Toki
荘太郎 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP22394997A priority Critical patent/JPH1168025A/en
Publication of JPH1168025A publication Critical patent/JPH1168025A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multi-chip module substrate where a substrate can be prevented front being warped, without deteriorating the adhesion of an insulating layer to a conductor wiring layer in strength. SOLUTION: A first resin layer 3 composed of BCB (benzocyclobutene) resin and inorganic filter dispersed therein and a second resin layer 4 of BCB resin are deposited for the formation of an insulating layer 10 on a substrate 1, where a conductor wiring layer 2 is formed. Furthermore, a via hole forming hole is bored in the insulating layer 10 at a prescribed position, then a copper thin film conductor layer is formed thereon by sputtering, and a via hole 6 and a conductor wiring layer 5 are formed through a semi-additive method for the formation of a multi-chip module substrate. Furthermore, when a multilayered multi-chip module substrate is needed, processes where the insulating layer 10 and the conductor wiring layer 5 are provided are repeatedly carried out a few times as required so as to obtain the multilayered multi-chip module substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はLSI、VLSI等
に代表される半導体集積回路の実装に用いられるマルチ
チップモジュール基板に係わり、さらに詳しくは絶縁層
と導体配線層との密着強度の向上を実現させるマルチチ
ップモジュール基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module substrate used for mounting a semiconductor integrated circuit represented by an LSI, a VLSI, etc., and more specifically, to an improvement in the adhesion strength between an insulating layer and a conductive wiring layer. The present invention relates to a multi-chip module substrate to be made.

【0002】[0002]

【従来の技術】従来のマルチチップモジュール基板は、
図2に示すように絶縁層23がベンゾシクロブテン(以
下BCBと称す)樹脂又はBCB樹脂中に無機充填剤を
添加した樹脂で構成されたマルチチップモジュール基板
であった。
2. Description of the Related Art Conventional multi-chip module substrates are:
As shown in FIG. 2, the insulating layer 23 was a multi-chip module substrate made of a benzocyclobutene (hereinafter referred to as BCB) resin or a resin obtained by adding an inorganic filler to a BCB resin.

【0003】上記のマルチチップモジュール基板におい
て、BCB樹脂を使った絶縁層上にスパッタリング等の
PVD法にて導体薄膜層を形成し、さらに電解めっきに
て導体層を形成する場合、BCB樹脂と導体層との密着
性は、例えば750gf/cmと高い密着強度が得られ
るが、BCB樹脂と導体層との熱膨張率の違いにより、
基板に反りが大きく発生し、半導体素子のフェイスダウ
ン実装が困難になったり、基板自身の外部回路への実装
が困難になるという問題がある。
In the above-mentioned multi-chip module substrate, when a conductor thin film layer is formed by a PVD method such as sputtering on an insulating layer using a BCB resin and then a conductor layer is formed by electrolytic plating, the BCB resin and the conductor As for the adhesion to the layer, a high adhesion strength of, for example, 750 gf / cm can be obtained, but due to the difference in the coefficient of thermal expansion between the BCB resin and the conductor layer,
There is a problem in that the substrate is greatly warped, which makes it difficult to mount the semiconductor element face-down or to mount the substrate on an external circuit.

【0004】また、BCB樹脂中に無機充填剤を添加す
ることにより、BCB樹脂と導体層との熱膨張率を合わ
せ、基板の反りを防止するといった試みがなされてい
る。この場合、フィラーをBCB樹脂に分散させる際に
BCB樹脂がフィラー中に吸着され、固定されることが
熱硬化時に運動の妨げとなり、フィラー近傍のBCB樹
脂の硬化が進まなくなり、膜表面の硬化状態にムラが発
生するといったこと、また、フィラーが存在することに
より樹脂との接着面積が低下するといったこと等により
密着強度(例えば600gf/cm)が低下し、生産及
び半導体素子のリペアでの配線剥離が発生するといった
問題が生じる。
Attempts have also been made to prevent the substrate from warping by adding an inorganic filler to the BCB resin so as to match the coefficient of thermal expansion between the BCB resin and the conductor layer. In this case, when the filler is dispersed in the BCB resin, the BCB resin is adsorbed and fixed in the filler, which hinders the movement at the time of thermosetting, and the hardening of the BCB resin in the vicinity of the filler does not proceed, and the cured state of the film surface The adhesion strength (for example, 600 gf / cm) is reduced due to the occurrence of unevenness in the resin and the decrease in the adhesive area with the resin due to the presence of the filler. This causes a problem such as the occurrence of

【0005】[0005]

【発明が解決しようとする課題】本発明は、前記問題点
に鑑みなされたものであり、その目的とするところは、
絶縁層と導体配線層との密着強度を低下させることな
く、且つ基板のそりを防止できるマルチチップモジュー
ル基板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the following:
It is an object of the present invention to provide a multi-chip module substrate capable of preventing warpage of a substrate without lowering adhesion strength between an insulating layer and a conductor wiring layer.

【0006】[0006]

【課題を解決するための手段】本発明は上記課題を解決
するために、まず請求項1においては、導体配線層を絶
縁層によって電気的に絶縁してなるマルチチップモジュ
ール基板において、前記絶縁層がBCB樹脂中に無機充
填剤を分散してなる第1樹脂層とBCB樹脂からなる第
2樹脂層の複合層で構成されていることを特徴とするマ
ルチチップモジュール基板としたものである。
According to the present invention, there is provided a multi-chip module substrate in which a conductor wiring layer is electrically insulated by an insulating layer. Comprises a composite layer of a first resin layer in which an inorganic filler is dispersed in BCB resin and a second resin layer made of BCB resin.

【0007】また、請求項2においては、前記導体配線
層がBCB樹脂からなる第2樹脂層上に形成されている
ことを特徴とする請求項1記載のマルチチップモジュー
ル基板としたものである。
According to a second aspect of the present invention, there is provided the multi-chip module substrate according to the first aspect, wherein the conductive wiring layer is formed on a second resin layer made of a BCB resin.

【0008】[0008]

【発明の実施の形態】以下本発明の実施の形態につき説
明する。図1に本発明のマルチチップモジュール基板の
一実施例の部分断面図を示す。本発明の特徴は、絶縁層
10がBCB樹脂中に無機充填剤を分散してなる第1樹
脂層3とBCB樹脂からなる第2樹脂層4で構成されて
いる点にある。BCB樹脂中に無機充填剤を分散してな
る第1樹脂層3で基板のそりを防止し、BCB樹脂から
なる第2樹脂層4で導体配線層との密着強度を向上さし
ている。このことから、絶縁層10を構成している第1
樹脂層と第2樹脂層の層数には限定はないが、絶縁層1
0の最上層には第2樹脂層4が必ず形成されている必要
がある。
Embodiments of the present invention will be described below. FIG. 1 shows a partial cross-sectional view of one embodiment of the multichip module substrate of the present invention. The feature of the present invention is that the insulating layer 10 is composed of a first resin layer 3 in which an inorganic filler is dispersed in a BCB resin and a second resin layer 4 made of a BCB resin. The first resin layer 3 in which an inorganic filler is dispersed in BCB resin prevents warpage of the substrate, and the second resin layer 4 made of BCB resin improves the adhesion strength with the conductor wiring layer. From this, the first layer forming the insulating layer 10
The number of the resin layer and the second resin layer is not limited.
It is necessary that the second resin layer 4 is always formed on the uppermost layer of "0".

【0009】BCB樹脂中に無機充填剤を分散してなる
第1樹脂層3は使用する導体配線層の導体層の材質、膜
厚等から、無機充填剤の配合比及び第1樹脂層の膜厚を
適宜選定することにより基板のそりを防止する条件を設
定することができる。
The first resin layer 3 in which the inorganic filler is dispersed in the BCB resin has a compounding ratio of the inorganic filler and a film of the first resin layer depending on the material and thickness of the conductor layer of the conductor wiring layer to be used. By appropriately selecting the thickness, conditions for preventing the warpage of the substrate can be set.

【0010】BCB樹脂からなる第2樹脂層4はスパッ
ター等のPVD法で導体薄膜を形成する場合導体薄膜と
の接着層としてのアンカーの役目を有しており、最終的
に形成される導体配線層5との所定の密着強度が確保で
きるようになっている。
The second resin layer 4 made of a BCB resin has a role of an anchor as an adhesive layer with the conductive thin film when a conductive thin film is formed by a PVD method such as sputtering, and the finally formed conductive wiring A predetermined adhesion strength with the layer 5 can be secured.

【0011】まず、BCB樹脂(ダウケミカル社製)と
シリカ粉末とを混合し三本ロール法によりシリカ粉末を
分散させた後メシチレン等で希釈し樹脂溶液Aを作製す
る。
First, a BCB resin (manufactured by Dow Chemical Company) and silica powder are mixed, and the silica powder is dispersed by a three-roll method, and then diluted with mesitylene or the like to prepare a resin solution A.

【0012】次に、前記樹脂溶液Aをロールコート法に
より導体配線層2が形成された基板1の表面に塗布し、
100℃のオーブン中で約30分間キュアして第1樹脂
層3を形成する。
Next, the resin solution A is applied to the surface of the substrate 1 on which the conductor wiring layer 2 is formed by a roll coating method,
The first resin layer 3 is formed by curing in an oven at 100 ° C. for about 30 minutes.

【0013】次に、BCB樹脂(ダウケミカル社製)を
メシチレン等で希釈して樹脂溶液Bを作製し、同じくロ
ールコート法により第1樹脂層3上に塗布し、窒素雰囲
気のオーブン中で75℃で約20分、100℃で約15
分、150℃で約15分、200℃で約30分硬化し、
第2樹脂層4を形成する。
Next, a resin solution B is prepared by diluting a BCB resin (manufactured by Dow Chemical Co., Ltd.) with mesitylene or the like, and is coated on the first resin layer 3 by a roll coating method in the same manner. About 20 minutes at 100 ° C, about 15 minutes at 100 ° C
For about 15 minutes at 150 ° C and about 30 minutes at 200 ° C,
The second resin layer 4 is formed.

【0014】次に、スパッタリング法により、例えばC
uをスパッタして、例えば0.3μm厚の薄膜導体層を
形成する。薄膜導体層の形成にあたってはPVD法等の
ドライめっきであればいずれの方式でも良いが、第2樹
脂層4との密着性を考慮した場合スパッタリング法が好
適である。
Next, by sputtering, for example, C
By sputtering u, a thin film conductor layer having a thickness of, for example, 0.3 μm is formed. In forming the thin film conductor layer, any method may be used as long as it is dry plating such as a PVD method, but a sputtering method is preferable in consideration of the adhesion to the second resin layer 4.

【0015】次に、薄膜導体層上に所定厚の感光層を形
成し、パターニング処理してレジストパターンを形成す
る。このレジストパターンは電解めっきで導体配線層を
形成するためのレジストパターンである。さらに、感光
層の膜厚は後工程で形成される導体配線層5の膜厚を決
定するので導体配線層5の膜厚によって適宜設定する。
Next, a photosensitive layer having a predetermined thickness is formed on the thin-film conductor layer, and is patterned to form a resist pattern. This resist pattern is a resist pattern for forming a conductor wiring layer by electrolytic plating. Further, the thickness of the photosensitive layer determines the thickness of the conductor wiring layer 5 formed in a later step, and is appropriately set according to the thickness of the conductor wiring layer 5.

【0016】次に、レジストパターンをマスクにして電
解銅めっきを行い、レジストパターンと同一膜厚まで銅
めっき層を形成し、レジストパターンを剥離し、レジス
トパターン下の薄膜導体層をソフトエッチングし、導体
配線層5を形成することで本発明のマルチチップモジュ
ール基板を作製する。
Next, electrolytic copper plating is performed using the resist pattern as a mask, a copper plating layer is formed to the same thickness as the resist pattern, the resist pattern is peeled off, and the thin film conductor layer under the resist pattern is soft-etched. The multi-chip module substrate of the present invention is manufactured by forming the conductor wiring layer 5.

【0017】さらに、多層化する場合は上記絶縁層10
と導体配線層5の工程を必要回数繰り返すことにより多
層配線層を有するマルチチップモジュール基板を作製す
ることができる。
Further, when forming a multilayer structure, the insulating layer 10
By repeating the steps of and the necessary number of times for the conductor wiring layer 5, a multi-chip module substrate having a multilayer wiring layer can be manufactured.

【0018】本発明に係わるマルチチップモジュール基
板の場合、絶縁層10がBCB樹脂中に無機充填剤が分
散してなる第1樹脂層3とBCB樹脂のみの第2樹脂層
4とで構成されているため、絶縁層10と導体配線層5
との密着強度が向上し、且つ基板の反りが防止される。
In the case of the multi-chip module substrate according to the present invention, the insulating layer 10 is composed of the first resin layer 3 in which the inorganic filler is dispersed in the BCB resin and the second resin layer 4 composed of only the BCB resin. Therefore, the insulating layer 10 and the conductor wiring layer 5
And the substrate is prevented from warping.

【0019】[0019]

【実施例】以下実施例により本発明を詳細に説明する。
BCB樹脂(ダウケミカル社製)100重量部と平均粒
径100オングストロームのシリカ粉末4重量部とを混
合し、三本ロールにてシリカ粉末を分散させた後メシチ
レン70重量部で希釈し、樹脂溶液Aを作製した。
The present invention will be described in detail with reference to the following examples.
100 parts by weight of a BCB resin (manufactured by Dow Chemical Company) and 4 parts by weight of silica powder having an average particle size of 100 Å were mixed, dispersed with a three-roll mill, and diluted with 70 parts by weight of mesitylene to obtain a resin solution A was prepared.

【0020】次に、前記樹脂溶液Aをロールコート法に
より導体配線層2が形成された基板1の表面に塗布し、
100℃のオーブン中で約30分間キュアし、20μm
厚の第1樹脂層3を形成した。
Next, the resin solution A is applied to the surface of the substrate 1 on which the conductor wiring layer 2 is formed by a roll coating method,
Cure in oven at 100 ° C for about 30 minutes,
A thick first resin layer 3 was formed.

【0021】次に、BCB樹脂(ダウケミカル社製)1
00重量部をメシチレン100重量部で希釈して樹脂溶
液Bを作製し、ロールコート法にて上記第1樹脂層3上
に塗布し、窒素雰囲気のオーブン中で75℃で約20
分、100℃で約15分、150℃で約15分、200
℃で約30分キュアし、5μm厚の第2樹脂層4を形成
した。
Next, BCB resin (manufactured by Dow Chemical Company) 1
The resin solution B was prepared by diluting 00 parts by weight with 100 parts by weight of mesitylene, applied on the first resin layer 3 by a roll coating method, and then dried at 75 ° C. in a nitrogen atmosphere oven at about 20 ° C.
Min, 100 ° C for about 15 minutes, 150 ° C for about 15 minutes, 200
C. for about 30 minutes to form a second resin layer 4 having a thickness of 5 .mu.m.

【0022】次に、エキシマレーザ(ビーム強度30m
j、周波数500Hz)により、絶縁層10の所定位置
にビアホール形成孔を形成した。
Next, an excimer laser (beam intensity 30 m
j, frequency 500 Hz), a via hole forming hole was formed at a predetermined position of the insulating layer 10.

【0023】次に、スパッタリング法にて、Arガスに
て逆スパッタを行った後Cuをスパッタして0.3μm
厚の薄膜導体層を形成した。
Next, by sputtering, reverse sputtering was performed with Ar gas, and then Cu was sputtered to a thickness of 0.3 μm.
A thick thin-film conductor layer was formed.

【0024】次に、薄膜導体層上に感光性レジストAZ
ーPLP30(ヘキスト社製)を塗布し、10μm厚の
感光層を形成し、露光・現像等のパターニング処理して
導体配線層を形成するための10μm厚のレジストパタ
ーンを形成した。
Next, a photosensitive resist AZ is formed on the thin film conductor layer.
A PLP30 (manufactured by Hoechst) was applied to form a 10 μm-thick photosensitive layer, and patterning treatment such as exposure and development was performed to form a 10 μm-thick resist pattern for forming a conductor wiring layer.

【0025】次に、硫酸銅めっき液を使った電解めっき
により、電流密度5A/dm2 でレジストパターン以外
の薄膜導体層上に銅めっきを行い、10μm厚の銅の導
体層を形成した。
Next, copper plating was performed on the thin film conductor layer other than the resist pattern at a current density of 5 A / dm 2 by electrolytic plating using a copper sulfate plating solution to form a copper conductor layer having a thickness of 10 μm.

【0026】次に、レジストパターンを剥離して、レジ
ストパターン下の薄膜導体層をソフトエッチングして、
ビアホール6及び導体配線層5を形成し、本発明のマル
チチップモジュール基板を作製した。
Next, the resist pattern is peeled off, and the thin film conductor layer under the resist pattern is soft-etched,
Via holes 6 and conductive wiring layers 5 were formed, and a multichip module substrate of the present invention was manufactured.

【0027】さらに、多層化する場合は上記絶縁層10
と導体配線層5の工程を必要回数繰り返すことにより多
層化されたマルチチップモジュール基板を作製できる。
Further, when forming a multilayer, the insulating layer 10
By repeating the steps of and the necessary number of times for the conductor wiring layer 5, a multilayered multi-chip module substrate can be manufactured.

【0028】[0028]

【発明の効果】上記したように、導体配線層を電気的に
絶縁する絶縁層が、BCB樹脂中に無機充填剤が分散し
てなる第1樹脂層とBCB樹脂のみの第2樹脂層で構成
されているため、絶縁層と導体配線層の密着強度が向上
し、且つ、基板の反りのないマルチチップモジュール基
板を得ることができる。
As described above, the insulating layer for electrically insulating the conductor wiring layer is composed of the first resin layer in which the inorganic filler is dispersed in the BCB resin and the second resin layer of only the BCB resin. Therefore, the adhesion strength between the insulating layer and the conductor wiring layer is improved, and a multi-chip module substrate without warping of the substrate can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のマルチチップモジュール基板の一実施
例の構成を示す部分断面図である。
FIG. 1 is a partial sectional view showing a configuration of an embodiment of a multichip module substrate of the present invention.

【図2】従来のマルチチップモジュール基板の構成を示
す部分断面図である。
FIG. 2 is a partial cross-sectional view showing a configuration of a conventional multichip module substrate.

【符号の説明】[Explanation of symbols]

1、21……基板 2、22……導体配線層 3…… BBC樹脂中に無機充填剤を添加した第1樹脂
層 4…… BBC樹脂からなる第2樹脂層 5、24……導体配線層 6……ビアホール 10、23……絶縁層
1, 21 ... substrate 2, 22 ... conductor wiring layer 3 ... first resin layer obtained by adding an inorganic filler to BBC resin 4 ... second resin layer made of BBC resin 5, 24 ... conductor wiring layer 6 Via hole 10, 23 Insulating layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】導体配線層を絶縁層によって電気的に絶縁
してなるマルチチップモジュール基板において、前記絶
縁層がベンゾシクロブテン樹脂中に無機充填剤を分散し
てなる第1樹脂層とベンゾシクロブテン樹脂からなる第
2樹脂層の複合層で構成されていることを特徴とするマ
ルチチップモジュール基板。
1. A multi-chip module substrate in which a conductive wiring layer is electrically insulated by an insulating layer, wherein the insulating layer is formed of a benzocyclobutene resin and an inorganic filler dispersed in an inorganic filler. A multi-chip module substrate comprising a composite layer of a second resin layer made of butene resin.
【請求項2】前記導体配線層がベンゾシクロブテン樹脂
からなる第2樹脂層上に形成されていることを特徴とす
る請求項1記載のマルチチップモジュール基板。
2. The multi-chip module substrate according to claim 1, wherein said conductive wiring layer is formed on a second resin layer made of a benzocyclobutene resin.
JP22394997A 1997-08-20 1997-08-20 Multi-chip module substrate Pending JPH1168025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22394997A JPH1168025A (en) 1997-08-20 1997-08-20 Multi-chip module substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22394997A JPH1168025A (en) 1997-08-20 1997-08-20 Multi-chip module substrate

Publications (1)

Publication Number Publication Date
JPH1168025A true JPH1168025A (en) 1999-03-09

Family

ID=16806230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22394997A Pending JPH1168025A (en) 1997-08-20 1997-08-20 Multi-chip module substrate

Country Status (1)

Country Link
JP (1) JPH1168025A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217514A (en) * 2000-02-03 2001-08-10 Denso Corp Multi-layered wiring board
US7019404B2 (en) 2002-01-24 2006-03-28 Shinko Electric Industries Co., Ltd. Multilayered circuit substrate, semiconductor device and method of producing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217514A (en) * 2000-02-03 2001-08-10 Denso Corp Multi-layered wiring board
US7019404B2 (en) 2002-01-24 2006-03-28 Shinko Electric Industries Co., Ltd. Multilayered circuit substrate, semiconductor device and method of producing same
US7250355B2 (en) 2002-01-24 2007-07-31 Shinko Electric Industries Co., Ltd. Multilayered circuit substrate, semiconductor device and method of producing same

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