JPH1166874A - Nonvoltatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a device capable of evaluating other memory cells by impressing a selection potential on plural nonvilatile memory cells and a word line and impressing a nonselection potential lower than the selection potential on nonselection word lines at the time of a normal mode and impressing the selection potential on word lines selected from the plural word lines and impressing a potential lower than the non-selection potential on nonselection word lines at the time of a prescribed mode. SOLUTION: In this flash memory, since the potential of nonselection word lines is made a negative potential, electrons are drawn out excessively from floating gates 404d and threshold voltages become lower than a grounded potential at the time of a programmed operation. In short, data of memory cells connected to the same subbit line 403 as that of the overprogrammed memory cells 404 are read out and it is possible to perform the evaluation of the data. Since the potential of the nonselection word lines can be made to be a negative potential lower than the grounded potential, the over-programmed memory cells 404 are made to be in nonconduction states at the time of a, non-selection, the evaluation is made possible without being affected by the memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor device, and more particularly to a flash memory.

[0002]

2. Description of the Related Art As a conventional nonvolatile semiconductor memory device,
For example, there is a flash memory disclosed in JP-A-6-244386.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to evaluate other memory cells connected to a bit line connected to a memory cell whose threshold value is lower than the non-selection level of a word line. To obtain a non-volatile semiconductor device capable of doing so. Another object of the present invention is to provide a nonvolatile semiconductor memory device in which a through current of a circuit for selecting a word line is suppressed.

[0004]

A non-volatile semiconductor memory device according to the present invention is provided in correspondence with a bit line, a plurality of word lines provided crossing the bit line, and intersections of the bit line and the plurality of word lines. A plurality of nonvolatile memory cells each having a drain connected to a bit line and a control gate connected to a corresponding word line, and a plurality of words in response to an address signal during a normal read operation. A selection potential is applied to a word line selected from the lines, and a non-selection potential lower than the selection potential is applied to a non-selected word line. In a predetermined mode, a plurality of word lines are responded to an address signal. Word line potential applying means is provided for applying a selection potential to a word line selected from among them and for applying a predetermined potential lower than the non-selection potential to unselected word lines. Than it is.

In addition, the word line potential applying means is connected to a first potential line for supplying a selection potential, a second potential line for supplying a non-selection potential and a predetermined potential, a first potential line and a second potential line. And a row selection circuit for applying a potential of a first potential line to a word line selected from a plurality of word lines in response to an address signal and applying a potential of a second potential line to a non-selected word line. , And during a normal read operation,
The circuit includes a low-level potential applying circuit that applies a non-selection potential to the second potential line and applies a predetermined potential to the second potential line in a predetermined mode.

The low-level potential applying circuit includes a pad connected to the second potential line and to which a predetermined potential is externally applied in a predetermined mode.

Further, the low-level potential applying circuit further connects the pad to the second potential line when a predetermined potential is applied to the pad, and sets the non-selection potential to the second potential line during a normal read operation. And a pad connected to a second potential line via a low level potential applying circuit.

A low-level switching circuit is connected between a pad and a second potential line, and has a gate connected to a non-selection potential node supplying a non-selection potential.
An OS transistor, a second N-channel MOS transistor connected between the non-selection potential node and the second potential line and having a gate connected to the pad, and a second N-channel M transistor
It includes a charging circuit for charging the gate of the OS transistor.

A row selection circuit is provided corresponding to a decoder for decoding an address signal and outputting a decode signal having an amplitude between a selection potential and a non-selection potential, and a plurality of word lines. A drive signal generating circuit connected to the second potential line while receiving the high level potential and outputting a drive signal having an amplitude between the high level potential and the potential of the second potential line in response to a decode signal; , Connected between the first potential line and the corresponding word line;
A P-channel type drive transistor which conducts in response to a drive signal attaining the potential of the second potential line;
A plurality of word line drivers having an N-channel type drive transistor connected between the potential line and a corresponding word line and conducting in response to a drive signal attaining a high level potential. It was done.

A row selection circuit for generating a negative potential equal to or lower than a predetermined potential; a decoder for decoding an address signal and outputting a decode signal having an amplitude between a selection potential and a non-selection potential; And a drive signal provided corresponding to the plurality of word lines, each receiving a high level potential and a negative potential, and outputting a drive signal having an amplitude between the high level potential and the negative potential in response to a decode signal A generating circuit, a P-channel drive transistor connected between the first potential line and the corresponding word line, and turned on in response to a drive signal becoming negative potential, and a word line corresponding to the second potential line , Connected in response to the drive signal attaining the high level potential.
And a plurality of word line drivers having a gate circuit including a channel type drive transistor.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, DINO according to an embodiment of the present invention will be described.
An R (DIvided NOR) flash memory will be described with reference to FIGS. First, referring to FIG. 1, a flash memory FM includes a power supply pad 1a and a ground pad receiving externally a power supply potential V _CC and a ground potential GND, respectively.
1b. This flash memory FM uses these power supply potentials
This is a single power supply flash memory that operates in response to V _CC and ground potential GND. In this embodiment, the power supply potential V _CC and ground potential GND are 3.3 V and 0 V, respectively. The flash memory FM further includes an external address signal AD.
It has an address pad 1c for receiving D. This address signal includes a plurality of bits. Therefore, a plurality of address signals ADD and address pads 1c shown in FIG. 1 are collectively shown.

Further, the flash memory FM receives a chip enable signal / CE and a write enable signal / W from outside.
It has pads 1d and 1e for receiving E 1 respectively. The chip enable signal / CE is a signal for enabling the flash memory FM. When the chip enable signal / CE is at a high level, it indicates that the flash memory FM is in a disabled state, and when it is at a low level, the flash memory FM is in an enabled state. The write enable signal / WE is used to program the flash memory FM,
This signal is for instructing erase and test. When it is at the low level, it indicates that program, erase or test has been instructed.

The flash memory FM further includes a pad 1f for receiving an output enable signal / OE from outside. The output enable signal / OE is a signal for instructing a read (read) operation of the flash memory FM. When the output enable signal / OE is at a low level, it indicates that the read operation is instructed. Further, the flash memory FM has a plurality of data pads 1g for exchanging 8-bit data D ₀ -D ₇ with the outside.

The flash memory FM further includes a buffer circuit 100. Buffer circuit 100 receives an address signal ADD input to pad 1c from the outside, and receives an address signal ADDi for an internal circuit in response to the address signal.
Output from the address buffer 110. Further, the buffer circuit 100 includes a chip enable signal / CE, a write enable signal which is externally input to the pads 1c, 1d and 1e.
CE that receives / WE and output enable signal / OE, respectively, and outputs chip enable signal / CE for the internal circuit and write output signal / WE and output enable signal / OE that respond to these signals.
The buffer 120 includes a WE buffer 130 and an OE buffer 140. Further, the buffer circuit 100 controls the internal chip enable signal from the CE buffer 120 and the OE buffer 140.
In response to / CE and the output enable signal / OE, the internal chip enable signal / CE is set to the low level indicating the enable state, and the internal output enable signal
An input / output buffer 150 for outputting data D _j (j = 0-7) read from the inside to the outside through the data pad 1g in response to / OE being set to the low level indicating data reading. including.

The input / output buffer 150 further includes a WE buffer
In response to the internal write enable signal / WE from 130, the internal chip enable signal / CE is set to the low level indicating the enable state, and the internal write enable signal / WE is set to the low level indicating that the program, erase or test is instructed. Data D ₀ -D ₇ received from outside via data pad 1g in response to
It is also a circuit for outputting as COM _j or program data D _j .

The flash memory FM further includes a CE buffer
120, internal chip enable signal / CE from WE buffer 130 and OE buffer 140, write enable signal / W
CPU (Central) that receives E and output enable signal / OE and command data COMj from input / output buffer 150, and outputs control signal CTRL in response to these signals.
Processing Unit) 200. The control signal CTRL is a general term for various control signals. The CPU 200 responds when the internal chip enable signal / CE is set to the low level indicating the enable state and the internal write enable signal / WE is set to the low level indicating that the program, erase or test is instructed. Data pad from outside
Receives data D ₀ -D ₇ received through 1g as command data COM _j, in response changes the control signal CTRL to the command data COM _j.

[0017] For example, when CPU 200 is an 8-bit command data COM _j indicates 41H (41 hex), i.e., CO
When M ₇ , COM ₆ , ..., COM ₀ = 0,1,0,0,0,0,0,1
CTRL is made to indicate a program, when referring to 20H, means that, COM _7, COM _6, ..., when COM ₀ = 0,0,1,0,0,0,0,0, control signals The CTRL points to the erase. Further, for example, the CPU 200 sets the command data COM _j to 81
H, that is, COM ₇ , COM ₆ , ..., COM ₀ = 1,0,0,0,
In the case of 0, 0, 0, 1, the control signal CTRL designates the special test mode in which the read operation is performed by setting the low level potential VL of the word line to a negative potential.

Further, the flash memory FM includes a low-level potential applying circuit 300 for outputting a low-level potential VL applied to a word line. In the special test mode in which the read operation is performed with the low-level potential VL of the word line set to a negative potential when the low-level potential application circuit 300 receives a negative potential from the outside, the low-level potential VL applied to the word line is set to the negative potential. During a normal read operation in which no word line is received, the low level potential VL applied to the word line is
D In this embodiment, the negative potential is -3.3V.

Further, the flash memory FM is provided in correspondence with a plurality of nonvolatile memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines 401 provided corresponding to the rows of the memory cells, and columns of the memory cells. And a memory cell array 400 including a plurality of main bit lines 402.

Further, the flash memory FM includes an internal address signal ADD _i from the address buffer 110, a low-level potential VL from the low-level potential applying circuit 300, and a CPU.
When the control signal CTRL from the memory cell array 400 receives the control signal CTRL from the memory cell array 400 and the control signal CTRL indicates a normal read operation, the address signal ADD _i
Select the word line that responds to the
Given V _CC, it includes a row selection circuit 500 to provide a low level potential VL which is the lower ground potential GND than the power supply potential V _CC to the unselected word lines.

[0021] The row selection circuit 500, when the control signal CTRL instructs the special test mode, selects a word line responsive to the address signal ADD _i from among a plurality of word lines 401,
The power supply potential V _{CC is applied} to the word line, and the low-level potential VL, which is lower than the ground potential GND, is applied to unselected word lines. Also, the row selection circuit 500 controls the control signal CT
RL time to instruct the program gives a negative program gate potential VPG to a word line responsive to an address signal ADD _i (-8 V in this embodiment). Further, the row selection circuit 50
When the control signal CTRL indicates erasing, 0 gives a boosted potential V _PP (10 V in this embodiment) higher than the power supply potential V _CC to the word line responding to the address signal ADDi. The row selection circuit 500 and the low level potential application circuit 300 are included in the word line potential application circuit.

Furthermore, the flash memory FM receives a control signal CTRL from the address signal ADD _i and CPU 200 from the address buffer 110, when the control signal CTRL instructs the normal read operation and a special mode, a plurality of source lines a source line voltage generator 600 to the ones in response to the address signal ADD _i in the potential SL _n to the ground potential GND. The source line potential generating circuit 600, when the control signal CTRL instructs the program, a floating (open) state potential SL _n of the plurality of source lines. Further, when the control signal CTRL indicates erasing, the source line potential generating circuit 600 generates a signal corresponding to an address signal among a plurality of source line potentials SL _n to a negative erasing potential VE (− 8V).

Furthermore, the flash memory FM receives a control signal CTRL from the address signal ADD _i and CPU 200 from the address buffer 110, when the control signal CTRL instructs the normal read operation and a special mode, in the memory cell array 400 the potential VW _n of a plurality of wells in which the memory cell of is formed comprising a well potential generation circuit 700 to the ground potential GND. Well potential generation circuit 700, the control signal CTRL when instructing program, the potential VW _n of the plurality of wells and the ground potential GND. Also, the well potential generation circuit 700
When the control signal CTRL instructs the erasing, to the ones in response to the address signals in the potential VW _n of the plurality of wells to a negative erase voltage VE.

Furthermore, the flash memory FM receives a control signal CTRL from the address signal ADD _i and CPU 200 from the address buffer 110, when the control signal CTRL instructs the normal read operation and a special mode, in the memory cell array 400 of the plurality of main bit lines 402, it gives an address signal ADD _i read potential to that in response to VR (1V in this embodiment), the high level or low level depending on whether current flows through the main bit line and it outputs the data D _j made to the column selection circuit and a sense amplifier circuit 800
Is provided. The column selection circuit and the sense amplifier circuit 800
When the control signal CTRL instructs the program, address signals ADD _i and data D _j of the plurality of main bit lines 402
Among them, a program drain potential VPD (6 V in this embodiment) is applied to one responding to high-level data.
When the control signal CTRL indicates erasing, the column selection circuit and the sense amplifier circuit 800 bring the potentials MBL _m of the plurality of main bit lines 402 into a floating (open) state.

Next, a part of the circuit of the CPU 200 will be described with reference to FIG. Referring to FIG. 2, CPU 200 has internal chip enable signal / CE and write enable signal / WE.
And control signal CT in response to command data COM ₀ -COM ₇
A special test mode detection circuit 210 for outputting a special test mode signal TE included in RL is included. When the chip enable signal / CE and the write enable signal / WE are both set to the low level at the beginning of the operation cycle, the special test mode detection circuit 210 converts the data D ₀ -D _{7 applied} to the input / output buffer 150 into the command data COM ₀ -COM ₇
This command data indicates special test mode 81H
The special test mode signal TE is set to a high level indicating that the special test mode has been set.

Next, the row selection circuit 500 will be described with reference to FIG.
Will be explained. Referring to FIG. 3, row selection circuit 500 is
Rank V_CC And the low-level potential VL
Is provided. Also, the row selection circuit 500
Is the address signal ADD_iTo decode the power supply potential V_CC Contact with
Row decode signal X having amplitude between ground potential GND₀, X ₁,
X_Two, X_Three,... Are output. Row deco
DA 510 is the address signal ADD_iIn response to two bits of
Supply one of the four row decode signals to the power supply potential V_CC When
And the other three units are set to the ground potential GND.
Is included. The row decoder 510 outputs the address signal ADD._i
Is a high level indicating the selection.
Number of gate selection signals SG₀, SG₁, SG_Two, ... occurs.

Further, the row selection circuit 500 is connected to the potential lines 501 and 502 and receives row decode signals X ₀ , X ₁ , X ₂ , X ₃ ,.
The potential of the selected word line 401 in response to
Includes a word line drive circuit 520 for setting the potential of the non-selected word line 401 to the potential of the potential line 502. further,
Row selection circuit 500, the address signal ADD _i and received a special test mode signal TE, the level shift signal generating circuit 530 for generating a level-shifted signal / LS in response to these signals
including. Level shift signal generating circuit 530, at a high level indicating that the special test mode signal TE is set to a special test mode, by detecting the change in the address signal ADD _i, the level shift signal from the change after a predetermined time has elapsed
/ LS is changed to a low level instructing a level shift.

Next, a word line drive circuit will be described with reference to FIG.
520 will be described. Referring to FIG. 4, word line drive circuit 520 includes a plurality of word line drivers WD provided corresponding to a plurality of word lines 401. Each word line driver WD receives the potential of the potential line 501 and is connected to the potential line 502, and responds to the decode signals X ₀ , X ₁ , X ₂ , X ₃ ,. drive signal generation circuit 521 for outputting a drive signal DS _t having an amplitude between the potential of the line 502
including. Each word line driver WD receives a potential from the potential lines 501 and 502 and drives the corresponding word line driver WD.
In response to DS _t becoming the potential of the potential line 502, the potential of the corresponding word line 401 is made the potential of the potential line 501, and in response to the corresponding drive signal DS _t becoming the potential of the potential line 501, A gate circuit 522 for setting the potential of the word line 401 to the potential of the potential line 502.

The drive signal generating circuit 521 outputs one of the row decode signals X _p (p = 0, 1, 2, 3) and X _q (q = 4, 5,
6,7) and a level shifter 521a that receives one of X _r (r = 8,9,10,11), respectively. Drive signal generation circuit 521 receives level-shifted row decode signals X _p , X _q , and X _r from level shifter 521a, and when all of them become the potential of potential line 501, corresponding drive signal DS
A NAND circuit 521b for setting _t to the potential of the potential line 502 is included. The level shifter 521a is level-shifted signal generation level shift signal / LS in response to goes low to indicate the level shift corresponding row decode signal X _p from the circuit 530, X _q, latches and shift the level X _r Provided to the NAND circuit 521b.

Next, the level shifter 521a will be described with reference to FIG. Referring to FIG. 5, the level shifter 521a
Receiving level shift signal / LS and the inverted signal from inverter 523, transfer gate TG is turned off in response to level shift signal / LS becoming low level instructing level shift. Transfer gate TG
It includes a P-channel MOS transistor 521aa and an N-channel MOS transistor 521ab. The level shifter 521a receives the row decode signal received via the transfer gate TG.
A latch circuit LT for latching and level shifting X _p , X _q , X _r is included. The latch circuit LT is composed of P-channel MOS transistors 521ac, 521ad and N-channel MOS transistors 52
Including 1ae, 521af. Further, the level shifter 521a has a latch circuit including an inverter INV. Inverter INV includes a P-channel MOS transistor 521ag and an N-channel MOS transistor 521ah.

Next, the NAND circuit 521b included in the word line driver WD will be described with reference to FIG. NAND circuit 521b
Including P-channel MOS transistor 521ba and N-channel MOS transistor 521bd receiving a row decode signal X _p. Also, P undergoing NAND circuit 521b row decode signal X _q
Channel MOS transistor 521bb and N-channel MOS
Includes transistor 521be. Further, P-channel MOS transistor 52 which receives the NAND circuit 521b row decode signal X _r
Includes 1bc and N-channel MOS transistor 521bf.

Next, the gate circuit 522 included in the word line driver WD will be described with reference to FIG. Gate circuit
522 is connected between the potential line 501 and the word line 401, the corresponding drive signal DS _t is P-channel MOS transistors 522a and potential line 502 and word line 401 which is rendered conductive in response to become the potential of the potential line 502 It is connected between an N-channel MOS transistor 522b rendered conductive in response to a corresponding drive signal DS _t is the potential of the potential line 501.

Next, the low-level potential applying circuit 300 will be described with reference to FIG. Low level potential applying circuit 300
Includes a pad 310 to which a negative potential lower than the ground potential GND is externally applied in the special test mode. Also, the low-level potential applying circuit 300 includes a low-level switching circuit 320 that conducts the pad 310 to the potential line 502 when a negative potential is applied to the pad 310 and applies the ground potential GND to the potential line 502 during a normal read operation. . Pad 310 is connected to potential line 502 via low level switching circuit 320. The low level switching circuit 320 is connected between the pad 310 and the potential line 502, and has a gate connected to the ground potential GND applied to the ground pad 1b.
And an N-channel MOS transistor 321 having a back gate connected to the potential line 502. Low-level switching circuit 320 includes an N-channel MOS transistor 322 connected between ground potential node 10b and potential line 502, a gate connected to pad 310, and a back gate connected to potential line 502. Further, low-level switching circuit 320 includes a charging circuit 323 for charging the gate of N-channel MOS transistor 322. The charging circuit 323 is a power supply potential applied to the power supply pad 1a.
A resistance element 323a having a high resistance connected between a power supply potential node for supplying V _CC and the gate of N-channel MOS transistor 322 is included.

When a negative potential is not applied to the pad 310 during a normal read operation or the like, the gate potential of the N-channel MOS transistor 322 is changed by the charging circuit 323 to the power supply potential.
Rises to V _CC and this N-channel MOS transistor 322
Becomes conductive, the potential line 502 and the ground potential node 10b conduct through the N-channel MOS transistor 322, and the potential VL of the potential line 502 becomes the ground potential GND. Also,
When a negative potential is applied to the pad 310 in the special test mode, the resistance element 323a has a high resistance value, so that the charging circuit 32
3 discharges more from the pad 310 than charges the gate of the N-channel MOS transistor 322, and the gate potential of the N-channel MOS transistor 322 becomes negative. The source potential of the N-channel MOS transistor 321 is also negative, and the gate is at the ground potential GND.
If the threshold voltage is higher than 1, the N-channel MOS transistor 321 becomes conductive and the potential line 502 and the pad
The transistor 310 and the N-channel MOS transistor 321 conduct, and the potential VL of the potential line 502 becomes a negative potential.

Next, the memory cell array 400 will be described with reference to FIG. Referring to FIG. 9, memory cell array 40
0 indicates a plurality of word lines 401, a plurality of main bit lines 402 intersecting the word lines 401, and a plurality of word lines 401.
And a sub bit line 403 connected to a corresponding main bit line 402 via a selection gate 405. Further, the memory cell array 400 includes a plurality of nonvolatile memory cells 404 provided corresponding to intersections of the sub-bit lines 403 and the word lines 401. Each of the nonvolatile memory cells 404 has a drain connected to a corresponding sub-bit line 403, a source connected to a source line 406, a floating gate, and a control gate connected to a corresponding word line 401. At the time of programming, normal reading, and reading in the special test mode, the memory cell 40 specified and selected in response to the address signal ADD is selected.
The selection gate 405 is controlled by gate selection signals SG ₀ , SG ₁ ,... So that the sub bit line 403 to which 1 is connected is electrically connected to the corresponding main bit line 402 through the selection gate 405.

Next, the column selection circuit and the sense amplifier 800 will be described with reference to FIG. Referring to FIG. 10, column select circuit and sense amplifier 800 are connected to a plurality of main bit lines 40.
2 and a plurality of column select gates 810 connected between the corresponding sense amplifiers 830. The column selection circuit and a sense amplifier 800, column decoder control signal CTRL is programmed, the column selection gate 810 responsive to the address signal ADD _i in response to indicate the normal read operation or special test mode in a conductive state 820 included. Further, the column selection circuit and the sense amplifier 800 apply a read potential to the main bit line 402 connected via the column selection gate 810 during the normal read operation and the special test mode, so that a current flows through the main bit line 402. Multiple sense amplifiers that output a low level signal if they do not flow
830 included. Furthermore, a column selection circuit and a sense amplifier 80
0, the control signal CTRL when showing the normal read operation and a special test mode, the output signals from the plurality of sense amplifiers 830, and outputs the 8-bit in response to the address signal ADD _i as data D ₀ -D ₇ An output circuit 840 is included.

Next, a sectional structure of the semiconductor substrate on which the memory cell array 400 is formed will be described with reference to FIGS. FIG. 11 shows a cross section in a direction along the main bit line 402. Referring to FIG. 11, memory cell 404 is formed in P well PW. The P well PW is formed on the main surface of the semiconductor substrate SUB, and is electrically separated from the base portion of the semiconductor substrate SUB by the N well NW. Well potential generation circuit 70
Well potential VW _n generated from 0 is given to the P-well PW. The element isolation insulating film IF is
Is formed on the main surface of the semiconductor substrate SUB so as to be separated from the memory cell 404 connected thereto.

The memory cell 404 has a drain 404a composed of an N-type semiconductor region formed on the surface of the P well PW, a P well
A source 404b, a drain 404a, and a source made of an N-type semiconductor region formed separately from the drain 404a on the surface of the PW
The semiconductor device includes a floating gate 404d formed facing the channel region sandwiched by 404b with the gate insulating film 404c interposed therebetween, and a control gate 404f formed facing the floating gate 404d with the insulating film 404e interposed therebetween. Adjacent ones of the memory cells 404 connected to the same sub-bit line 403 share the drain 404a or the source 404b. Potential WL _k of the word line 401 is applied to the corresponding control gate 404f. Also, the potential SL of the source line 406
_n is provided to the corresponding source 404b.

The selection gate 405 is one source / drain composed of an N-type semiconductor region formed on the surface of the P well PW.
405a, the other source / drain 405b formed of an N-type semiconductor region formed on the surface of the P well PW, and a channel region sandwiched between one and the other source / drain 405a and 405b via a gate insulating film 405c. Floating gate 405d and floating gate 40 to be formed
A control gate 405f is formed on 5d so as to be opposed to the other via an insulating film 405e. Control gate 405f receives a gate selection signal SG _y of correspondence. Since the selection gate 405 does not need to store data, the floating gate
Although the 405d is not required, the floating gate 405d is also formed since it is formed in the same manufacturing process as the memory cell 404. In addition, one of the sources /
The drain 405a is the drain 404a of the adjacent memory cell 404.
Is shared with. Further, the other source / drain 405b of the adjacent select gate 405 is shared.

The insulating film 410a is formed so as to cover the memory cell 404 and the select gate 405. The sub-bit line 403 is formed of a polysilicon layer on the insulating film 410a, and is connected to the drain 404a of the memory cell 404 via a contact hole opened in the insulating film 410a. Contact pad
410b is formed of a polysilicon layer on which the sub-bit line 403 is formed, and is connected to the other source / drain 405b of the select gate 405. The insulating film 410c is formed on the sub bit line 403 and the contact pad 410b. The main bit line 402 is formed of a first aluminum layer on the insulating film 410c, and is connected to the contact pad 410b via a contact hole opened in the insulating film 410c. The insulating film 410d is formed on the main bit line 402. The wiring IN for transmitting a signal or supplying a potential such as a power supply potential is formed using a second aluminum layer over the insulating film 410d. The insulating film 410e is formed on the wiring IN.

FIG. 12 shows a cross section in a direction along the word line 401. Referring to FIG. 12, a part of word line 401 faces floating gate 404d via insulating film 404e, and also functions as a control gate of memory cell 404.

Next, the erase operation of the flash memory FM will be described with reference to FIG. Erase is performed prior to the program. Referring to FIG. 13, when the chip enable signal / CE and the write enable signal / WE is high again and set to the low level, respectively the time t ₁ and t _2, the chip enable signal / CE and the write enable signal / WE (In FIG. 13, the write enable signal / WE
Since the direction of which is to early high level, at time t _3),
Flash memory FM fetches the data D _j given as command data COM _j. CPU 200 determines when it is detected that this command data COM _j is 20H, and an instruction to erase operation. And flash memory FM
In the same manner as from time t ₁ to t _3, really captures data D _j for sure may perform an erase operation as command data COM _j. CPU 200 is a state of indicating erase control signal CTRL determines that command data COM _j for verification may be performed erase operation When it is D0H.

[0043] In response to this control signal CTRL is a state of indicating an erase or potential SL _n of the source line 406 the source line voltage generator 600 in response to the address signal ADD
-8V. Also, well potential generation circuit 700 the potential VW _n of P-well PW in response to the address signal ADD to -8 V. Furthermore, the row selecting circuit 500 to the potential WL _k of the word line 401 in response to the address signal ADD to 10V. As a result, in the memory cell 404 responding to the address signal ADD,
10V for control gate 404f, -8V for source 404b, P
-8 V is applied to the well PW, and the drain 404a
Then, electrons are injected into the floating gate 404d from the channel region interposed between the source and the source 404b, and the threshold value of the memory cell 404 becomes higher than the power supply potential V _CC .

Next, a program operation of the flash memory FM will be described with reference to FIG. Referring to FIG. 14, first the erase operation as well as the chip enable signal / CE and the write enable signal / WE is high again and set to the low level at time t ₁ and t _2, respectively, the chip enable signal / CE and in earlier timing of the person who has become the high level of the write enable signal / WE (because better in FIG. 14, the write enable signal / WE becomes earlier high level at time t _3), the flash memory FM is The given data D _j is fetched as command data COM _j .
CPU 200 determines when it is detected that this command data COM _j is 41H, and an instruction of the program operation. Then, the flash memory FM in the same manner as from time t ₁ to t _3, it takes in the data D _j as program data. The CPU 200 sets the control signal CTRL to a state in which a program is instructed.

[0045] In response to the control signal CTRL is the state of indicating a program, the source line voltage generator 600 is set to open the source line 406, well potential generation circuit 700 and the ground potential GND well potential VW _n I do. The row selection circuit 500 is the potential WL _k of the word line 401 in response to the address signal ADD to -8 V. The row selection circuit 500 turns on the corresponding selection gate 405 so that the sub bit line 403 to which the memory cell 404 responding to the address signal ADD is connected is connected to the corresponding main bit line 402. Further, the column selection circuit and a sense amplifier 800 to the potential of the main bit line 402 to which the memory cell 404 to program the high level of data among the data D _j is connected to the 6V. This allows
In the memory cell 404 in which high-level data is programmed in response to the address signal ADD, the control gate
-8V is applied to 404f and 6V is applied to the drain 404a, electrons are extracted from the floating gate 404d to the drain 404a, and the threshold value of the memory cell 404 becomes the power supply potential V
_Lower than _CC . In the memory cell 404 to which low-level data is programmed, since 6 V is not applied to the drain 404a, electrons are not extracted from the floating gate 404d, and the threshold value of the memory cell 404 remains in the erased state, and the power supply potential V _Remains higher than _CC .

Next, a normal read operation of the flash memory FM will be described with reference to FIG. Referring to FIG. 15, the chip enable signal / CE is at time t ₁ to a high level remains the write enable signal / WE even after the lapse of a predetermined time is at a high level, CPU 200 is a normal read operation Is determined, and the control signal CTRL is set to a state in which a normal read operation is instructed. In response to the control signal CTRL being set to a state instructing a normal read operation, the source line potential generating circuit 600 sets the potential SL _n of the source line 406 in response to the address signal ADD to the ground potential GND, and generates the well potential. circuit 700 to the well potential VW _n to the ground potential GND.
During a normal read operation, the low-level potential VL applied from the low-level potential applying circuit 300 to the potential line 502 is the ground potential
Since the power supply potential V _CC is applied to the potential line 501 at the GND, the row decode signals X _p , X _q , and X _r to be input among the NAND circuits 521 b in the word line driver WD of the row selection circuit 500 are input. There is what has become all high level to the corresponding drive signal DS _t to the ground potential GND, and a gate circuit 522 receiving this the potential WL _k of the corresponding word line 401 to the power supply potential V _CC, the other word line driver WD The gate circuit 522 of the corresponding word line 40
The potential WLk of _{1 is set} to the ground potential GND. Also, the row selection circuit
Reference numeral 500 designates a sub bit line 403 to which a memory cell 404 responding to the address signal ADD is connected to a corresponding main bit line 402.
The corresponding selection gate 405 is turned on so as to be connected to.

Further, the column selection circuit and the sense amplifier 80
0 selects the main bit line 402 to which the memory cell 404 responding to the address signal ADD is connected, and connects the selected main bit line 402 to the corresponding sense amplifier 830. The sense amplifier 830 applies a potential of 1 V to the selected main bit line 402. As a result, in the memory cell 404 responding to the address signal ADD, 3.3V and
1V is applied to the drain 404a and 0V is applied to the source 404b, and the threshold voltage of the memory cell 404 is changed to the power supply potential V
_If it is lower than _CC , the memory cell 404 becomes conductive, and a current flows from the main bit line 402 to the selection gate 405, sub-bit line 403, drain 404a, source 404b, and source line 406. If the threshold voltage of the memory cell 404 is higher than the power supply potential V _CC ,
4 is turned off, and no current flows through the main bit line 402.

The sense amplifier 830 detects a current flowing through the main bit line 402, and provides an output circuit 840 with a high level when a current flows and a low level when no current flows. The output circuit 840 provides the output buffer 150 as data D _j reads 8-bit responsive to the address signal ADD of the output from the plurality of sense amplifiers 830. And
At time t ₂ the output enable signal / OE in response to set low, output buffer 150 outputs to the outside the read data D _j received from the column selection circuit and the sense amplifier 800 at time t _3.

Next, the special test mode operation of the flash memory FM will be described with reference to FIG. Referring to FIG. 16, first the erase and program operations as well as the chip enable signal / CE and the write enable signal / WE is again at a high level is the low level at time t ₁ and t _2, respectively, the chip enable At the timing of the signal / CE and the write enable signal / WE which have become the high level earlier (in FIG. 16, the write enable signal / W
Since E is at the high level earlier, time t
₃₎ captures the flash memory FM is given data D _j as command data COM _j. CPU 200 determines when it is detected that this command data COM _j is 81H, and an instruction of a special test mode operation, the control signal CTRL
Is set to a high level.

[0050] Further, while the write enable signal / WE is at the high level, the chip enable signal at time t ₅
When / CE is set to the low level, the CPU 200 determines that a read operation in the special test mode has been instructed, and sets the control signal CTRL to a state in which the special test mode operation is instructed.
In response to the control signal CTRL is a state of indicating special test mode operation, as in normal reading, the source line voltage generator 600 is a potential SL _n of the source line 406 in response to the address signal ADD at the ground potential GND, and the well potential generation circuit 700 the well potential VW _n to the ground potential GND.
The level shift signal generating circuit included in the row selection circuit 500 530, predetermined response to special test mode signal TE becomes high level, since the change in the effective address address signal ADD at time t ₄ After a lapse of time, the level shift signal / LS is set to low level.

In response to the level shift signal / LS going low, the level shifter 521a of the word line driver WD responds.
Are in a non-conductive state.
At this time, since already elapsed since the change in the effective address address signal ADD at time t ₄ a predetermined time, the row decode signal X _p of the address signal ADD indicating the effective address, X _q, X _r of level shifter 521a Latched by the latch circuit LT. At this time, the potential of the potential line 501 is set to the power supply potential V _CC , and
Since the potential of 2 is at the ground potential GND, the latched signal and the signal output from the inverter INV oscillate between the power supply potential V _CC and the ground potential GND. afterwards,
Since a negative potential of −3.3 V is applied to the pad 310 of the low-level potential applying circuit 300, the low-level potential VL applied from the low-level potential applying circuit 300 to the potential line 502 is the negative potential −
It becomes 3.3V.

Then, the signal latched by the latch circuit LT and the signal output from the inverter INV become the power supply potential V
_The level is shifted to a signal that swings between _CC and the negative potential -3.3V. The drive signal DS _t outputted from the NAND circuit 521b is also the amplitude of the signal between the power supply potential V _CC and the negative potential -3.3 V. That is, the low-level drive signal DS corresponding to the word line 401 selected in response to the address signal ADD.
_t changes from the ground potential GND to the negative potential -3.3V. Also,
The word line 401 selected in response to the address signal ADD remains at the power supply potential V _CC and does not change, but is not selected.
401 potential WL _k varies in response to the potential of the potential line 502 is changed to a negative potential from the ground potential GND to a negative potential -3.3 V. Further, the row selection circuit 500 turns on the corresponding selection gate 405 so that the sub bit line 403 connected to the memory cell 404 responding to the address signal ADD is connected to the corresponding main bit line 402 as in the normal read operation. .

Further, similarly to the normal read operation, the column selection circuit and the sense amplifier 800 are connected to the main bit line 402 to which the memory cell 404 responding to the address signal ADD is connected.
Is selected, and the selected main bit line 402 is connected to the corresponding sense amplifier 830. The sense amplifier 830 applies a potential of 1 V to the selected main bit line 402. As a result, in the memory cell 404 responding to the address signal ADD, the control gate 404f has 3.3V, the drain 404a has 1V, and the source 40 has
If 0 V is applied to 4b and the threshold voltage of the memory cell 404 is lower than the power supply potential V _CC , the memory cell 404 is turned on and the main bit line 402 is switched to the selection gate 405, the sub bit line 403, and the drain. 404a, source
A current flows through the path of 404b and the source line 406. If the threshold voltage of the memory cell 404 is higher than the power supply potential V _CC , the memory cell 404 is turned off, and no current flows through the main bit line 402.

The sense amplifier 830 detects the current flowing through the main bit line 402 in the same manner as in a normal read operation, and provides an output circuit 840 with a high level when a current flows and a low level when no current flows. The output circuit 840 outputs the address signal ADD among the outputs of the plurality of sense amplifiers 830.
_Are given to the input / output buffer 150 as read data Dj. Then, output enable signal / OE in response to at the low level at time t _6, input buffer 150 column selection circuit and a sense amplifier 800
And outputs to the outside the read data D _j received from at time t _7.

As described above, in the flash memory FM of the first embodiment, the potential of the unselected word line 401 is set to a negative potential. The voltage has become lower (for example, -1V) than the ground potential GND,
That is, the data of the memory cell 404 connected to the same sub-bit line 403 as the over-programmed memory cell 404 can be read and evaluated. Now, assume that a memory cell 404 temporarily exists, for example, the potential WL ₁ of the word line 401 in FIG.
Is received at the control gate, the leftmost memory cell 404 assumes that the threshold voltage has become negative due to overprogramming.
For example, the threshold voltage of the leftmost memory cell 404 connected to the same sub-bit line 403 as the word line 401 of FIG. 9 and receiving the potential WL ₀ of the word line 401 is higher than the power supply potential V _CC , and this high threshold voltage It is assumed that reading is performed from the memory cell 404 having.

The potential WL ₀ of the word line 401 is set to the power supply potential V _CC , but since the threshold voltage of the memory cell 404 performing reading is higher than the power supply potential V _CC , the memory cell 404 is turned off. Originally, the main bit line 402, the selection gate 405, the sub bit line 403, the source line
No current flows through the path 406. Therefore, the output of the corresponding sense amplifier 830 should normally be at the high level. However, the potential WL ₁ of the unselected word line 401
Is merely ground potential GND, the threshold voltage of the over-programmed memory cell 404 is negative, so that the word line
The potential WL ₁ 401 is a ground potential GND indicating the non-selected becomes conductive, select gate 40 from the main bit line 402
5, a current flows through the path of the sub-bit line 403, the drain 404a of the over-programmed memory cell 404, the source 404b of the over-programmed memory cell 404, and the source line 406. Therefore, when the potential WL ₁ of the non-selected word line 401 is simply the ground potential GND, and although the original outputs of the corresponding sense amplifier 830, such should be a high level, it becomes a low level. Due to such an erroneous read, the same sub-bit line
The evaluation of the memory cell 404 connected to 403 cannot be performed normally.

In a normal use of the flash memory FM, the over-programmed memory cell 404 is detected during the programming operation, and the threshold value lower than the ground potential GND is lower than the power supply potential V _CC and lower than the ground potential. Over program recovery to a high value (for example 1V),
ECC (Error Correction Check) is used to avoid erroneous reading. However, in the case of chip evaluation (test mode), these workarounds are often not performed. In the first embodiment, since the potential of the unselected word line 401 can be set to a negative potential lower than the ground potential GND, the over-programmed memory cell 404 is turned off when not selected, and the over-programmed memory cell 404 is turned off. Of the memory cell 404 connected to the same sub-bit line 403 without being affected by the above.

Further, since the negative potential applied to the non-selected word lines is externally applied, a circuit for generating the negative potential and a switching circuit associated therewith are not required, thereby suppressing an increase in chip size. .

[0059] Further, since the low-level drive signal DS _t inputted to the gate circuit 522 is made to level shifting from the ground potential GND to a negative potential, with reference to FIG. 7, when the drive signal DS _t is negative potential, Even when a negative potential is applied to the potential line 502, the N-channel
The voltage between the gate and the source of the MOS transistor 522b becomes 0 V, and the N-channel MOS transistor 522b is turned off. At this time, the P-channel MOS transistor 522a
Is conducting, and the word line 401 has the power supply potential V
_CC is given. However, if you leave the ground potential GND the low level of the drive signal DS _t is without being level-shifted, when the drive signal DS _t is of the ground potential GND, potential line
When negative potential -3.3V is applied to 502, N-channel MOS
The voltage between the gate and the source of the transistor 522b is 3.3V, which exceeds the threshold voltage of the N-channel MOS transistor 522b.
Becomes conductive. At this time, the P-channel MOS transistor 522a is conducting, and as a result, the P-channel MOS transistor 522a and the N-channel
A through current flows through the potential line 502 via the channel MOS transistor 522b. In contrast, since the low-level drive signal DS _t is level-shifted from the ground potential GND to a negative potential as described above in the first embodiment, a through current is not generated.

Further, in the first embodiment, the potential line 50
When a negative potential is applied to 2, the transfer gate TG of the level shifter 521a is in a non-conductive state, so that the signal latched by the latch circuit LT and the row decode signals X _p , X _q ,
It is set to the low level of X _r occurs, without both signals collide, never current flows from the row decoder 510 to the potential line 502.

Embodiment 2 Next, a flash memory according to another embodiment of the present invention will be described with reference to FIG. The difference between the second embodiment and the first embodiment is that the row selection circuit 50 according to the first embodiment is different from the first embodiment.
0, the word line driver WD receives and drives the potential lines 501 and 502. In the second embodiment, however, the word line driver WD operates with the potential V higher than the potential applied to the potential line 501. _P2 and the potential V _N2 which is lower than the negative potential given to the potential line 502 in the special test mode are driven, and the circuit configuration of the word line driver WD is changed accordingly. Hereinafter, this difference will be described, and the description of the same points as the first embodiment will be omitted.

Referring to FIG. 17, row selection circuit 500 includes a boosted potential generating circuit 540 for generating a boosted potential _VP2 higher than the potential applied to potential line 501 based on power supply potential V _CC and ground potential GND, It includes a negative potential generating circuit 550 for generating a negative potential V _N2 equal to or lower than the negative potential applied to potential line 502 in the special test mode based on power supply potential V _CC and ground potential GND. The drive signal generation circuit 521 of each word line driver WD receives and drives the boosted potential _VP2 and the negative potential _VN2 . Drive signal generation circuit 521 responds to row decode signals X _p , X _q , X _r having an amplitude between power supply potential V _CC and ground potential GND, and has an amplitude between boosted potential V _P2 and negative potential V _N2. Drive signal DS
generates _t . The drive signal generation circuit 521 is
Inverter 521c with the same configuration as inverter INV shown in
And 521d. Further, the gate circuit 522 includes an N-channel MOS transistor 522c and a P-channel MOS transistor 522d which receive the output of the inverter 521c at the gate.
Is newly included.

The flash memory according to the second embodiment
In the FM, the flash memory FM of the first embodiment is also used.
Perform almost the same operation as described above, and achieve the same effect.

[0064]

As described above, according to the present invention, other memory cells connected to the bit line to which the memory cell whose threshold value is lower than the non-selection level of the word line are evaluated. A non-volatile semiconductor device capable of performing the above-described operations.

Further, it is possible to obtain a nonvolatile semiconductor memory device in which a through current generated in a P-channel drive transistor and an N-channel drive transistor in a gate circuit is suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a flash memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a CPU of the flash memory according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a row selection circuit of the flash memory according to the first embodiment of the present invention;

FIG. 4 is a circuit diagram showing a word line drive circuit of the flash memory according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing a level shifter of the flash memory according to the first embodiment of the present invention;

FIG. 6 is a circuit diagram showing a NAND circuit of the flash memory according to the first embodiment of the present invention;

FIG. 7 is a circuit diagram showing a gate circuit of the flash memory according to the first embodiment of the present invention;

FIG. 8 is a circuit diagram showing a low-level potential applying circuit of the flash memory according to the first embodiment of the present invention;

FIG. 9 is a circuit diagram showing a memory cell array of the flash memory according to the first embodiment of the present invention.

FIG. 10 is a block diagram showing a column selection circuit and a sense amplifier of the flash memory according to the first embodiment of the present invention;

FIG. 11 is a sectional view showing a structure of the flash memory according to the first embodiment of the present invention;

FIG. 12 is a sectional view showing a structure of the flash memory according to the first embodiment of the present invention;

FIG. 13 is a timing chart showing an erase operation of the flash memory according to the first embodiment of the present invention;

FIG. 14 is a timing chart showing a program operation of the flash memory according to the first embodiment of the present invention;

FIG. 15 is a timing chart showing a normal read operation of the flash memory according to the first embodiment of the present invention;

FIG. 16 is a timing chart showing a special test mode operation of the flash memory according to the first embodiment of the present invention;

FIG. 17 is a circuit diagram showing a word line driver of the flash memory according to the second embodiment of the present invention.

[Explanation of symbols]

FM flash memory 300 low level potential applying circuit, 310 pad, 320 low level switching circuit 321 N channel MOS transistor, 322 N channel MO
S transistor 323 Charging circuit 401 Word line 403 Sub bit line 404 Memory cell, 404a Drain, 404f Control gate 500 row selection circuit, 501 potential line, 502 potential line 510 row decoder, WD word line driver 521 drive signal generation circuit, 522 gate circuit 522a P-channel MOS transistor 522b N-channel MOS transistor 550 Negative potential generation circuit

Claims (7)

[Claims] 1. A bit line, a plurality of word lines provided to cross the bit line, and a drain provided corresponding to an intersection of the bit line and the plurality of word lines, each connected to the bit line And a plurality of nonvolatile memory cells having a control gate connected to the corresponding word line, and selecting a word line selected from the plurality of word lines in response to an address signal during a normal read operation. A potential is applied, and a non-selection potential lower than the selection potential is applied to a non-selected word line. In a predetermined mode, a word line selected from among the plurality of word lines is responded to the address signal. A nonvolatile semiconductor memory including a word line potential applying means for applying the selection potential and for applying a predetermined potential lower than the non-selection potential to unselected word lines. Apparatus. 2. The word line potential applying means includes: a first potential line for supplying the selection potential, a second potential line for supplying the non-selection potential and the predetermined potential, the first potential line and the second potential line. 2 potential lines,
A row for applying the potential of the first potential line to a word line selected from the plurality of word lines in response to the address signal, and applying the potential of the second potential line to a non-selected word line. A selection circuit, and a low-level potential applying circuit for applying the non-selection potential to the second potential line during the normal read operation and applying the predetermined potential to the second potential line during the predetermined mode. Claim 1 containing
14. The nonvolatile semiconductor memory device according to claim 1. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said low-level potential applying circuit includes a pad connected to said second potential line and to which said predetermined potential is externally applied in said predetermined mode. 4. The low-level potential applying circuit, further comprising, when the predetermined potential is applied to the pad, electrically connecting the pad to the second potential line, and the non-selection potential during the normal read operation. 4. The nonvolatile semiconductor memory device according to claim 3, further comprising: a low-level switching circuit that supplies the second potential line to the second potential line, and the pad is connected to the second potential line via the low-level potential applying circuit. 5. The first N-channel MOS transistor connected between the pad and the second potential line and having a gate connected to a non-selection potential node for supplying the non-selection potential. A second N-channel MOS transistor connected between the non-selection potential node and the second potential line and having a gate connected to the pad;
5. The nonvolatile semiconductor memory device according to claim 4, further comprising a charging circuit for charging a gate of the S transistor. 6. The decoder according to claim 1, wherein said row selection circuit decodes said address signal and outputs a decode signal having an amplitude between said selection potential and said non-selection potential, and said plurality of word lines. Drive signals, each receiving a high-level potential and being connected to the second potential line, and having an amplitude between the high-level potential and the potential of the second potential line in response to the decode signal And a P-channel type connected between the first potential line and the corresponding word line, and turned on in response to the drive signal attaining the potential of the second potential line. An N-channel type transistor connected between the drive transistor and the second potential line and the corresponding word line, and rendered conductive in response to the drive signal attaining the high level potential; The nonvolatile semiconductor memory device according to claims 2 to claim 5 including a plurality of word line drivers and a gate circuit including a drive transistor. 7. The row selection circuit includes: a negative potential generation circuit that generates a negative potential equal to or less than the predetermined potential; a decode signal that decodes the address signal and has an amplitude between the selection potential and the non-selection potential. And a decoder for receiving the high-level potential and the negative potential, respectively, and an amplitude between the high-level potential and the negative potential in response to the decode signal. A drive signal generating circuit for outputting a drive signal having the following configuration, and a P-channel type drive connected between the first potential line and the corresponding word line, and turned on in response to the drive signal becoming the negative potential An N-channel transistor connected between the transistor and the second potential line and the corresponding word line, and rendered conductive in response to the drive signal attaining the high-level potential; The nonvolatile semiconductor memory device according to claims 2 to claim 5 including a plurality of word line drivers and a gate circuit including a Le-type drive transistor.