JP3667821B2 - Nonvolatile semiconductor memory - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an electrically writable / erasable nonvolatile semiconductor memory (EEPROM), and in particular, an EEPROM having a block system in which a memory cell array is divided into a plurality of cell blocks and read, written, and erased independently in units of blocks. To the row decoder.
[0002]
[Prior art]
In an EEPROM using a stack gate type MOS transistor having a structure in which a floating gate and a control gate are stacked as an electrically writable / erasable nonvolatile memory cell, the memory cell array is divided into a plurality of cell blocks, and read / write is performed. / A circuit configuration is proposed in which selection / non-selection is determined for each block so that it can be read / written / erased independently for each block in accordance with the operation mode of erasing for each block (for example, this application) Japanese Patent Application No. 4-281193) related to the applicant's application has been put into practical use.
[0003]
An example of an EEPROM that performs reading, writing, and erasing independently on a block-by-block basis is a NAND cell type EEPROM, part of which is shown in FIG.
In FIG. 6, 11i is a cell block, RMDi is a row main decoder provided corresponding to the plurality of cell blocks, and RSDi is a row sub-decoder provided corresponding to the plurality of cell blocks.
[0004]
The row main decoder RMDi decodes a row address signal and outputs a plurality of control signals whose potential changes according to each operation mode of read / write / erase and selection / non-selection of the corresponding cell block 11i. is there.
[0005]
The row sub-decoder RSDi controls data reading / writing / erasing with respect to the nonvolatile memory cells of the corresponding cell block 11i in accordance with a control signal supplied from the corresponding row main decoder RMDi.
[0006]
By the way, when adopting a system in which the control gate of the cell transistor is set to the voltage Vpp higher than the power supply voltage Vcc or the ground potential Vss at the time of writing or erasing the NAND type cell, the low-level at the time of writing or erasing is adopted. The gate insulating film of a specific transistor in the decoder is subjected to a great electric field stress, which has a great influence on the decrease in reliability. This will be described in detail below.
[0007]
FIG. 7 shows a part of one set of the row main decoder RMDi, the row sub-decoder RSDi and the cell block 11i in FIG. 6, and the NAND type cell NAC in the cell block 11i typically shows two pieces. ing.
[0008]
The row main decoder RMDi includes a NAND gate 70 for decoding a row address signal, a first inverter circuit 71 for inverting the output of the NAND gate, a second inverter circuit 72 for inverting the output of the first inverter circuit, The latch circuit 73 latches the outputs of the two inverter circuits. The power supply voltage Vcc is supplied to the power supply node of the NAND gate 70 and the two inverters 71 and 72, and the power supply voltage Vcc or the high voltage Vpp is switched and supplied to the first power supply node P of the latch circuit 73.
[0009]
The row sub-decoder RSDi has a predetermined voltage according to each operation mode of read / write / erase and selection / non-selection of the word lines WL1 to WL8 connected to the control gate of the NAND cell NAC of the corresponding cell block 11i. .., G8, and CMOS transfer gates TG inserted and connected between the input nodes G1, G2,..., G8 and one ends of the corresponding word lines WL1 to WL8, respectively. And a pull-down NMOS transistor Nd connected between one end of each of the word lines WL1 to WL8 and a ground node.
[0010]
Each of the CMOS transfer gates TG includes a PMOS transistor TP and an NMOS transistor TN connected in parallel. The PMOS transistor TP and the NMOS transistor TN are switched by applying a high voltage Vpp or a ground potential Vss to their gates. Be controlled. Note that, similarly to the first power supply node P of the latch circuit 73, the power supply voltage Vcc or the high voltage Vpp is switched and supplied to the substrate region of the PMOS transistor TP.
[0011]
In the NAND type cell NAC, nonvolatile memory cells M1 to M8 made of MOS transistors having floating gates are connected in series, one end is common to the bit line BLi via the selection transistor Q1, and the other end is common to the selection transistor Q2. It is connected to the source line CS. Each of the transistors is formed on the same well substrate, the control electrodes of the memory cells M1 to M8 are connected to the word lines WL1 to WL8, the control electrode of the selection transistor Q1 is connected to the selection line SL1, and the selection transistor Q2 The control electrode is connected to the selection line SL2.
[0012]
Each of the memory cells M1 to M8 has a threshold value corresponding to the data to be held. This threshold value is 0 V or more when "0" data is held, and the cell data is converted into ultraviolet rays from the word line potential at the time of reading. The value is set to a value lower than the value obtained by subtracting the threshold value at the time of erasing, and to 0 V or less when “1” data is held.
[0013]
In the case of a NAND-type EEPROM, normally, a state where “1” data is held is called an “erase state”, and a state where “0” data is held is called a “write state”. In addition, shifting the threshold value of the memory cell holding “1” data in the positive direction to hold “0” data is called “write operation”, and “0” data is held. Shifting the threshold value (Vth) of the memory cell in the negative direction to hold “1” data is called an erase operation.
[0014]
FIG. 8 shows a list of voltages applied to the memory cells M1 to M8 during data read / write / erase operations.
During the read operation, the bit line BLi is precharged to a certain voltage (for example, 5V) and then floated, the selection line SL1 is set to 5V, the selected memory cell word line WLi is set to 0V, and the unselected memory cell word line is set. A voltage higher than the threshold of the “0” data cell (for example, 5V) is applied to WLi, a power supply voltage (for example, 5V) is applied to the selection line SL2, 0V is applied to the well, and 0V is applied to the common source line CS. Then, all transistors (including non-selected memory cells) other than the selected memory cell are turned on. When “0” is held in the selected memory cell, this memory cell is in a non-conducting state and the potential of the bit line BLi remains 5V and does not change, but when “1” is held, it is in a conducting state. The bit line BLi is discharged and the potential is lowered. Data sensing is performed by detecting the bit line potential at the time of reading.
[0015]
At the time of erasing operation, the bit line BLi is opened, a voltage at which the gate of the selection transistor Q1 does not break down (for example, 18V having the same potential as the well) is selected on the selection line SL1, and 0V is selected on the word line WLi of the memory cell. The voltage at which the gate of the selection transistor Q2 is not destroyed at the line SL2 (for example, 18V having the same potential as the well), the voltage necessary for erasing the cell data (for example, 18V), and the common source line CS has the same potential as the well (Or open state). Then, a tunnel current flows through the gate insulating film between the floating gate and the well, and the threshold value becomes 0V or less.
[0016]
During the write operation, different voltages are applied depending on the write data. That is, in “0” writing (when the threshold value is shifted), a voltage (for example, 0 V) is applied to the bit line BLi to obtain an electric field necessary for shifting the cell threshold value, and “1” writing (threshold value is set). In the case of not shifting), a certain voltage (for example, 9 V) is applied to the bit line BLi so as not to shift the cell threshold. A voltage (for example, 11V) necessary for transferring 9V of the bit line BLi to the memory cell is obtained for the selection line SL1, and an electric field necessary for shifting the threshold value of the cell is obtained for the word line WLi of the selection memory cell. A possible voltage (e.g. 18V), a word line WLi of an unselected memory cell, a voltage required to transfer 9V of the bit line BLi to the selected memory cell without shifting the cell threshold (e.g. 9V), 0V is applied to the selection line SL2, 0V is applied to the well, and 0V is applied to the common source line CS. As a result, all the transistors from the selection transistor Q1 to the memory cell M8 become conductive and have the same potential as the bit line BLi.
[0017]
Accordingly, in the memory cell in which 0 V is applied to the bit line BLi, a high voltage of 18 V is applied between the channel and the control electrode, a tunnel current flows, and the threshold value is shifted in the positive direction. In addition, since the memory cell to which 9V is applied to the bit line BLi has only 9V between the channel and the control electrode, the shift of the threshold in the positive direction is suppressed. A voltage having a certain value (9 V in this example) applied so as not to shift the threshold value of the cell to the bit line BLi is called a write inhibit voltage Vinh.
[0018]
Here, in each of the data erasing / data writing operation modes in the conventional NAND type EEPROM, when the row main decoder RMDi selects / does not select the corresponding cell block 11i, the internal node S of the row main decoder RMDi and the plurality of nodes The relationship between the potentials of the control signals R1 and R2 is shown in FIG.
[0019]
When the row main decoder RMDi selects the cell block 11i at the time of erasing (when erasing is selected), the output node S of the first inverter circuit 71 is Vss, the output node SB of the second inverter circuit 72 is Vcc, and control is performed. The signal R1 becomes Vss and the control signal R2 becomes Vpp. At the time of erasing, the row sub-decoder RSDi is supplied with Vpp at the input nodes G1, G2,..., G8, and when receiving the control signals R1, R2, the transistors TP and TN are turned off and the transistor Nd is turned on. Turn on. Thereby, the word lines WL1, WL2,..., WL8 become Vss, and the data of the memory cells connected to these are erased.
[0020]
When the row main decoder RMDi does not select the cell block 11i at the time of erasing (when erasing is not selected), the node S is Vcc, the node SB is Vss, the control signal R1 is Vpp, and the control signal R2 is Vss. The row sub-decoder RSDi receives the control signals R1 and R2, and the transistors TP and TN are turned on and the transistor Nd is turned off. As a result, the word lines WL1, WL2,..., WL8 become Vpp, and the data of the cell block corresponding to the memory cells connected to these are not erased.
[0021]
Further, when the row main decoder RMDi selects the cell block 11i at the time of writing (when writing is selected), the node S becomes Vcc, the node SB becomes Vss, the control signal R1 becomes Vpp, and the control signal R2 becomes Vss. At the time of writing, for example, the row sub decoder RSDi has Vpp applied to the input node G1 corresponding to the selected word line WL1, and has an intermediate potential applied to the input nodes G2,..., G8 corresponding to the remaining unselected word lines WL2,. Assuming that the write inhibit voltage Vinh is supplied, when the control signals R1 and R2 are received, the transistors TP and TN are turned on and the transistor Nd is turned off. As a result, the word line WL1 becomes Vpp, data is written to the memory cells connected thereto, and the word lines WL2,..., WL8 become Vinh, and data is written to the memory cells connected thereto. Is not done.
[0022]
When the row main decoder RMDi does not select the cell block 11i at the time of writing (when writing is not selected), the node S becomes Vss, the node SB becomes Vcc, the control signal R1 becomes Vss, and the control signal R2 becomes Vpp. When the row sub-decoder RSDi receives the control signals R1 and R2, the transistors TP and TN are turned off and the transistor ND is turned on. As a result, the word lines WL1, WL2,..., WL8 become Vss, and data is not written into the memory cells connected thereto.
[0023]
However, when erasing is selected / programming is not selected as described above, the Vpp level control signal R2 is applied to the gate of the pull-down NMOS transistor Nd of the row sub-decoder, and the input nodes G1, G2,. , G8 is applied via the CMOS transfer gate TG, and the source is connected to the Vss node, so that the electric field stress applied to the gate oxide film is large.
[0024]
Further, when erasing is not selected as described above, the Vss level control signal R2 is applied to the gates of the PMOS transistors TP of all the CMOS transfer gates TG of the row sub-decoder RSDi, and the input nodes G1, Since the Vpp level is applied from G2,..., G8, a large electric field stress Vpp is applied to the gate oxide film.
[0025]
Further, at the time of write selection as described above, the PMOS transistor TP of the CMOS transfer gate TG of a part of the row sub-decoder RSDi is applied with the control signal R2 of the Vss level at the gate and part of the input at the source / drain. Since the Vpp level is applied from the node (G1 in this example), a large electric field stress Vpp is applied to the gate oxide film.
[0026]
[Problems to be solved by the invention]
As described above, in an EEPROM having a row decoder provided corresponding to a cell block in order to perform reading, writing, and erasing independently in units of cell blocks, the control gate of the cell transistor is powered when writing or erasing a memory cell. When a method of setting the voltage Vpp higher than the voltage Vcc or the ground potential Vss is adopted, a large electric field stress is applied to the gate insulating film of a specific transistor in the row sub-decoder at the time of writing or erasing. There was a problem that the influence on the reliability was large.
[0027]
The present invention has been made to solve the above-described problems, and can prevent the gate insulating film of a specific transistor in a row sub-decoder from receiving a great electric field stress during writing or erasing, and lowering its reliability. An object of the present invention is to provide a nonvolatile semiconductor memory capable of preventing the above.
[0028]
[Means for Solving the Problems]
A nonvolatile semiconductor memory according to the present invention is provided corresponding to a plurality of cell blocks each having an array of electrically programmable and erasable nonvolatile memory cells, and decodes a row address signal. A plurality of row main decoders for outputting a plurality of control signals whose potentials are set in accordance with respective read / write / erase operation modes, and a corresponding row main decoder provided corresponding to the plurality of row main decoders. A plurality of row sub-decoders for controlling reading / writing / erasing of data from / to the nonvolatile memory cells of the corresponding cell block in accordance with a control signal applied from the row main decoder, A NAND gate for decoding the row address signal, a first inverter circuit for inverting the output of the NAND gate, a second inverter circuit for inverting the output of the first inverter circuit and outputting a second control signal; A latch circuit that latches outputs of the two inverter circuits, the latch circuit including a first PMOS transistor and a first PMOS transistor connected in series between a first power supply node and a second power supply node; And a second PMOS transistor and a second NMOS transistor connected in series between the first power supply node and the ground node, and the gate of the first NMOS transistor is connected to the first NMOS transistor. The output of the inverter circuit is input, and the second inverter circuit is input to the gate of the second NMOS transistor. An output is input, a series connection point of the first PMOS transistor and the first NMOS transistor is connected to a gate of the second PMOS transistor, and a third control signal is taken out, and the second PMOS transistor A series connection point of the second NMOS transistor and the second NMOS transistor are connected to the gate of the first PMOS transistor and a first control signal is taken out. The first power supply node has a first potential higher than or equal to a power supply potential. A potential is switched and supplied, and the power supply potential or the ground potential is switched and supplied to the second power supply node. When the corresponding cell block is selected to be erased / not programmed, Said The potential of the first control signal is ground Potential, the potential of the second control signal is the power supply potential, and the potential of the third control signal The first The potential of the first control signal is set at the time of non-erasing / writing selection of the corresponding cell block. First And the potential of the second control signal ground Potential, the potential of the third control signal is the power supply potential or Second higher than ground potential Set to the potential of And The row sub-decoder is an input node to which a predetermined voltage is supplied in accordance with each operation mode of read / write / erase and selection / non-selection of a word line connected to a control gate of a memory cell of a corresponding cell block And a CMOS transfer gate inserted and connected between the input node and one end of the corresponding word line, and connected between the one end of the word line and the ground node. The third control signal is applied to the gate of the PMOS transistor of the CMOS transfer gate, and the second control signal is applied to the gate of the pull-down NMOS transistor. Applied to the NMOS transistor of the CMOS transfer gate. The over preparative wherein the first control signal is applied.
[0029]
[Action]
The row main decoder outputs a plurality of control signals controlled to predetermined potentials according to the corresponding cell block when erasing is selected / programming is not selected, and when the corresponding cell block is erasing is not selected / programming is selected. Separate control signals are supplied to the gate of the PMOS transistor and the gate of the NMOS transistor for pull-down in the corresponding row sub-decoder.
[0030]
Thus, the row main decoder appropriately sets the potential of the control signal so that the gate insulating film of the PMOS transistor and NMOS transistor in the row sub-decoder is not subjected to a great electric field stress at the time of writing or erasing the cell block. Thus, it becomes possible to prevent the reliability of the PMOS transistor and the NMOS transistor from being lowered. Moreover, the chip area does not increase significantly with such a configuration.
[0031]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing the overall configuration of a NAND cell type EEPROM according to the first embodiment of the present invention.
[0032]
The NAND type EEPROM 10 is a memory cell array 11 in which a plurality of NAND type memory cells are arranged in a matrix, a number of bit lines BL are arranged in the vertical direction, and a number of word lines WL are arranged in the horizontal direction. A row decoder 12 for selecting a word line of the memory cell array 11 based on an externally input address, a sense latch circuit 13 connected to the bit line of the memory cell array 11, and the sense latch circuit 13 is connected to the column gate 15, the column decoder 14 that controls the column gate 15 based on an externally input address and selects a corresponding bit line and sense circuit, and the column gate 15 connected to the column gate 15. Between the I / O buffer 18 and the booster circuit 16 for supplying a high voltage necessary for the write operation and the erase operation, and the outside of the chip. And a control circuit 17 for taking over the face.
[0033]
In the memory cell array 11, for example, eight memory cells and two select transistors are connected in series, and an array of NAND cells is divided into a plurality of cell blocks 11i as shown in FIG.
[0034]
For example, in the case of a 4 Mbit NAND type EEPROM, 256 8-bit (1 byte) type NAND cells are provided in the column direction and 256 in the row direction, so that a 4 Mbit cell array is formed as a whole. The cell block 11i is divided into 256 cell blocks 11i in the row direction, and each cell block 11i has 8 × 256 = 2 Kbytes of memory cells.
[0035]
The row decoder 12 includes a row main decoder 12Mi and a row sub-decoder 12Si provided corresponding to the plurality of cell blocks 11i, respectively.
The row main decoder 12Mi decodes a block address signal input from an address buffer (not shown) or the like, and sets a potential according to each operation mode of reading / writing / erasing and selection / non-selection of the corresponding cell block 11i. The circuit configuration is such that a plurality of control signals are output.
[0036]
The row sub-decoder 12Si controls reading / writing / erasing of data from / to the memory cells of the corresponding cell block 11i in accordance with a control signal supplied from the corresponding row main decoder 12Mi. Depending on the operation mode, the memory cell selection line (word line WLi), the selection transistor selection line SLi, etc. are set to required voltages so as to conform to the operation principle of the NAND type cell in the corresponding cell block 11i. It has a circuit configuration.
[0037]
In the present invention, the configuration of the row main decoder 12Mi and the control signal applied to the row sub-decoder 12Si are different from those of the conventional EEPROM.
FIG. 2 shows an example of a set of the row main decoder 12Mi, the row sub-decoder 12Si, and the cell block 11i, and two NAND-type cells NAC in the cell block 11i are representatively shown.
[0038]
The row main decoder 12Mi includes a NAND gate 70 for decoding a row address signal, a first inverter circuit 71 for inverting the output of the NAND gate, a second inverter circuit 72 for inverting the output of the first inverter circuit, The latch circuit 73 latches the outputs of the two inverter circuits. A power supply voltage Vcc is supplied to the power supply node of the NAND gate 70 and the two inverters 71 and 72.
[0039]
The latch circuit 73 includes a first PMOS transistor P1 and a first NMOS transistor N1 connected in series between a first power supply node P and a second power supply node Q, and the first power supply node P. And a ground node and a second PMOS transistor P2 and a second NMOS transistor N2 connected in series. The output of the first inverter circuit 71 is input to the gate of the first NMOS transistor N1, the output of the second inverter circuit 72 is input to the gate of the second NMOS transistor N2, and the first A series connection point (first output node A) of the PMOS transistor P1 and the first NMOS transistor N1 is connected to the gate of the second PMOS transistor P2, and the second PMOS transistor P2 and the second NMOS transistor N2 are connected in series. The connection point (second output node B) is connected to the gate of the first PMOS transistor P1.
[0040]
The power supply voltage Vcc or the high voltage Vpp is switched and supplied to the first power supply node P, and the ground potential Vss or the power supply voltage Vcc is switched and supplied to the second power supply node Q. The node Q is commonly connected to the latch circuit 73 of the row main decoder 12Mi corresponding to each cell block 11i.
[0041]
The potential of the second output node B of the latch circuit 73 is output as the first control signal R1, the potential of the first output node A is output as the third control signal R3, and the output node of the second inverter circuit 72 is output. The potential of SB is output as the second control signal R2. The potentials of these first to third control signals R1 to R3 change in accordance with each operation mode of reading / writing / erasing and selection / non-selection of the corresponding cell block 11i.
[0042]
That is, the row main decoder 12Mi sets the potential of the first control signal R1 to the first potential (the ground potential Vss in this example) and the second potential when the corresponding cell block 11i is selected for erasure / non-selection. The control signal R2 is set to the power supply potential Vcc and the third control signal R3 is set to the second potential higher than the power supply potential Vcc (in this example, the high voltage Vpp), and the corresponding cell block 11i is not erased. At the time of selection / writing selection, the potential of the first control signal R1 is set to the second potential Vpp, the potential of the second control signal R2 is set to the first potential Vss, and the potential of the third control signal R3 is set. The power supply potential Vcc or a third potential lower than this (for example, approximately 3 V) is set.
[0043]
Then, the row sub-decoder 12Si responds to each read / write / erase operation mode and selection / non-selection of the word lines WL1, WL2,..., WL8 connected to the control gates of the memory cells of the corresponding cell block 11i. .., G8 to which a predetermined voltage is supplied and the input node and one end of the corresponding word line are inserted and connected, and the PMOS transistor TP and the NMOS transistor TN are connected in parallel. A CMOS transfer gate TG, and a pull-down NMOS transistor Nd connected between one end of the word line WLi and the ground node. Then, the third control signal R3 is applied to the gate of the PMOS transistor TP of the CMOS transfer gate TG, and the second control signal R2 is applied to the gate of the NMOS transistor Nd for pull-down. The first control signal R1 is applied to the gate of the NMOS transistor TN of the transfer gate TG.
[0044]
Note that, similarly to the first power supply node P of the latch circuit 73, the power supply voltage Vcc or the high voltage Vpp is switched and supplied to the gate of the PMOS transistor TP of the CMOS transfer gate TG.
[0045]
The NAND type cell NAC is configured in the same manner as the conventional one. That is, nonvolatile memory cells M1 to M8 made of MOS transistors having floating gates are connected in series, one end is connected to the bit line BLi via the selection transistor Q1, and the other end is connected to the common source line CS via the selection transistor Q2. It is connected. Each of the transistors is formed on the same well substrate, the control electrodes of the memory cells M1 to M8 are connected to the word lines WL1 to WL8, the control electrode of the selection transistor Q1 is connected to the selection line SL1, and the selection transistor Q2 The control electrode is connected to the selection line SL2.
[0046]
Each of the memory cells M1 to M8 has a threshold value corresponding to the data to be held. This threshold value is 0 V or more when “0” data is held, and the cell data is converted into ultraviolet rays from the word line potential at the time of reading. It is set to a value lower than the value obtained by subtracting the threshold value at the time of erasure, and to 0 V or less when “1” data is held.
[0047]
At the time of data read / write / erase operation to the memory cells M1 to M8, a voltage is applied as shown in the list of FIG.
Next, operations of the row main decoder 12Mi and the row sub-decoder 12Si will be described with reference to FIGS.
[0048]
FIG. 3 shows a waveform example of the applied potential of the first power supply node P and the applied potential of the second power supply node Q of the latch circuit 73 in the row main decoder 12Mi.
FIG. 4 shows the row main decoder 12Mi when the row main decoder 12Mi selects / does not select the corresponding cell block 11i in the data erasure / data write operation modes in the EEPROM of the present embodiment (first embodiment). The relationship between the internal node S and the potentials of the plurality of control signals R1, R2, and R3 is shown as a list.
[0049]
At the time of erasing, the row main decoder 12Mi is assumed to initially apply Vcc to the first power supply node P of the latch circuit 73 and Vss to the second power supply node Q. When the cell block 11i is selected at the time of erasing (when erasing is selected), the output node S of the first inverter circuit 71 is Vss, and the potential of the output node SB of the second inverter circuit 72 (control signal R2) is Vcc. As a result, the first NMOS transistor N1 is turned off, but the second NMOS transistor N2 is turned on and the control signal R1 becomes Vss, and the first PMOS transistor P1 is turned on and the control signal is turned on. R3 becomes Vcc.
[0050]
After the selection of the cell block 11i is thus determined, the potential of the first power supply node P is boosted to Vpp, and the control signal R3 becomes Vpp. Thereafter, the potential of the second power supply node Q is switched to Vcc. However, since the first NMOS transistor N1 is in the OFF state, the potential of the first output node A (control signal R3) is not affected.
[0051]
When the erase is selected, Vpp is supplied to the input nodes G1, G2,..., G8 of the row sub-decoder 12Si, and when the row sub-decoder 12Si receives the control signals R1, R2, the transistors TP and TN are turned off. Thus, the transistor Nd is turned on. Thereby, the word lines WL1, WL2,..., WL8 become Vss, and the data of the memory cells connected to these are erased.
[0052]
In this case, the pull-down NMOS transistor Nd of the row sub-decoder 12Si does not need to have a gate applied potential of Vpp as in the conventional example, and is turned on even when Vcc is applied as in this embodiment. As described above, the Vcc level control signal R2 is applied to the gate of the pull-down NMOS transistor Nd, and the Vss level is applied to the drain from the input nodes G1, G2,..., G8 via the CMOS transfer gate TG. Since the source is connected to the Vss node, the electric field stress applied to the gate oxide film is Vcc, which is smaller than Vpp of the conventional example.
[0053]
When the row main decoder 12Mi does not select the cell block 11i at the time of erasing (when erasing is not selected), the node S becomes Vcc and the potential of the node SB (control signal R2) becomes Vss. As a result, the second NMOS transistor N2 is turned off, but the first NMOS transistor N1 is turned on and the control signal R3 becomes Vss, and the second PMOS transistor P2 is turned on and the control signal is turned on. R1 becomes Vcc.
[0054]
After the selection of the cell block 11i is thus determined, the potential of the first power supply node P is boosted to Vpp and the control signal R1 becomes Vpp. Thereafter, the potential of the second power supply node Q is switched to Vcc, and the first output node A is charged from the second power supply node Q via the first NMOS transistor N1. At this time, the potential of the first output node A (control signal R3) becomes a value (approximately 3 V) that is lower than the potential Vcc of the second power supply node Q by the threshold value of the first NMOS transistor N1.
[0055]
When the row sub-decoder 12Si receives the control signals R1, R2, and R3 when the erase is not selected, the transistors TP and TN are turned on and the transistor Nd is turned off. As a result, the word lines WL1, WL2,..., WL8 become Vpp, and the data of the cell block corresponding to the memory cells connected to these are not erased.
[0056]
In this case, the PMOS transistors TP of all the CMOS transfer gates TG of the row sub-decoder 12Si are supplied with the same potential (Vcc or Vpp) as the first power supply node P of the latch circuit 73 in the substrate region. The applied potential of the gate does not need to be Vss as in the conventional example, and it is turned on even when approximately 3 V is applied as in this embodiment.
[0057]
In this way, the PMOS transistor TP has a gate applied with the control signal R3 of approximately 3V and the source / drain applied with Vpp from the input nodes G1, G2,..., G8. The electric field stress is Vpp-3V, which is smaller than Vpp of the conventional example.
[0058]
Further, at the time of writing, the row main decoder 12Mi is assumed to initially apply Vcc to the first power supply node P of the latch circuit 73 and Vss to the second power supply node Q. When the cell block 11i is selected at the time of writing (when writing is selected), the node S becomes Vcc and the node SB (control signal R2) becomes Vss. As a result, the second NMOS transistor N2 is turned off, but the first NMOS transistor N1 is turned on and the control signal R3 becomes Vss, and the second PMOS transistor P2 is turned on and the control signal is turned on. R1 becomes Vcc.
[0059]
After the block selection is thus determined, the potential of the first power supply node P is boosted to Vpp, and the control signal R1 becomes Vpp. Thereafter, the potential of the second power supply node Q is switched to Vcc, the first output node A is charged from the second power supply node Q via the first NMOS transistor N1, and the potential of the first output node A is charged. (Control signal R3) is approximately 3V.
[0060]
At the time of the write selection, the row sub-decoder 12Si has, for example, Vpp at the input node G1 corresponding to the selected word line WL1, and an intermediate potential at the input nodes G2,..., G8 corresponding to the remaining unselected word lines WL2,. Assuming that the write inhibit voltage Vinh is supplied, when the control signals R1, R2, and R3 are received, the transistors TP and TN are turned on and the transistor Nd is turned off.
[0061]
As a result, the word line WL1 becomes Vpp, data is written to the memory cells connected thereto, and the word lines WL2,..., WL8 become Vinh, and data is written to the memory cells connected thereto. Is not done.
[0062]
In this case, in the row subdecoder 12Si, the control signal R3 of approximately 3V (different from Vss in the conventional example) is applied to the gates of the PMOS transistors TP of some of the CMOS transfer gates TG connected to the input node G1. Since Vpp is applied to the source / drain from the input node G1, the electric field stress applied to the gate oxide film is Vpp-3V, which is smaller than Vpp of the conventional example.
[0063]
When the row main decoder 12Mi does not select the cell block 11i at the time of writing (when writing is not selected), the node S becomes Vss and the potential of the node SB (control signal R2) becomes Vcc. As a result, the first NMOS transistor N1 is turned off, but the second NMOS transistor N2 is turned on and the control signal R1 becomes Vss, and the first PMOS transistor P1 is turned on and the control signal is turned on. R3 becomes Vcc.
[0064]
After the selection of the cell block 11i is thus determined, the potential of the first power supply node P is boosted to Vpp, and the control signal R3 becomes Vpp. Thereafter, the potential of the second power supply node Q is switched to Vcc. However, since the first NMOS transistor N1 is in the OFF state, the potential of the first output node A (control signal R3) is not affected.
[0065]
When the row sub-decoder 12Si receives the control signals R1, R2, and R3 when the write is not selected, the transistors TP and TN are turned off and the transistor Nd is turned on. As a result, the word lines WL1, WL2,..., WL8 become Vss, and data is not written into the memory cells connected thereto.
[0066]
In this case, the pull-down NMOS transistor Nd of the row sub-decoder 12Si does not need to have a gate applied potential of Vpp as in the conventional example, and is turned on even when Vcc is applied as in this embodiment. As described above, the Vcc level control signal R2 is applied to the gate of the pull-down NMOS transistor Nd, and the Vss level is applied to the drain from the input nodes G1, G2,..., G8 via the CMOS transfer gate TG. Since the source is connected to the Vss node, the electric field stress applied to the gate oxide film is Vcc, which is smaller than Vpp of the conventional example.
[0067]
In the above embodiment, since the potential of the node S of the row main decoder 12Mi at the “H” level is Vcc, as described above, the potential of the second power supply node Q becomes Vcc at the time of erase non-selection / write selection. Then, the potential of the control signal R3 becomes approximately 3V, which is lowered from Vcc by the threshold value of the first NMOS transistor N1. In this case, for example, if the potential at the “H” level of the node S is made higher than Vcc using a bootstrap circuit, the potential of the control signal R3 at the time of the non-erasing / selection selection is set to Vcc. The electric field stress applied to the gate oxide film of the PMOS transistor TP to which the control signal R3 is applied to the gate becomes Vpp-Vcc, which is further smaller than Vpp-3V in the above embodiment.
[0068]
FIG. 5 shows a part of an EEPROM according to the second embodiment of the present invention.
Compared with the EEPROM of the first embodiment of the present invention described above with reference to FIG. 2, this EEPROM sets the potential of the third control signal R3 output from the row main decoder at the time of erase non-selection / write selection to Vcc. As described above, the configuration of a part of the row main decoder 12Mi is changed, and the other parts are denoted by the same reference numerals as those in FIG.
[0069]
In each data erasing / data writing operation mode in the EEPROM of the second embodiment, the internal node S and control of the row main decoder 12Mi when the row main decoder 12Mi selects / does not select the corresponding cell block 11i. The relationship between the potentials of the signals R1, R2, and R3 is shown in FIG.
[0070]
That is, in the row main decoder 12Mi, the first NMOS transistor N1 of the row main decoder 12Mi shown in FIG. The gate of the NMOS transistor DN is connected to the node S, and the gate of the PMOS transistor EP is connected to the node SB.
[0071]
The operation of the row main decoder 12Mi differs from the operation of the row main decoder in the first embodiment described above when the potential of the second power supply node Q becomes Vcc when erasing is not selected / programmed. Since the others are the same, the description thereof is omitted. That is, at the beginning of erase non-selection / programming selection, if Vcc is applied to the first power supply node P of the latch circuit 73 and Vss is applied to the second power supply node Q, the node S is Vcc, SB (control signal R2) becomes Vss. As a result, the second NMOS transistor N2 is turned off, but the depletion type NMOS transistor DN and the enhancement type PMOS transistor EP are both turned on, and the potential of the first output node A (control signal R3). ) Becomes a value determined by the threshold value of the PMOS transistor EP (approximately 1V), the second PMOS transistor P2 is turned on, and the control signal R1 becomes Vcc.
[0072]
After the selection of the cell block 11i is thus determined, the potential of the first power supply node P is boosted to Vpp, and the control signal R1 becomes Vpp. Thereafter, the potential of the second power supply node Q is switched to Vcc, and the first output node A is charged from the second power supply node Q through the enhancement type PMOS transistor EP and the depletion type NMOS transistor DN. The potential of the first output node A (control signal R3) becomes Vcc.
[0073]
When the erasing non-selection / writing selection is selected, when the row sub-decoder 12Si receives the control signals R1, R2, and R3, the transistors TP and TN are turned on and the transistor Nd is turned off. In this case, in the PMOS transistor TP to which the Vcc control signal R3 is applied to the gate, Vpp is applied to the source / drain from the input node, so that the electric field stress applied to the gate oxide film is Vpp−Vcc. It becomes smaller than Vpp-3V of one embodiment.
[0074]
The present invention can be applied not only to the NAND type EEPROM of the above embodiment but also to a NOR type EEPROM, and applies either a method of applying a ground potential to the control gate or a negative voltage when erasing data in the memory cell. This can be applied to an EEPROM having an arbitrary erasing method such as a method.
[0075]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory of the present invention, it is possible to prevent the gate insulating film of a specific transistor in the row sub-decoder from being subjected to a great electric field stress at the time of writing or erasing, thereby reducing its reliability. Can be prevented.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing an overall configuration of a NAND type EEPROM according to a first embodiment of the present invention;
2 is a circuit diagram showing an example of a set of a row main decoder, a row sub-decoder and a cell block in FIG. 1;
3 is a diagram showing waveform examples of an applied potential of a first power supply node P and an applied potential of a second power supply node Q of a latch circuit in the row main decoder in FIG. 2;
4 is a diagram showing a relationship between potentials of an internal node S of a row main decoder and a plurality of control signals R1, R2, and R3 in the operation example of the circuit in FIG. 2;
FIG. 5 is a circuit diagram showing an example of a set of a row main decoder, a row sub-decoder, and a cell block in the EEPROM of the second embodiment of the present invention;
FIG. 6 is a block diagram showing a part of a NAND cell type EEPROM as an example of an EEPROM that performs reading, writing, and erasing independently in units of blocks;
7 is a circuit diagram showing a part of one set of a row main decoder, a row sub-decoder, and a cell block in FIG. 6;
8 is a diagram showing a list of voltages to be applied during data read / write / erase operations for the memory cells in FIG. 7; FIG.
[Explanation of symbols]
11 ... Memory cell array, 11i ... Cell block, 12 ... Row decoder, 12Mi ... Row main decoder, 12Si ... Row subdecoder, G1, G2, ..., G8 ... Input node, TG ... CMOS transfer gate, TP ... PMOS transistor, TN , Nd ... NMOS transistor, NAC ... NAND type cell, WL1-WL8 ... Word line, M1-M8 ... Non-volatile memory cell, Q1, Q2 ... Select transistor, BLi ... Bit line, CS ... Common source line, SL1, SL2 DESCRIPTION OF SYMBOLS ... Selection line, 70 ... NAND gate, 71 ... 1st inverter circuit, 72 ... 2nd inverter circuit, 73 ... Latch circuit, P ... 1st power supply node of a latch circuit, Q ... 2nd power supply node of a latch circuit .

Claims (3)

A plurality of cell blocks each having an array of electrically programmable and erasable nonvolatile memory cells;
A plurality of row main decoders provided corresponding to the plurality of cell blocks, for decoding a row address signal, and outputting a plurality of control signals whose potentials are set according to read / write / erase operation modes;
A plurality of row subs provided corresponding to the plurality of row main decoders and controlling reading / writing / erasing of data with respect to the nonvolatile memory cells of the corresponding cell block according to a control signal supplied from the corresponding row main decoder. A decoder,
The row main decoder includes a NAND gate that decodes a row address signal, a first inverter circuit that inverts the output of the NAND gate, an output of the first inverter circuit that is inverted, and a second control signal that is output. 2 inverter circuits and a latch circuit that latches the outputs of the two inverter circuits. The latch circuit is connected in series between a first power supply node and a second power supply node. PMOS transistor and first NMOS transistor, and a second PMOS transistor and a second NMOS transistor connected in series between the first power supply node and the ground node, and the first NMOS transistor The output of the first inverter circuit is input to the gate of the second NMOS transistor, and the gate of the second NMOS transistor The output of the second inverter circuit is inputted, the series connection point of the first PMOS transistor and the first NMOS transistor is connected to the gate of the second PMOS transistor, and a third control signal is taken out. The series connection point of the second PMOS transistor and the second NMOS transistor is connected to the gate of the first PMOS transistor and the first control signal is taken out. The first power supply node has a power supply potential. or higher first potential is switched supply, said the second power supply node the power supply potential or a ground potential is switched supplied, when paired selectively erased when / write non-selected response to the cell block, the first ground potential the potential of the control signal, the power source potential the potential of the second control signal, the potential of the third control signal first It was set at a potential, corresponding the the erasing unselected / write select of the cell block to the first potential of the first potential of the control signal, the second potential ground potential of the control signal, the third control signal Is set to a second potential higher than the power supply potential or ground potential ,
The row sub-decoder is an input node to which a predetermined voltage is supplied in accordance with each operation mode of read / write / erase and selection / non-selection of a word line connected to a control gate of a memory cell of a corresponding cell block And a CMOS transfer gate inserted and connected between the input node and one end of the corresponding word line, and connected between the one end of the word line and the ground node. The third control signal is applied to the gate of the PMOS transistor of the CMOS transfer gate, and the second control signal is applied to the gate of the pull-down NMOS transistor. Applied to the NMOS transistor of the CMOS transfer gate. Nonvolatile semiconductor memory, wherein the first control signal is applied to the chromatography bets. A plurality of cell blocks each having an array of electrically programmable and erasable nonvolatile memory cells;
A plurality of row main decoders provided corresponding to the plurality of cell blocks, for decoding a row address signal, and outputting a plurality of control signals whose potentials are set according to read / write / erase operation modes;
A plurality of row subs provided corresponding to the plurality of row main decoders and controlling reading / writing / erasing of data with respect to the nonvolatile memory cells of the corresponding cell block according to a control signal supplied from the corresponding row main decoder. A decoder,
The row main decoder includes a NAND gate that decodes a row address signal, a first inverter circuit that inverts the output of the NAND gate, an output of the first inverter circuit that is inverted, and a second control signal that is output. and second inverter circuit consists of a latch circuit for latching the output of the two inverter circuit, the latch circuit includes a first connected in series between a first power supply node and a second power supply node One PMOS transistor, a depletion-type first NMOS transistor, a second PMOS transistor whose power supply potential is supplied to the substrate region, and the first power supply node and the ground node are connected in series. A third PMOS transistor and an enhancement type second NMOS transistor, wherein the first NMOS transistor The output of the first inverter circuit is input to the gate of the transistor, the output of the second inverter circuit is input to the gate of the second NMOS transistor and the gate of the second PMOS transistor, and the first A series connection point of the PMOS transistor and the first NMOS transistor is connected to the gate of the third PMOS transistor and a third control signal is taken out, and the series connection of the third PMOS transistor and the second NMOS transistor is connected. The point is connected to the gate of the first PMOS transistor and a first control signal is taken out. A power supply potential or a first potential higher than the first power supply node is switched and supplied to the first power supply node. The power supply node is switched and supplied with the power supply potential or the ground potential, and the corresponding cell block is supplied. When the erase is selected / not programmed, the potential of the first control signal is set to the ground potential, the potential of the second control signal is set to the power supply potential, and the potential of the third control signal is set to the first potential. When the corresponding cell block is not erased / programmed, the potential of the first control signal is the first potential, the potential of the second control signal is the ground potential, and the potential of the third control signal is the potential of the third control signal. Set to a second potential higher than the power supply potential or ground potential,
The row sub-decoder is an input node to which a predetermined voltage is supplied in accordance with each operation mode of read / write / erase and selection / non-selection of a word line connected to a control gate of a memory cell of a corresponding cell block And a CMOS transfer gate inserted and connected between the input node and one end of the corresponding word line, and connected between the one end of the word line and the ground node. The third control signal is applied to the gate of the PMOS transistor of the CMOS transfer gate, and the second control signal is applied to the gate of the pull-down NMOS transistor. Applied to the NMOS transistor of the CMOS transfer gate. Nonvolatile semiconductor memory, wherein the first control signal is applied to the chromatography bets. Before Symbol row main decoder, the erasing selected time or write select the corresponding cell block, wherein the said second power supply node with a power supply potential to the first power supply node is supplied is supplied with the ground potential, after this 3. The nonvolatile memory according to claim 1, wherein the first power supply node is switched from a power supply potential to the first potential , and then the second power supply node is switched from a ground potential to a power supply potential . Semiconductor memory.

Images