JPH1139213A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the correction of a program by connecting directly a CPU to a correction data register for a designated correction bit and then connecting directly the CPU to a peripheral device control register for other bits. SOLUTION: The address of a desired peripheral device control register (SFR) 11 to be corrected is stored in a correction address register 12, the data to be corrected are stored in a correction data register 13, and the data which designate the bit position of the desired SFR 11 to be corrected are stored in a correction bit register 14 respectively. A CPU 10 executes an instruction to read the address of the SFR 11 out of the register 12, and a coincidence detection signal 15a is outputted from a coincidence circuit 15. Thus, the switch circuits 180 to 18n are controlled by the output signals 17a0 to 17an of the decided AND circuits 170 to 17n . Then the CPU 10 is separated from a data bus 5 and connected to the register 13 only for the bit that is designated toy the register 14, and the correction data are sent to the CPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a program correcting function.

[0002]

2. Description of the Related Art FIG.
FIG. 5 is a block diagram showing a conventional microcomputer disclosed in Japanese Patent Application Laid-Open Publication No. HEI 10-125, and FIG. 5 is a conceptual diagram showing a program change process of a read-only memory. In the figure, 1 is a processor, 2 is a read only memory (hereinafter referred to as ROM), 3 is a random access memory (hereinafter referred to as RAM), 4 is an address bus, and 5 is a data bus.

Next, the operation will be described. In the microcomputer shown in FIG. 4, the processor 1 operates in accordance with the program stored in the ROM 2 and the address bus 4
And data processing while storing data in the RAM 3 via the data bus 5. This ROM 2
There is a method of using a RAM 3 in which a mask ROM for printing a program in a manufacturing process is used. When a defect is found in the program, the ROM 2 does not need to be replaced.

FIG. 5 shows the method, and a ROM
In the case where there is a program requiring modification in the RAM 2, a jump instruction "JMP ABC" to the address ABC of the RAM 3 storing the modification program is written, and a jump instruction "JMP DEF to the next address DEF of the ROM 2" is written at the end of the modification program in the RAM 3. If "" is written, the program flow in the ROM 2 can be corrected even after the mask ROM is burned by changing the flow of the program.

[0005]

Since the conventional microcomputer is configured as described above, the problem of the program in the ROM 2 is corrected by changing the program flow using the RAM 3.
In addition to occupying the memory area, there are problems such as an increase in the program amount and an increase in the processing time of the program due to a change in the program flow.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and uses a random access memory to eliminate a program defect that occurs when reading data from a built-in peripheral device, for example, processing of an indefinite bit. It is an object of the present invention to obtain a microcomputer which can correct a program without changing the flow of the program without changing the program flow.

[0007]

According to a first aspect of the present invention, there is provided a microcomputer including a correction address register for specifying a correction address of a peripheral device control register, a correction data register for specifying correction data, and a correction for specifying a correction bit. A bit register, a match circuit that outputs a match detection signal when an address input from the address bus in accordance with the operation of the central processing unit matches the correction address specified in the correction address register, At the time of output, the correction bit specified in the correction bit register is connected to the central processing unit and the correction data register, and the other bits are connected to the central processing unit and the peripheral device control register via the data bus. And a selection circuit.

According to a second aspect of the present invention, there is provided a microcomputer including a correction instruction address register for specifying an address of a correction instruction of a program, an address input from an address bus according to the operation of the central processing unit, and a correction address register. And a first match circuit that outputs a match detection signal when the match is made with the corrected address specified by the addressing unit, and outputs a match end signal when the match ends, and an address bus according to the operation of the central processing unit. The second match circuit, which outputs a match detection signal when the address input from the address matches the address of the correction instruction specified in the correction instruction address register, matches the first match circuit and the second match circuit When the detection signal is output, the central processing unit and the correction data register determine the correction bit specified in the correction bit register. Connect, when the output of the other bit or the first matching circuit matches end signal, in which a selection circuit connected to the peripheral device control register via the central processing unit and a data bus.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention. In FIG. 1, reference numeral 4 denotes an address bus, reference numeral 5 denotes a data bus, and reference numeral 10 denotes a read-only memory (hereinafter referred to as a ROM). A CPU (Central Processing Unit) 11 that operates based on a program is an SFR (peripheral device control register) that controls peripheral devices. A correction address register 12 has the same bit length as the address bus 4 and specifies the correction address of the SFR 11, a correction data register 13 has the same bit length as the data bus 5 and specifies the correction data of the SFR 11, and 14 It has the same bit length as data bus 5 and
This is a correction bit register for specifying a correction bit of FR11.

A matching circuit 15 outputs a match detection signal 15a when an address input from the address bus 4 and a corrected address specified in the corrected address register 12 match according to the operation of the CPU 10, and 16 is a matching circuit. 1
5 outputs the coincidence detection signal 15a, the modified bit specified in the modified bit register 14 is
The PU 10 and the correction data register 13 are connected, and the other bits are connected to the CPU 10 and the data bus 5 via the data bus 5.
This is a selection circuit connected to FR11.

FIG. 2 is a circuit diagram showing the details of the selection circuit. 17 _{0 to} 17 _n are provided by the same number as the bit length of the data bus 5, and each of the match detection signal 15 a and the correction bit register 14 is designated. aND circuit which takes a logical product of the modified bit (0 to n), each by 17 _a0 to 17 _an, output signals of the aND circuits _{17 0 ~17 n, 18 0 ~18} n their output signals 17 _a0 to 17 _an, The CPU 10 and the correction data register 13 are connected for each bit, or
This is a switch circuit for selecting whether to connect the U10 and the data bus 5.

Next, the operation will be described. First, the address of the SFR 11 to be corrected is stored in the correction address register 12, the data to be corrected is stored in the correction data register 13, and the data specifying the bit position of the SFR 11 to be corrected is stored in the correction bit register 14. In the CPU 10, R
During execution of the program burned into the OM, if an instruction to read out the SFR 11 at the address stored in the correction address register 12 is executed, the matching circuit 1
5 outputs a coincidence detection signal 15a.

The AND circuits 17 _{0 to} 17 _{n are} determined by the coincidence detection signal 15 a and the read value of the correction bit register 14.
Output signals 17 _{a0 to} 17 _an are determined. The switch circuits 18 ₀ to 18 _n are controlled by the output signals 17 _{a0 to} 17 _an , and only the bits designated by the correction bit register 14 are CP
The correction data is sent to the CPU 10 by disconnecting the data bus 5 from the U 10 and connecting it to the correction data register 13. The AND circuits 17 _{0 to} 17 _n output the coincidence detection signal 15a and output the corrected bit register 1
When the bit is designated in 4, the data bus 5 is disconnected from the CPU 10 and connected to the correction data register 13.

As described above, according to the first embodiment, the program is corrected without using the RAM and without changing the flow of the program by correcting the problem of the bit processing for the specific SFR 11. be able to.

Embodiment 2 FIG. 3 is a block diagram showing a microcomputer according to the second embodiment of the present invention. In FIG. 3, reference numeral 20 denotes a microcomputer having the same bit length as the data bus 5 and indicating an address of a correction instruction in a program operated by the CPU 10. This is the modification instruction address register to be specified. 21 outputs a match detection signal 21a when the address input from the address bus 4 matches the correction address specified in the correction address register 12 according to the operation of the CPU 10, and ends the match when the match ends. A first matching circuit that outputs a signal 21b, 22 is C
When the address input from the address bus 4 in accordance with the operation of the PU 10 matches the address of the correction instruction specified in the correction instruction address register 20, the match detection signal 2
2a is a second matching circuit that outputs 2a.

Reference numeral 23 denotes a latch circuit which is set by a match detection signal 22a of the second match circuit 22 and reset by a match end signal 21b of the first match circuit 21.
An AND circuit 24 calculates the logical product of the coincidence detection signal 21a and the output of the latch circuit 23 and outputs the coincidence detection signal 15a. The selection circuit 16 in FIG. 3 is the same as that shown in FIG. 2, but the coincidence detection signal 15a in FIG.
In the second embodiment, the output of the AND circuit 24, that is,
This is a signal when the coincidence detection signal 21a becomes valid.
Other configurations are the same as those in FIG.

Next, the operation will be described. Embodiment 1
Similarly, the data is stored in the correction address register 12, the correction data register 13, and the correction bit register 14, and in addition, the correction instruction address register 20 stores the address indicating the instruction in the program to be corrected. CPU
When the instruction of the address stored in the modified instruction address register 20 is executed during the execution of the program burned in the ROM at 10, the latch circuit 23 is set by the output of the match detection signal 22a of the second match circuit 22, and the match detection is performed. The signal 21a becomes valid.

At this time, when an instruction for performing a read process is executed on the SFR 11 of the address stored in the correction address register 12, the match detection signal 21a becomes valid for the selection circuit 16, and the same as in the first embodiment. And only the bits specified in the correction bit register 14 are CP
The correction data is sent to the CPU 10 by disconnecting the data bus 5 from the U 10 and connecting it to the correction data register 13. When the match between the address stored in the modified address register 12 and the address on the address bus 4 ends, the first match circuit 21 outputs a match end signal 21b,
By resetting the latch circuit 23, the coincidence detection signal 21a becomes invalid.

As described above, according to the second embodiment, by correcting the problem of bit processing for an arbitrary SFR 11 in an arbitrary instruction in a program burned into a ROM, a RAM is not used, In addition, the program can be modified without changing the flow of the program.

[0020]

As described above, according to the first aspect of the present invention, the address input from the address bus according to the operation of the central processing unit matches the correction address specified in the correction address register. A match circuit that outputs a match detection signal when the match detection signal is output, and connects the central processing unit and the correction data register for the correction bit specified in the correction bit register when the match detection signal is output; Since it is configured to include an arithmetic processing unit and a selection circuit connected to a peripheral device control register via a data bus, it is possible to use a random access memory by correcting a bit processing defect for a specific peripheral device control register. And the program can be modified without changing the program flow.

According to the second aspect of the present invention, a match detection signal is output when the address input from the address bus matches the correction address specified in the correction address register according to the operation of the central processing unit. A first match circuit that outputs a match end signal when the match ends, an address input from an address bus according to the operation of the central processing unit, and a correction instruction specified in the correction instruction address register. The second match circuit that outputs a match detection signal when the address matches, and the first match circuit and the second match circuit output the match detection signal when the match bit specified in the match bit register is output. The central processing unit is connected to the correction data register, and when the other bits or the first matching circuit outputs a match end signal, the central processing unit is connected. And a selection circuit connected to the peripheral device control register via the data bus, so that there is a defect in bit processing for an arbitrary peripheral device control register in an arbitrary instruction in a program burned into the read-only memory. Has the effect that the program can be modified without using the random access memory and without changing the flow of the program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a selection circuit.

FIG. 3 is a block diagram showing a microcomputer according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional microcomputer.

FIG. 5 is a conceptual diagram showing a program change process of a read-only memory.

[Explanation of symbols]

4 address bus, 5 data bus, 10 CPU (central processing unit), 11 SFR (peripheral device control register), 12 correction address register, 13 correction data register, 14 correction bit register, 15 matching circuit, 16 selection circuit, 20 Correction instruction address register, 21 first match circuit, 22 second match circuit.

Claims (2)

[Claims] 1. A central processing unit that operates based on a program stored in a read-only memory, a peripheral device control register connected to the central processing unit by an address bus, and a modified address of the peripheral device control register. , A correction data register that specifies correction data of the peripheral device control register, a correction bit register that specifies a correction bit of the peripheral device control register, and a correction bit register that specifies the correction bit of the peripheral device control register. A match circuit that outputs a match detection signal when the address input from the address bus matches the correction address specified in the correction address register; and, when the match circuit outputs a match detection signal, Regarding the correction bits specified in the correction bit register, the central processing unit A microcomputer including a correction data register, and a selection circuit for connecting the other bits to the central processing unit and the peripheral device control register via a data bus. 2. A central processing unit that operates based on a program stored in a read-only memory, a peripheral device control register connected to the central processing unit by an address bus, and a modified address of the peripheral device control register. , A correction data register that specifies correction data of the peripheral device control register, a correction bit register that specifies correction bits of the peripheral device control register, and an address of a correction instruction of the program. Outputting a match detection signal when the address input from the address bus matches the correction address specified in the correction address register in accordance with the operation of the correction instruction address register and the central processing unit; A first match circuit that outputs a match end signal when the search has ended, A second matching circuit for outputting a match detection signal when an address input from the address bus matches an address of a correction instruction specified in the correction instruction address register in accordance with an operation of the central processing unit; When the first match circuit and the second match circuit output a match detection signal, the central processing unit and the correction data register are used for the correction bit specified in the correction bit register. A microcontroller including a central processing unit and a selection circuit connected to the peripheral device control register via a data bus when the other bit or the first match circuit outputs a match end signal. Computer.