JPH11235011A - Driving of gate/base of power semiconductor switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce time delay from a control signal of a turn-ON timing of power semiconductor to be controlled by perfectly turning ON the off-drive switch only for an extremely short period after application of off gate/base control signal and thereafter operating the switch with the threshold by the resistance between drain and gate. SOLUTION: A MOSFET is used for off-drive switch Soff and a resistor Rgd is connected between the drain and gate of the MOSFET. The MOSFET is perfectly turned ON only for an extremely short period immediately after application of off-gate/base control signal and Soff is then operated in the active area until turn ON of the semiconductor switch Q1 to be controlled. Thereby, when Q1 has turned OFF, the gate signal source of the MOSFET depends only on the resistor Rgd and Soff is driven by the gate threshold. Therefore, time delay from the control signal of the turn ON timing of the power semiconductor to be controlled can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT (insulated gate bipolar transistor) which is a voltage-driven element,
The present invention relates to a method for driving a gate / base of a power semiconductor switch such as an SI thyristor (static induction thyristor), a GTO (gate turn-off thyristor) which is a current-driven element, and a power transistor.

[0002]

2. Description of the Related Art A basic example of a conventional gate / base drive circuit for turning on / off a power semiconductor switch is shown in FIG. In FIG. 3, Q1 is a controlled power semiconductor switch that is turned on / off, and is indicated by GTO in FIG. E1 and E2 denote on-drive and off-drive DC power sources, respectively, and Son and Soff denote on-drive and off-drive switches, respectively. In the figure, P-channel MOSFET and N-channel MOSFET are used, respectively. Gate resistance Ro
It is controlled by the gate pulse generator PG through n and Roff. When turning off a GTO or the like, it is necessary to flow a large off-drawing current in a very short time. Recently, however, relatively low-voltage power MOSFETs that can flow a large current at a high speed have been available. Examples of use as an off-drive switch are increasing. This off-drive MOSFET applies a voltage considerably higher than the threshold value between the gate and the source of the MOSFET while the power semiconductor switch Q1 is off, so as to be in a sufficiently low resistance state.

[0003]

As shown in FIG. 3, the MOSFET used for the off-drive is a gate-source,
Capacitances Cgs, Cgd, Cds having relatively large capacitances between the gate and the drain and between the drain and the source, respectively
Exists, and the capacitance changes in the order of two digits depending on the voltage Vds between the drain and the source. The capacitance changes when Vds is low and decreases when Vds is high. Therefore, MOSFE
When T is turned on and Vds is sufficiently low, the capacitance (input capacitance Ciss = Cgs + Cgd) seen from the gate is very large and is several thousand PF or more. Therefore, in order to turn off the MOSFET, the charge stored in this capacitor must be discharged. Therefore, the higher the charged voltage, that is, the gate-source voltage Vgs, the longer the time required for discharging, and the gate circuit condition However, the turn-on time is as long as several hundred nsec. On the other hand, in the off state, Cg
d is as small as several tens of PF, and the turn-on time is less than half the turn-off time.

If the turn-off time is several hundred nsec, a time delay from application of a control signal to turn-on of the power semiconductor switch Q1, which is a controlled element, is not allowed.
For example, it is inconvenient to perform so-called zero voltage switching (ZVS) in which a semiconductor switch Q1 is turned on when the semiconductor switch Q1 reaches a minimum voltage including zero in a resonant inverter. Another problem is that the turn-off time of the MOSFET is longer than the turn-on time as described above. That is, when the controlled semiconductor switch Q1 is turned on, the off drive switch Soff is turned off,
It is necessary to turn on the ON drive switches Son at the same time or with a slight delay. However, if both switches are driven by the same signal, the ON state of both switches wraps due to the difference in turn-on and turn-off times, causing a large crossover from the DC power supply A current flows, increasing the loss of both switches, not only increasing the operating frequency, but also destroying the switches. For this reason, gate pulses for driving both switches are separated from each other, and a time difference is made between them, so that the gate pulse generator is complicated.

The present invention has been proposed in order to solve the above-mentioned problems, and an object of the present invention is to shorten the turn-off time of an off drive switch Soff,
It is an object of the present invention to provide a gate / base drive circuit that can reduce the delay of turn-on of the controlled power semiconductor switch Q1, suppress switch loss and the like, and increase the operating frequency.

[0006]

In order to achieve the above object, the present invention provides a positive / negative DC power supply in which a power semiconductor switch in which an ON drive switch and an OFF drive switch are connected in series is connected. Are connected in parallel to both ends of the power semiconductor switch.
In a circuit in which a connection point of the DC power supply is connected to a cathode / emitter of the power semiconductor switch on a base, a MOSFET is used for the off drive switch, and a drain and a gate of the MOSFET are connected to each other. The MOSFET is completely turned on for a very short time (time until the gate / base off current becomes zero) immediately after the application of the off-gate / base control signal, and thereafter, the resistance between the drain and the gate is turned off. MOSFE
Operate T at the threshold.

That is, when the controlled semiconductor switch Q1 is turned off, it is necessary to apply a reverse voltage to the gate / base and rapidly flow a large current so as to extract the charge accumulated around the gate / base. After the off capability is restored, no gate / base current flows. Therefore, the off-drive switch Soff only needs to be completely turned on for this period, and the Soff operates in the active region until the next turn-on of Q1. By doing so, after the turn-off of the controlled semiconductor switch Q1 is completed, the off-drive switch Soff M
The gate signal source of the OSFET is based solely on the resistance connected between the drain and the gate. By this, Soff
Is the base-source voltage V due to the MOSFET principle.
gs = drain-source voltage Vds, that is, driven by the gate threshold. For this reason, the turn-off delay time required for lowering the gate voltage to the threshold value when turning off the Soff becomes unnecessary, and the turn-off time becomes １ ／ or less.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operation explanatory diagram. In FIG. 1, Q1 is a semiconductor switch for controlled power to be turned on and off, and E1 and E2 are connected in series by a DC power supply for on and off driving, respectively.
off is a switch connected in series with an on / off drive switch, and is connected in parallel to the DC power supply.
The connection point of f and the connection points of E1 and E2 are connected to the gate / base and cathode / emitter of Q1, respectively.
In this embodiment, a P-channel MOSFET is used for Son and an N-channel MOSFET is used for Soff. Up to this point, it is the same as the conventional example, but there is a difference in the gate drive method of both switches.

An on / off gate pulse is commonly used as one signal, output from the buffer circuit BF, supplied to the gate of the on drive switch Son via a gate resistor Ron, and a differential capacitor C is connected to the gate of the off drive switch Soff. And a diode connected in parallel and a gate resistor Rof
f are supplied in series. Further, a resistor Rgd is connected between the series point and the drain of Soff. Here, the capacity of the differential capacitor C is larger than the input capacity Ciss of Soff (about twice or more), and the resistance Rgd
Is selected sufficiently larger than the gate resistance Roff (usually 10 ohms or less). The controlled semiconductor switch Q1 is turned on, ie, S
With on and Soff turned on and off respectively,
When a control signal is applied at time t0 shown in FIG. 2 and the output of the buffer circuit BF switches from “L” to “H”, a differentiating circuit formed by a differential capacitor C → a gate resistance Roff → Soff gate (input capacitance Ciss). Current flows through C
Charge the iss. At this time, since the resistance Rgd is very large as compared with Roff, it hardly affects the differential operation.

Since the capacity of C is larger than Ciss,
The charging voltage of Ciss becomes sufficiently high, that is, Soff is completely turned on, and the gate of the controlled semiconductor switch Q1 is turned on.
A large extraction current flows rapidly from the base. On the other hand, after the differentiation operation is completed, the Soff is completely turned on, so that the input capacitance Ciss of the Soff is discharged by the gate resistance Roff and the on-resistance of the resistance Rgd and the Soff, and the gate-source voltage Vgs of the Soff is discharged. Becomes lower and becomes closer to the threshold, the drain-source voltage Vds of Soff starts to increase, and Vgs = Vd
Equilibrate and stable at s. Therefore, as described above, the next So
At the time of ff turn-off, a turn-off delay time for lowering Vgs to a threshold is not required, so that the turn-off of Soff is quickened. Further, the differential capacitor C is further charged,
(E1 + E2-Vgs). When the control signal of the electric charge charged in the capacitor C changes at time t1 and the output of the buffer circuit switches from “H” to “L”, So
A reverse voltage will be applied between the gate and the source of ff,
This will help turn off Soff even faster.

As described above, the turn-off time of the Soff is shortened, and the turn-on time of the Son is approached, so that the simultaneous on-time of the Son and the Soff is eliminated. The delay of the turn-on timing of the controlled semiconductor switch from the signal can also be reduced. In the above description, as a method of increasing the gate voltage Vgs only immediately after the turn-off of the Soff, the description has been made using the differentiating circuit in the embodiment of FIG. 1, but any method may be used as long as the same effect can be obtained. GT controlled semiconductor switch Q1
Although described with O, it goes without saying that the present invention can be applied to semiconductor switches such as IGBTs, SI thyristors, and power transistors.

[0012]

As described above, according to the present invention,
The time delay from the control signal of the turn-on timing of the controlled power semiconductor can be reduced, and
There is an effect that generation of a large loss due to a crossover current due to simultaneous turning-on of the off-drive switches is suppressed and high-frequency operation is enabled.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation of FIG.

FIG. 3 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 Q1 ... Controlled power semiconductor switch E1 ... On DC power supply E2 ... Off DC power supply Son ... On drive switch Soff ... Off drive switch Ron, Roff ... Gate resistance BF ... Buffer circuit C …… Differential capacitor D …… Diode Rgd… Drain-gate resistance PG …… Signal generator

Claims (1)

[Claims] A power semiconductor switch in which an on-drive switch and an off-drive switch are connected in series is connected in parallel to both ends of a series-connected positive / negative DC power supply,
In a circuit formed by connecting a connection point of the switch to a gate / base of the power semiconductor switch and a connection point of the DC power supply to a cathode / emitter of the power semiconductor switch, A MOSFET is used for the switch, a resistor is connected between the drain and the gate of the MOSFET, and the MOSFET is turned on for an extremely short time (gate / gate) immediately after the off-gate / base control signal is applied.
(The time until the base-off current becomes zero), and then completely turns on.
A gate / base driving method for a power semiconductor switch, comprising operating an SFET at a threshold value.