JP3430878B2 - MOS gate type element driving circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a MOS gate type element such as an IGBT or a power MOSFET which constitutes a main circuit of a semiconductor power converter.

[0002]

2. Description of the Related Art In a semiconductor power converter (hereinafter, simply referred to as a power converter), in recent years, due to various legal regulations, this occurs along with the switching operation of the MOS gate type element constituting the power converter. It is required to reduce noise. FIG. 5 is a circuit configuration diagram showing a conventional example of this type of power converter.

In FIG. 5, 1 is an MO of this power converter.
IGBT as S gate type element, 2 is inductive load, 3
Represents a wheeling diode of the inductive load 2, power is supplied to the inductive load 2 on the basis of the main circuit power supply (V _M) to IGBT1 on and off, the inductive load 2 current when IGBT1 is turned off It flows to the free wheeling diode 3. The drive circuit 10 for turning on / off the IGBT 1 includes a P-channel MOSFET 11 and an N-channel MOSFET 12 which are connected in series between the drive circuit power supply (V _DD ) shown in the figure and the emitter terminal of the IGBT 1, and an N-channel MO.
SFET 13 and MOSFET 11 based on the drive signal
Buffer elements 15 and 16, which control the elements 13 to 13, an AND element 17, and a control circuit 14 including a comparator 18.

The operation of the drive circuit 10 shown in FIG.
This will be described below with reference to the operation waveform charts shown in (A, B). FIG. 6A shows operation waveforms when an element having a relatively large on-resistance of the MOSFETs 11 and 12 is selected in order to suppress noise associated with the switching operation of the IGBT 1, and when the IGBT 1 is turned on, as shown in FIG.
By reducing the dV / dt of the gate voltage V _GE of the GBT 1, the collector current I _C of the IGBT 1 (thick solid line in the figure) and the collector-emitter voltage V _CE (thin solid line in the figure).
Is slowly changing.

Similarly, in FIG. 6 (A), the IGBT 1
At the time of turn-off, the gate voltage V _GE of the IGBT 1 is reduced dV / dt as shown in the figure to moderate the changes in the collector current I _C and the collector-emitter voltage (V _CE ) of the IGBT 1. On the other hand, FIG. 6 (B) shows the MOSFET 1 in order to speed up the switching operation of the IGBT 1.
The operation waveforms when the elements having a relatively low on-resistance of 1 and 12 are selected are shown, and when the IGBT1 is turned on, the gate voltage V _GE of the IGBT1 is increased to increase dV / dt so that the collector current I _{C of the} IGBT 1 ( (Thick solid line shown) and collector-emitter voltage V _CE (thin solid line shown)
As a result, an oscillating phenomenon occurs in the collector current I _C during turn-on of the IGBT 1, and this oscillation and the changes in I _C and V _CE of the IGBT 1 serve as a noise source.

Similarly, in FIG. 6B, the IGBT 1
At the time of turn-off, the gate voltage V _GE of the IGBT 1 is increased as shown to increase the collector current I _{C of the} IGBT 1 and the collector-emitter voltage V _CE quickly. As shown in the figure, a vibration phenomenon occurs in the collector-emitter voltage V _CE , and this vibration and changes in I _C and V _CE of the IGBT 1 become noise sources.

The comparator 18 shown in FIG. 5 operates when the drive signal changes and the gate voltage V _GE drops to V _G2 (see FIGS. 6A and 6B), and as a result, the AND element. 1
7 turns on the MOSFET 13 to turn on the gate voltage V _GE
Of the IGBT 1 is accelerated, the turn-off time of the IGBT 1 is shortened, and the turn-off time is maintained. When the IGBT 1 is turned on, the MOSFET 13 is turned off via the AND element 17 by the input of the ON drive signal regardless of the output of the comparator 18.

[0008]

As described above, in the conventional drive circuit 10, the elements having relatively large on-resistances of the MOSFETs 11 and 12 are selected in order to suppress noise accompanying the switching operation of the IGBT 1. As a result, the drive signal changes, the gate voltage V _GE rises to V _G1 , and I
Time until GBT1 starts to turn on (Fig. 6
(A) T ₁ ) is longer than T ₃ in FIG. 6B,
Similarly, the time (T _{2 in} FIG. 6A) until the drive signal changes and the IGBT 1 starts to turn off is shown in FIG. 6B.
There was a problem that it became longer than T ₄ of.

An object of the present invention is to solve the above problems and shorten both the turn-on time and the turn-off time of the MOS gate type element that constitutes the main circuit of the power converter, or either the turn-on time or the turn-off time. While
It is an object of the present invention to provide a drive circuit that suppresses noise accompanying switching operation of the MOS gate type element.

[0010]

The first aspect of the present invention is a drive circuit for a MOS gate type element constituting a main circuit of a semiconductor power converter, wherein the drive circuit includes a first transistor and a second transistor. A third transistor, a fourth transistor, and a control circuit are provided, and the first transistor and the second transistor are connected in series between one end of the power source of the drive circuit and the source terminal or the emitter terminal of the MOS gate type element. In addition, the third transistor and the fourth transistor are connected in series, the connection point of the first transistor and the second transistor, the connection point of the third transistor and the fourth transistor, and the gate terminal of the MOS gate type element. And the control circuit alternately turns on the first transistor and the second transistor based on the input drive signal.
The third transistor is turned on with a predetermined amplitude only for a predetermined period from when the first transistor is turned off and the first transistor is turned on, and the second transistor is turned on for a predetermined period and the second period.
It is assumed that the fourth transistor is turned on when the gate voltage of the MOS gate type element becomes equal to or lower than a predetermined value based on the turning on of the transistor.

A second invention is a drive circuit for a MOS gate type element which constitutes a main circuit of a semiconductor power converter, wherein the drive circuit includes a first transistor, a second transistor, a third transistor and a control circuit. And a first transistor and a second transistor connected in series between one end of the power source of the drive circuit and the source terminal or the emitter terminal of the MOS gate type element, and the first transistor and the second transistor.
The connection point of the transistor and the gate terminal of the MOS gate type element are connected, the third transistor is connected in parallel to both ends of the first transistor, and the control circuit is configured to connect the first transistor and the second transistor based on the input drive signal. The transistor and the transistor are alternately turned on and off, and the third transistor is turned on with a predetermined amplitude for a predetermined period from when the first transistor is turned on.

A third aspect of the present invention is a drive circuit for a MOS gate type element constituting a main circuit of a semiconductor power converter, wherein the drive circuit includes a first transistor, a second transistor, a third transistor and a control circuit. And a first transistor and a second transistor connected in series between one end of the power source of the drive circuit and the source terminal or the emitter terminal of the MOS gate type element, and the first transistor and the second transistor.
The connection point of the transistor and the gate terminal of the MOS gate type element are connected to each other, the third transistor is connected in parallel to both ends of the second transistor, and the control circuit controls the first transistor and the second transistor based on the input drive signal. The gate voltage of the MOS-gated element becomes less than or equal to a predetermined value based on turning on and off the transistor alternately and turning on the second transistor for a predetermined period from turning on the second transistor. Sometimes the third transistor is turned on.

According to the present invention, as will be described later, while shortening both the turn-on time and the turn-off time of the MOS gate type element which constitutes the main circuit of the power converter, or either one of the turn-on time and the turn-off time, The MO
Noise associated with the switching operation of the S-gate element can be suppressed.

[0014]

1 is a circuit configuration diagram of a power converter showing a first embodiment of the present invention, and those having the same functions as those of the conventional circuit shown in FIG. Attached. That is, in FIG. 1, the drive circuit 2 of the IGBT 1
0 is a P-channel MOSF as the first transistor
ET21 and N-channel M as the second transistor
OSFET 22, N-channel MOSFET 23 as a third transistor, and N as a fourth transistor
A channel MOSFET 24 and a control circuit 25 are provided. The control circuit 25 includes buffer elements 26 and 27, an inversion element 28, and one-shot circuits 29 and 30 that operate for a predetermined time at the rising edge of a signal input thereto and a comparator 31.
And an AND element 32 and an OR element 33.

The operation of the drive circuit 20 shown in FIG.
A description will be given below with reference to the operation waveform diagram shown in FIG. In addition, the MOSFET 21 for realizing the operation waveform of FIG.
As a selection condition of 24 to 24, the MOSFETs 21 and 22 are elements having a relatively large on-resistance, and the MOSFETs 23 and 2 are
The element 4 has a relatively small on-resistance.

First, when the drive signal (see FIG. 2A) changes from High to Low as shown and an ON command is issued to the IGBT 1, the MOSFET 21 is turned on by the buffer element 26 (see FIG. 2B). Then, the one-shot circuit 29 (see FIG. 2C) turns on the MOSFET.
23 is also turned on by the gate voltage of the amplitude V _H , and as a result, the gate voltage V _{GE of the} IGBT 1 (see FIG. 2E) rises rapidly and exceeds the threshold value V _G1 of the IGBT 1 for a flat period (the mirror capacitance of the IGBT 1). Charging period),
The IGBT1 starts the turn-on operation.

During this mirror capacitance charging period, the time period T ₂ of the one-shot circuit 29 is set to be slightly larger than T ₁ as shown in the figure, and the amplitude V _H is set to a value that does not exceed the threshold V _G1 of the IGBT 1. M to charge the gate capacitance during T ₁
The OSFETs 21 and 23 contribute to reduce this time. After that, as the gate voltage of the IGBT1 approaches V _G1 , the gate-source voltage of the MOSFET 23 becomes MO.
The IGBT1 is turned off as it approaches the threshold value of the SFET23.
In a region where the gate voltage of V _G1 is V _G1 or more, only the MOSFET 21 is turned on. As a result, as shown in the figure, the IGBT 1
DV / dt of the gate voltage V _GE of
The collector current I _C (thick solid line in FIG. 2G) and the collector-emitter voltage V _CE (thin solid line in FIG. 2G) change gradually.

Next, when the drive signal (see FIG. 2 (a)) changes from Low to High as shown and an off command is issued to the IGBT 1, the buffer element 27 (see FIG. 2 (b)) turns on the MOSFET 22. Then, the one-shot circuit 30 and the OR element 33 (see FIG. 2D) also turn on the MOSFET 24. As a result, I
The gate voltage V _{GE of the} IGBT 1 (see FIG. 2 (E)) rapidly falls, and the IGBT 1 starts the turn-off operation while leaving a slight flat period (the mirror capacitance discharge period of the IGBT 1).

This mirror capacity discharge period can be shortened by setting the time period T ₃ of the one-shot circuit 30 as shown in the figure. After reaching the time period T ₃ of the one-shot circuit 30, only the MOSFET 22 is temporarily turned on. As a result, the gate voltage V _{GE of the} IGBT 1 is turned on as shown in the figure.
DV / dt becomes smaller, and the collector current I _{C of the} IGBT 1 (thick solid line in FIG. 2G) and the collector-emitter voltage V _CE (thin solid line in FIG. 2G) change gradually.

The comparator 31 shown in FIG. 1 operates when the drive signal changes and the gate voltage V _GE drops to V _G2 (see FIG. 2 (E)). The MOSFET 24 is turned on again via the OR element 33 to accelerate the fall of the gate voltage V _GE , shorten the turn-off time of the IGBT 1 and hold it off.
When the IGBT 1 turns on, the comparator 3
Irrespective of the output of No. 1, the input of the ON drive signal causes the MOSFET 24 to pass through the AND element 32 and the OR element 33.
Turns off.

FIG. 3 is a circuit configuration diagram of a power converter showing a second embodiment of the present invention. Components having the same functions as those of the first embodiment circuit shown in FIG. 1 are designated by the same reference numerals. is doing. That is, in FIG. 3, the drive circuit 40 of the IGBT 1
Is a P-channel MOSFE as the first transistor
T21 and N-channel MO as the second transistor
An SFET 41, an N-channel MOSFET 23 as a third transistor, and a control circuit 42 are provided.
The control circuit 42 includes buffer elements 26 and 43, an inverting element 28, and a one-shot circuit 29. The ON resistance of the MOSFET 41 is selected to be a relatively small value or a general value. In this drive circuit 40, the turn-on operation of the IGBT 1 is made gentle and the turn-off operation is made faster, similar to the operation waveform of the left half surface of FIG. For example, in a power converter such as an inverter (not shown), it is suitable for further reducing noise at the time of reverse recovery of a diode antiparallel to a MOS gate type element.

FIG. 4 is a circuit configuration diagram of a power converter showing a third embodiment of the present invention. Components having the same functions as those of the first embodiment circuit shown in FIG. 1 are designated by the same reference numerals. is doing. That is, in FIG. 4, the drive circuit 50 of the IGBT 1
Is a P-channel MOSFE as the first transistor
T51 and N-channel MO as the second transistor
It is provided with an SFET 22, an N-channel MOSFET 24 as a third transistor, and a control circuit 52.
The control circuit 52 includes buffer elements 27 and 53, a one-shot circuit 30, a comparator 31, an AND element 32,
It is composed of an OR element 33. In addition, MOSFE
The on resistance of T51 is selected to be a relatively small value or a general value.

In the drive circuit 50, the turn-off operation of the IGBT 1 is made gentle and the turn-on operation is made faster, as in the operation waveform on the right half surface of FIG. For example, it is suitable for an application in which only turn-off of a MOS gate type element is desired to be more gradual.

[0024]

According to the present invention, both the turn-on time and the turn-off time of the MOS gate type element which constitutes the main circuit of the power converter such as the inverter and the switching regulator, or either one of the turn-on time and the turn-off time is set. It is possible to suppress the noise due to the switching operation of the MOS gate type element while shortening it.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a conventional example.

6 is a waveform diagram illustrating the operation of FIG.

[Explanation of symbols]

1 ... IGBT, 2 ... inductive load, 3 ... freewheeling diode,
10, 20, 40, 50 ... Driving circuits 11 to 13, 21
~ 24, 41, 51 ... MOSFET, 14, 25, 4
2, 52 ... Control circuit.

Claims (3)

(57) [Claims] 1. An MO constituting a main circuit of a semiconductor power converter.
A drive circuit for an S-gate type element, the drive circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor and a control circuit, wherein one end of a power source of the drive circuit and the MOS gate type The first transistor and the second transistor are connected in series between the source terminal or the emitter terminal of the element, and the third transistor
A transistor and a fourth transistor are connected in series, and a connection point between the first transistor and the second transistor and a third transistor
The connection point between the transistor and the fourth transistor, and the MOS
The gate terminal of the gate-type element is connected to the control circuit, and the control circuit alternately turns on and off the first transistor and the second transistor based on the input drive signal, and a predetermined time has passed since the first transistor was turned on. The third transistor is turned on with a predetermined amplitude only for a period, and the gate voltage of the MOS gate type element is equal to or less than a predetermined value based on the second transistor being turned on for a predetermined period from when the second transistor is turned on. A drive circuit for a MOS gate type element, wherein the fourth transistor is turned on when it is turned on. 2. An MO constituting a main circuit of a semiconductor power converter.
A driving circuit for an S-gate type element, wherein the driving circuit includes a first transistor, a second transistor, a third transistor and a control circuit, one end of a power source of the driving circuit and a source terminal of the MOS gate type element. Alternatively, a first transistor and a second transistor are connected in series between an emitter terminal and a connection point between the first transistor and the second transistor and the M
The gate terminal of the OS gate type element is connected, the third transistor is connected in parallel to both ends of the first transistor, and the control circuit alternately turns on the first transistor and the second transistor based on the input drive signal. A drive circuit for a MOS gate type element characterized in that the third transistor is turned on with a predetermined amplitude only for a predetermined period from when the first transistor is turned off and when the first transistor is turned on. 3. An MO constituting a main circuit of a semiconductor power converter.
A driving circuit for an S-gate type element, wherein the driving circuit includes a first transistor, a second transistor, a third transistor and a control circuit, one end of a power source of the driving circuit and a source terminal of the MOS gate type element. Alternatively, a first transistor and a second transistor are connected in series between an emitter terminal and a connection point between the first transistor and the second transistor and the M
The gate terminal of the OS gate type element is connected, the third transistor is connected in parallel to both ends of the second transistor, and the control circuit alternately turns on the first transistor and the second transistor based on the input drive signal. The M based on the second transistor being turned on for a predetermined period from when the second transistor was turned off.
A drive circuit for a MOS gate type element, wherein a third transistor is turned on when the gate voltage of the OS gate type element becomes equal to or lower than a predetermined value.