JPH11143777A - Cache memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory device for executing a processing for performing access only to a tag memory at the time of writing a block data of cache from a low order memory. SOLUTION: At the time of writing block data (128B) from a low order memory 103 in a data memory 101 during the execution of a processing of a load instruction controller 107 or a store instruction controller 108, the data are written by each 32B four times, and a valid bit is written in a tab memory 102 at the time of the first 32B writing, and a valid bit and a real page number are written in the tab memory 102 at the time of the last 32B writing, and writing in the tag memory 102 is not operated at the time of the second and third 32B writing. Then, when a processing request from processors (for example, 106 and 109 or the like) for operating a processing to be completed by performing access only to the tag memory is issued, a tag memory arbiter applies permission to the processors so that the processing can be attained at the time of the second and third 32B writing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device, and more particularly, to a cache memory device with an increased throughput.

[0002]

2. Description of the Related Art Many of today's information processing apparatuses employ a cache memory device in order to improve a memory access time. The cache memory has, for each block specified by the block address of the cache, data for judging the cache hit, a bit indicating the attribute of the cache block, and a bit indicating that the cache block is valid. Store in memory. On the other hand, the cache data is stored in the data memory.

Generally, the block size of a cache memory is larger than the write data width of the cache memory. One reason for this is that increasing the block size increases the cache hit rate. In addition, cache memory is generally mounted on a processor chip, or in the case of an external processor, a high-speed and expensive RAM is used, and an interface between the lower-level memory and the cache memory is provided by a processor or an external RAM. The number of pins is limited. Therefore, the data width written from the lower memory to a certain block in the cache memory is physically limited.

As described above, since the block size is larger than the write data width to the cache, the block data of the cache is transferred from the lower memory to the data memory.
It is necessary to write in times. In this case, 1 to (n-
1) At the time of writing data to the cache for the first time, an invalid bit is written to the tag memory each time and a valid bit is written for the nth time, but invalid bits for the second to (n-1) th times are written. It is not necessary to write at least two times to the tag memory, that is, writing the invalid bit at the first time and writing the valid bit at the nth time. While data was being written to the cache, no other process accessed the tag memory.

[0005]

In the above-described conventional cache memory device, it is not possible to write cache block data from the lower memory and simultaneously process an instruction for accessing only the tag memory. was there. The present invention has been made in view of the above circumstances, and provides a cache memory device that can execute processing for accessing only a tag memory when writing cache block data from a lower memory. With the goal.

[0006]

To achieve the above object, the present invention provides a data memory for storing data, a tag memory for storing an address of data stored in the data memory, a plurality of processing controllers, A data memory arbiter and a tag memory arbiter. When data is fetched and stored, the data memory arbiter and the tag memory arbiter permit use of the data memory arbiter. When the data memory arbiter and the tag memory arbiter are permitted to use a processing control device that performs processing in which the number of cycles of writing data to the data memory is greater than the number of cycles of writing to the tag memory in the cache memory device accessing the tag memory, The tag memory arbiter stores data in the processing of the processing control device. The cycles to be written only in the data memory, so that comprising means for permitting the use of the tag memory arbiter processing apparatus for completing processing by accessing only the tag memory in the cycle to be written only to the data memory.

[0007] Further, in a cycle in which only the data memory is written in the processing of the processing control device, a processing device which performs a process completed by accessing only the tag memory is provided.
Performs a hit check process to determine whether a shared memory address sent from another processor exists in the cache or a process of accessing the tag memory to invalidate a cache block including a shared memory address sent from another processor. It is a processing device.

Further, in a cycle in which only the data memory is written in the processing of the processing control device, a processing device which performs a process completed by accessing only the tag memory is provided.
The processing device performs a process of accessing the tag memory for hit check of the store.

[0009]

FIG. 1 is a block diagram showing an embodiment of a cache memory device according to the present invention. In FIG. 1, 10 is a processor, 20 to 60 are processing controllers, 20 is a central controller, 30 is a prefetch instruction controller, 40 is a load instruction controller, 5
0 is a store command controller, 60 is a snoop controller, 7
0 is a cache memory, 101 is a data memory, 102
Is a tag memory, 103 is a lower memory, 104 is a data memory arbiter, 105 is a tag memory arbiter, 114 is a data memory address selector, and 115 is a tag memory address selector. Reference numeral 106 denotes a path between a prefetch instruction request and an address, 107 denotes a path between a load instruction request and an address, 108 denotes a path between a store instruction request and an address, 109 denotes a path between a snoop instruction request and an address, and 110 denotes a path between a snoop instruction request and an address. An external data path 111 is an external address path. 112 is a data memory select signal, 113 is a tag memory select signal, 114 is a data memory selector, 115 is a tag memory selector,
116 is a block address to the data memory, and 117 is a block address to the tag memory.

The cache memory 70 has a data memory 1
01 and a tag memory 102, and a data memory 101
Has a block size of 128 bytes and a capacity of 128 Kbytes. From lower memory 103 to data memory 101
The write data width to is 32 bytes, and the data memory 101 is accessed four times to write one block.

Here, as an embodiment, a case where a prefetch instruction is executed at the time of writing block data in a cache is described. The prefetch instruction only needs to access the tag memory 102 only. If there is a cache hit, the execution is terminated, and in the case of a cache miss, an operation of issuing a cache block data request to the lower memory 103 is performed. In this embodiment,
The case where the process of accessing the tag memory 102 is a hit check of a prefetch instruction has been described. However, the processes of accessing only the tag memory 102 may be performed by using a snoop hit check, invalidating a cache block by snoop, And is processed in the same manner as in the embodiment described below.

First, the access status of each process to the cache memory device will be described with reference to a time chart of a single case of the block data write process of FIG. 2 and the hit check process of the prefetch instruction of FIG. First, FIG. 2 will be described. Here, the writing process of the first 32 bytes is shown among the 128-byte block size transferred from the lower-level memory four times in units of 32 bytes. The block data write is a signal BTPRE which is a signal to write the block data from the lower memory 103 in the next cycle in the first cycle.
D is issued. In the next cycle 2, the write data is transferred from the lower memory 103 to the data memory 101 by the path 110, and the block address is sent from the load instruction control device 40 or the store instruction control device 50 to the data memory address selector 114 by the path. A data valid indicating that the block address and the write data are invalid is output to the memory address selector 115. Then, in the next cycle 3, the data memory arbiter outputs a data memory select signal based on an instruction request signal from the load instruction control device 40 or the store instruction control device 50. With this signal, the data memory address selector 114 outputs the address information. The tag memory arbiter outputs a tag memory select signal based on the command request signal, and the tag memory address selector 115 selects address information and data valid based on the signal, and the tag memory arbiter 115 selects address information and data valid. Access to the memory 102 is performed, and data writing and data valid writing are performed.

Next, FIG. 3 shows a case in which a 128-byte block size is successively transferred from the lower memory four times in units of 32 bytes and written. In this case, the operations shown in FIG. 2 are sequentially repeated. In the case of FIG. 3, the tag memory 102 and the data memory 101 are accessed simultaneously in cycles 3 and 6, but only the data memory 101 is accessed in cycles 4 and 5. To access. That is, in cycle 3, an invalid bit is written to the tag memory 102, data is written to the data memory 101, and in cycle 6, a valid bit and a real page number are written to the tag memory 102, and data is written to the data memory 101. Then, in cycles 4 and 5, data is written to the data memory 101, but no data valid is written to the tag memory 102. This is because an invalid bit is written in the tag memory in cycle 3, so that it is not necessary to write an invalid bit in cycles 4 and 5, and it is sufficient to write a real page number and a valid bit in cycle 6.

Although the writing of the real page number is performed in cycle 6, it may be performed in cycle 3.

On the other hand, as shown in FIG. 4, the prefetch instruction accesses the tag memory in cycle 1 and performs a hit check. That is, the prefetch instruction control device 3
From 0, the block address is sent to the tag memory address selector 115, the tag memory arbiter 105 selects the block address by the tag memory address selector 115 based on the prefetch instruction request signal from the prefetch instruction control device 30, and the tag memory 102 is selected. A hit check is performed using the specified address. Then, in cycle 2, a hit result is obtained. If the check result is a hit, the process is terminated as it is. If the check result is a miss, a request for transferring block data of the cache to the lower memory is issued in cycle 3.

Next, the operation of the cache memory device according to one embodiment of the present invention, which simultaneously processes the execution of a prefetch instruction when writing block data, will be described. First, in cycle 1, the next cycle 2
BTPR that data is written to data memory
An ED is issued. Since this BTPRED is the first 32 bytes of the 128-byte block, the tag memory arbiter 105 sends a tag memory select signal for selecting a block write address to the tag memory address selector 115 in cycle 2. Then, in cycle 3, a bit in which the block data is invalid is written to the tag memory. Next, the second BTPR in cycle 2
When the ED is issued, the tag memory arbiter 105 selects the address of the prefetch instruction in cycle 3 because there is no access to the tag memory by the block write process and access to the tag memory by the prefetch instruction control device 30. Send the tag memory select signal to the tag memory address selector. Then, in the next cycle 4, the hit check of the prefetch instruction is performed in the tag memory, and the block data is written in the data memory. The case of the third BTPRED is the same as the case of the second BTPRED. Then, a hit result is obtained in cycle 5. If the check result is a mistake, a block data transfer request is issued in cycle 6. When the fourth BTPRED is issued, the tag memory arbiter sends a tag memory select signal for selecting a block write address to the tag memory address selector. As a result, in the next cycle, an operation of writing a bit indicating that the block data is valid and the real page number of the write block to the tag memory is performed.

As described above, it can be understood that the tag memory can be accessed in the same cycle as the block write by the cache memory device according to the present invention, so that the throughput is increased as compared with the prior art. In the present embodiment, the hit check of the prefetch instruction is taken as an example in the processing using only the tag memory. However, the present invention is not limited to this, and the hit check of the store, the hit check by the snoop, and the invalidation of the cache block by the snoop are performed. Also, throughput increases.

[0018]

As described above, according to the present invention,
The hit check of the prefetch instruction can be performed in the cycle of writing only the data memory by writing the block data of the cache, thereby increasing the throughput. Further, the use of only the tag memory is not limited to the hit check of the prefetch instruction of the embodiment, and the throughput increases even for the hit check of the store, the hit check of the snoop, and the invalidation of the cache block by the snoop. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory device according to the present invention.

FIG. 2 is a time chart of a block data write (first 32-byte data write) process.

FIG. 3 is a time chart of a block data write (continuous 32-byte data write) process.

FIG. 4 is an execution time chart of a prefetch instruction.

FIG. 5 is a time chart of block data write (continuous 32-byte data write) processing and simultaneous execution of a prefetch instruction.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Processor 20 Central controller 30 Prefetch instruction controller 40 Load instruction controller 50 Store instruction controller 60 Snoop controller 101 Data memory 102 Tag memory 103 Lower memory 104 Data memory arbiter 105 Tag memory arbiter 106 Prefetch instruction request, address path 107 Load instruction request, address path 108 Store instruction request, address path 109 Snoop instruction request, address path 110 external data path 111 external address path 112 data memory select signal 113 tag memory select signal 114 data memory selector 115 tag memory selector 116 to data memory Block address 117 Block address to tag memory

Claims (3)

[Claims] 1. A data memory for storing data, a tag memory for storing an address of data stored in the data memory, a plurality of processing controllers, a data memory arbiter, and a tag memory arbiter, wherein data is taken out At the time of storage and at the time of storage, the data memory arbiter and the tag memory arbiter permit use, so that only one of the plurality of processing controllers can store data in the data memory in the cache memory device accessing the data memory and the tag memory. When the data memory arbiter and the tag memory arbiter permit use of the data memory arbiter and the tag memory arbiter to perform a process in which the number of writing cycles is larger than the number of cycles of writing to the tag memory, the tag memory arbiter performs the data memory processing in the Write cycle only to tag memory Cache memory device characterized by comprising means for permitting the use of the tag memory arbiter in the cycle to be written only in the data memory to the processing unit for performing finish processing by accessing the. 2. The cache memory device according to claim 1, wherein, in a cycle of writing in only the data memory in the processing of the processing control device, a processing device performing a process completed by accessing only the tag memory is another processor. A processing device that performs a hit check process to check whether the shared memory address sent from the cache exists in the cache or a process of accessing the tag memory to invalidate a cache block including the shared memory address sent from another processor. A cache memory device, comprising: 3. The cache memory device according to claim 1, wherein, in a cycle of writing in only the data memory in the processing of the processing control device, the processing device performing a process completed by accessing only the tag memory includes a store hit. A cache memory device, which is a processing device that performs a process of accessing a tag memory for checking.