JPH02259945A - Storing processing system - Google Patents

Abstract

PURPOSE:To accelerate the processing speed by completing a storing instruction processing without awaiting a response from a main memory device by writing storing data in a move-in buffer when the mis-hit of cache occurs in the case of executing a storing instruction. CONSTITUTION:When no block data targeted to be stored is registered on a cache memory 3, a request to read out block data is issued to the main memory device, and also, when preceding move-in data is stored in the move-in buffer 8, the move-in data is transferred to the cache memory 3. When the transfer of the data to the cache memory 3 is completed and the move-in buffer 8 becomes null, the storing data from an instruction processor is written on the move-in buffer 8. In such a manner, it is possible to complete the processing of the storing instruction without awaiting the response from the main memory device and accelerate the processing speed.

Description

[Detailed Description of the Invention] [Summary] A store processing method that improves the processing speed of store commands and improves data processing efficiency regarding a store processing method in a memory control circuit using a move-in buffer. In a storage control circuit having a cache memory and a move-in buffer for temporarily holding data transferred from a main storage device to the cache memory, an inversion circuit for inverting a store byte mark, and a storage control circuit for inverting a store byte mark; A byte mark selection circuit for selecting a byte mark is provided, and when a miss occurs in the cache memory when a store instruction is executed, a data read request is requested to the main storage device and the byte mark selection circuit is activated. storing the store data in the move-in buffer according to the store byte mark directly through the main storage device, and storing the move-in data in the move-in buffer according to the store byte mark through the inverting circuit in response to a response from the main storage device. It was configured to do so.

[Industrial Application Field] The present invention relates to a store processing method in a storage control circuit using a move-in buffer.

BACKGROUND ART Cache memory has been widely used as a means for improving the performance of computer systems, and a store-in method (also called a swap method) is widely known as one control method for cache memory.

In the store-in method, if the block to be stored is registered in the cache memory when the store occurs (
(This state is called a cache miss state), the store data is written only to the cache memory, and if the target block is not registered in the cache memory (this state is called a cache miss state), the target block is written to the main memory. This method writes store data only to the cache memory after making a request to the device and registering it in the cache memory.According to this method, the control circuit is more complex than, for example, a method called a store-through method, but the main memory Since the operation rate of the processor is lowered, there is an advantage that the performance is improved compared to the store-through type, especially when a so-called multiprocessor system is configured in which the main memory is shared by a plurality of instruction processing units.

By the way, when there is no data in the cache memory in response to a memory request from the instruction processing unit, a so-called move-in is performed in which the data is read from the main memory and registered in the cache memory, but when there is a response from the main memory, At the same time, only the necessary data is responded to the instruction processing unit, and the response data from the main memory is not immediately registered in the cache memory, but is stored in a buffer storage called a move-in buffer and cached next time. By registering the move-in buffer data in the cache memory during an empty cycle when a miss occurs and waiting for a response from the main memory, the exclusive time of the cache memory for registration is eliminated, and the performance of the instruction processing unit is improved. There are known ways in which this can be improved.

In a cache memory using a store-in method, in this type of move-in control method, especially when processing a store instruction, when the block to be stored is not registered in the cache memory, a move-in is performed and the block is stored in the move-in buffer. After that, it is necessary to start the registration in the cache memory, and after the registration is completed, it is necessary to write the store data to the cache 1 memory.

[Prior Art] Conventionally, in a store-in cache memory, in a move-in control method using a move-in buffer, when a cache miss occurs due to a store instruction, the move-in buffer is not used and a block is transferred from the main memory. Register data directly to cache memory, or
After storing the block data in the move-in buffer, registration in the cache memory was started, and after the registration was completed, the store data was transferred to and from the cache memory.

[Problems to be Solved by the Invention] However, in cache memory using the conventional store-in method, the store is executed after the block data is completely registered in the cache memory, so the move-in is not completed completely. In other words, the store command cannot be completed until there is a response from the host W1 device and the block data is registered in the cache memory, and data processing efficiency cannot be improved. There was a problem.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a store processing method that improves the processing speed of store commands and improves data processing efficiency. There is.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 3 is a cache memory, 8 is a move-in buffer for temporarily holding data transferred from the main storage device to the cache memory 3, 12 is an inversion circuit for inverting a store byte mark, and 11 is a store byte mark. This is a byte mark selection circuit that selects.

[Operation] When processing a store instruction to the main memory, if the block data to be stored is not registered in the cache memory, a request is made to the main memory to read the block data, and the previous move is stored in the move-in buffer. If the move-in data is stored, this move-in data is transferred to the cache memory.

When the transfer to the cache memory is completed and the move-in buffer becomes empty, store data from the instruction processing device is written to the move-in buffer.

This completes the processing of the store instruction, and the instruction processing device starts processing the next instruction. After that, the storage control circuit
When there is a response from the main memory, move-in data from the main memory is written to the move-in buffer.

As described above, when a cache miss occurs during the execution of the S1 to A instructions, the instruction processing device transfers the data in the move-in buffer to the cache memory, and then writes the store data to the move-in buffer. Store command processing can be completed without waiting for a response from the storage device.

As a result, it is possible to avoid improving the processing speed of store instructions, and it is possible to improve data processing efficiency.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 to 4 are diagrams showing an embodiment of the present invention.

In FIG. 2, reference numeral 1 denotes an access address register into which the access address from the instruction processing device is input, and the access address register 1 is composed of, for example, 32 bits, and has an ID section, an index section, an intra-block address section, etc. ing. Access address register] is tag memory 2,
The address is output to the cache memory 3 and move-in buffer address register 4. The tag memory 2 is indexed with an address index section. The tag memory 2 contains the address I of the block registered in the cache memory 3.
It has a bit called the D section and a bit indicating whether the block is valid or invalid, and the ID section of the tag memory 2 and the ID section of the access address register 1 are compared in a comparison circuit 5, and the comparison result is detected in a match detection circuit 6. be done. At the same time as searching the tag memory 2, the address of the access address register 1 and the address of the move-in buffer 7 address register 4 are compared in the comparison circuit 7, and the comparison result is sent to the match detection circuit 6.
Detected in As a result of the comparison by the tag memory 2 and the move-in buffer address register 4, if the block to be accessed is registered in the cache memory 3, the block to be accessed is registered in the cache memory 3 and also in the move-in buffer address register 4. In this case, if the move-in buffer hit state is not registered in either the cache memory 3 or the move-in buffer address register 4, the cache miss state occurs.

8 is a move-in buffer (MIB) for temporarily holding data transferred from the main storage device to the cache memory 3, and the move-in buffer 8 has a block size of 32 bytes and a line size of 8 bytes, for example. There is. Therefore, if the line size that can be transferred at one time is 8 bytes, 4τ clock cycles are required to transfer block data. The move-in data in the move-in buffer 8 is transferred to the cache memory 3 via the selection circuit 9.

Reference numeral 10 denotes a byte mark register in which a store byte mark from the instruction processing device is set, and the byte mark stored in the byte mark register 10 is either directly input to the move-in buffer 8 via the byte mark selection circuit 11, or Alternatively, after being inverted by the inverting circuit 12, the signal is input to the move-in buffer 8 via the byte mark selection circuit 11.

When a cache miss occurs in the cache memory 3 during the execution of a store instruction, the store data from the instruction processing device is transferred to the move-in buffer 8 from the selection circuit 1.
Written according to the direct store byte mark via 3. When there is a response from the main memory, move-in data is written into the move-in buffer 8 from the main memory via the selection circuit 13 according to the byte mark inverted by the inversion circuit 12.

14 is a selection circuit for selecting move-in data from the main storage device or data from the move-in buffer 8; 15;
is the data from the selection circuit 14 or the cache memory 3
This is a selection circuit that selects data from. Selection circuit 15
The data is sent to the instruction processing unit as raw data.

Next, the operation will be explained.

The operation when a cache miss occurs during execution of a store instruction will be explained based on FIGS. 3 and 4.

In FIG. 3, at time τ0, the access address from the instruction processing device is set in the access address register 1, and the tag memory 2 is searched and the move-in buffer address register 4 is compared. As a result, if the cache memory 3 is not registered in any of the move-in buffers 8, a cache miss state occurs, and the 4: miss hit detection flag is set.

While this flag is on, the instruction processing device delays instruction processing. At the same time, it sends the address of the access address register 1 according to the main memory and issues a read request for the main memory.

Next, from time τ1 to τ4, if the previous move-in data is registered in the move-in buffer 8, these move-in data are transferred to the cache memory 3, and at the same time, the address of the move-in buffer address register 4 is transferred. Register in tag memory 2. In this way, the move-in buffer 8 becomes empty.

Next, at time τ5, when the control signal notifies the instruction processing device that the move-in buffer 8 has become empty, the instruction processing device outputs store data and a store byte mark. The store data is selected by the selection circuit 13 and written into the move-in buffer 8 in accordance with the non-inverted direct store byte mark set in the byte mark register 10. FIG. 4(1) shows a state in which the store data is written into the move-in buffer 8. Figure 4 (1) shows an example of operation when the store start address is address 3 and the store data length is 4 bytes.
Store data is written to the position indicated by diagonal lines.

As the store data is written to the move-in buffer 8, the processing of the store instruction ends, the cache miss flag is reset, and the instruction processing device starts executing the next instruction. In this way, the processing of the store command can be completed without a response from the main memory.

Next, at time τ-03, when there is a response of move-in data from the main memory, the move-in data is selected by the selection circuit 13, and the byte mark register 10
The move-in buffer 8 is moved according to the byte mark inverted by the inverting circuit 12 from the store byte mark held in the
will be written to.

FIG. 4(2) shows a state in which the move-in data is input and output to the move-in buffer B. As shown by diagonal lines in FIG. 4(2), the move-in data is written to a position inverted by the inverting circuit 12.

Next, the remaining move-in data is written to the move-in buffer 8 from time τn-2 to τn. The inserted and extracted states are shown in FIGS. 4(3) to 4(5), respectively. In this way, the move-in ends. Note that the time τn−
The operation from time 3 to time τn is carried out independently by the storage control circuit, and the instruction processing device does not perform any particular operation, allowing the execution of the slack instruction.

[Effects of the Invention] As described above, according to the present invention, when a cache miss occurs during the execution of a store instruction, the store data is written to the move-in buffer, so that the response from the main storage device is Store instruction processing can be completed without waiting for . As a result, the processing speed of store commands can be improved, and data processing efficiency can be improved.

In the figure, 1...Access address register, 2...Tag memory, 3...Cache memory, 4...Move-in buffer address register, 5.7
... Comparison circuit, 6 ... - Number configuration circuit, 8 ... Move-in buffer, 9.13, 14.15 ... Selection circuit, 10 ... - Byte mark register, 11 ... Byte Mark selection circuit, 12...inversion circuit.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a time chart of operation, and Fig. 4 is a diagram showing an example of storing a move-in buffer. . Figure 4

Claims (1)

[Claims] In a storage control circuit having a cache memory (3) and a move-in buffer (8) for temporarily holding data transferred from the main storage device to the cache memory (3), an inversion circuit ( 12
) and a byte mark selection circuit (11) for selecting a store byte mark, when executing a store instruction,
When a miss occurs in the cache memory (3), a request is made to the main memory to read data, and the store data is stored in accordance with the direct store byte mark via the byte mark selection circuit (11). Store the move-in data in the move-in buffer (8), and store the move-in data in the move-in buffer (8) according to the store byte mark via the inversion circuit (12) according to the response from the main memory. A store processing method characterized by the following.