JPH11149422A - Data holding system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the specifying of an error bit by holding error data and an error parity under an error condition in nodes at a transmission side and a reception side by means of the parity check of the reception side node and reading them. SOLUTION: When data is transferred from the transmission side node 100 to the reception side node 300 with a data bus 10, received data and the parity are respectively held in a reception data holding buffer 320 and a reception parity holding buffer 330 when a parity check result in the reception side node 300 indicates the error. Transmitted data and the parity are temporarily saved in the buffers 200 and 210 in the transmission side node 100. After that, transmission data being the error and the parity are respectively held in a transmission data holding buffer 220 and a transmission parity holding buffer 230. Then, held data and the held parity of the transmission side and the reception side nodes 100 and 300 are respectively read and compared so as to enable specifying the error bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a plurality of nodes connected by a bus, and more particularly to an information processing apparatus for transferring data between a plurality of nodes connected by a bus.

[0002]

2. Description of the Related Art In an information processing apparatus in which a plurality of nodes are connected by a bus, when data is transferred from a transmitting node to a receiving node, a data parity error is detected by a parity check of the receiving node. If the cause is waveform distortion due to signal reflection or crosstalk, it is necessary to observe the analog waveform of the data bus and data parity bus to identify the error bit . By the way, with the recent improvement in data transfer performance of information processing devices, there has been a remarkable increase in the data bus width, and it is difficult to identify error bits by observing analog waveforms using observation equipment. It is becoming.

For this reason, for example, Japanese Patent Application Laid-Open No. Sho 62-13472
In the information processing apparatus in which a plurality of nodes are connected to a bus, Japanese Patent Application Laid-Open No. 9-205980 discloses an input data register that captures data on the bus and a bus data register that checks the parity of the input data register and holds the result. parity·
Checking means, bus driving means for sending internal data to the bus, internal data parity checking means for checking the parity of the internal data when sending the internal data to the bus, and holding the result, and bus data・ Parity check result and internal data
Error detection signal generation means for generating an error detection signal when the result of the check by the parity check means is different from each other, and exclusion of output data and input data when the error detection signal is detected from the error detection signal generation means There has been proposed a method of calculating a logical OR to detect an error bit of data.

[0004]

However, the above-mentioned prior art has the following problems.

That is, in the prior art, the parity check result of the internal data to be output to the bus of the transmitting node and the parity check result of the input data register input from the bus of the transmitting node are obtained. If the result of the comparison is different, the error bit of the data is specified.

The reason for this is that, as described above, simply comparing the parity check result of the internal data of the transmission node with the parity check result of the input data register of the transmission node causes the transmission node to receive the data from the reception node. The parity check result of the input data register at the transmitting node is normal due to the line characteristics such as signal reflection, crosstalk, electric load, and bus line length when data propagates to the node. If the parity check result of the input data register is abnormal, the error detection means of the transmitting node is invalid for the receiving node, and the error bit cannot be specified. is there.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a data processing apparatus in which a plurality of nodes are connected by a bus, a data parity generation result of a transmission side node and a reception Parity of the side node
To provide a data retention method that can specify the error bit without observing the analog waveform of the data bus and the data parity bus when the data parity error is detected due to a difference in the check result. is there.

[0008]

According to the present invention, there is provided a data holding system comprising: a data bus for transferring data between a plurality of nodes; and a data bus for transferring a data parity generation result. A parity bus, data receiving means for receiving data from the data bus, parity receiving means for receiving parity from the data parity bus, and data stored in the data receiving means. Parity checking means for performing a parity check with the parity stored in the parity receiving means; and reception for holding data of the data receiving means when a result of the parity checking means indicates a data parity error. The data holding means and the parity check means when the result of the parity check means indicates a data parity error; Receiving parity holding means for holding parity of the parity receiving means, a data error signal that is valid when the result of the parity check circuit indicates a data parity error, and transmitting data to the data bus. Data transmission means for
Parity generation means for generating parity for transmission to a parity bus, parity transmission means for transmitting parity to the data parity bus, transmission data saving means for temporarily saving transmission data, and transmission Transmission parity saving means for temporarily saving parity, and transmission data holding means for holding data of the transmission data saving means when a data error signal valid when indicating the data parity error is valid And transmission parity holding means for holding the data of the transmission parity saving means when the data error signal is valid.

[0009]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, when data is transferred from a transmitting node to a receiving node via a data bus in a preferred embodiment, the parity check result at the receiving node indicates an error. In addition to notifying the data error, the contents of the received data and the received parity are held in the received data holding buffer and the received parity holding buffer, respectively, and the transmitting node temporarily saves the transmitted data and parity in the buffer. In addition, when the data error signal is notified, the transmitted data and the transmitted parity having an error are held in a transmission data holding buffer and a transmission parity holding buffer, respectively, And the stored parity, the stored data and the stored parity of the receiving node are read. It is obtained so as to enable specifying the error bit data and parity comparison.

More specifically, when the data receiving node detects a data parity error, it validates the data error signal and notifies the transmitting node that the data parity data has been detected. In addition, the received data is held in the reception data holding buffer, and at the same time, the received parity is held in the reception parity holding buffer.

When the transmitting node is notified that the data error signal is valid, the transmitting node causes the contents of the transmitting data saving buffer, which temporarily saves the transmitted data, to be held in the transmitting data holding buffer. The content of the transmission parity saving buffer temporarily saving the parity thus saved is held in the transmission parity holding buffer.

For this reason, when the data is detected from the data parity error in the receiving node, both the receiving node and the transmitting node can hold the data and parity for which the data parity error has been detected, By reading the reception data holding buffer, the reception parity holding buffer, the transmission data holding buffer, and the transmission parity holding buffer, and comparing them,
The specification of the error bit can be performed without observing the analog waveform of the data bus and the data parity bus.

[0013]

Next, in order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. 2 and 3 are timing charts for explaining the operation of one embodiment of the present invention.

Referring to FIG. 1, a data transmitting / receiving node 100 and a data transmitting / receiving node 300 are provided.

In the data transmission / reception node 100, the transmission data register 160 is set when transmitting internal data to the data bus 10, and is transmitted to the data bus 10 via the transmission data buffer 170.

The parity generation circuit 180 transmits the transmission data
The parity of the register 160 is generated and transmitted to the data parity bus 30 via the transmission parity buffer 190.

The transmission data saving buffer 200 saves the contents of the transmission data buffer 170 every time data is transmitted from the transmission data buffer 170 to the data bus 10.

The transmission parity save buffer 210 saves the contents of the transmission parity buffer 190 every time a parity is transmitted from the transmission parity buffer 190 to the data parity bus 30.

The transmission data holding buffer 220 holds the contents of the transmission data saving buffer 200 when the data error signal 20 that becomes valid when the receiving node detects a data parity error is valid.

The transmission parity holding buffer 230 holds the contents of the transmission parity saving buffer 210 when the data error signal 20 is valid.

The reception data buffer 120 stores the data
The data output to the bus 10 is received.

The receive parity buffer 130 receives the parity output on the data parity bus 30.

When the own node is the data receiving node, the parity check circuit 110 receives the contents of the received data buffer 120 and the contents of the received parity buffer 130 and performs a parity check.

When a data parity error is detected, the parity check circuit 110 stores the contents of the reception data buffer 120 in the reception data holding buffer 14.
0, and the contents of the reception parity buffer 130 are held in the reception parity holding buffer 150, and
The data error signal 20 is made valid to notify the transmitting node that a data parity error has been detected.

Data transmission / reception node 300 transmits / receives data.
The configuration is the same as that of the receiving node 100, and the description of the configuration is omitted.

Next, the operation of one embodiment of the present invention will be described. FIG. 2 is a timing chart showing the operation of each unit in FIG. 1 when a data parity error is not detected, and FIG. 3 is a timing chart showing the operation of each unit in FIG. 1 when a data parity error is detected. .

First, the operation of one embodiment of the present invention when no data parity error is detected will be described with reference to FIGS.

When data to be transmitted to the data bus 10 is set in the transmission data register 160 of the transmitting node 100 (A in FIG. 2), the transmission data buffer 170
(FIG. 2B), data is transmitted to the data bus 10 (FIG. 2H).

At the same time, the parity of the transmission data is generated by the parity generation circuit 180, and the transmission parity buffer 1
The data parity bus 30 via 90 (C in FIG. 2)
Is transmitted (I in FIG. 2).

The contents of the transmission data buffer 170 are saved in the transmission data saving buffer 200 (D in FIG. 2), and the contents of the transmission parity buffer 190 are saved in the transmission parity saving buffer 210 (FIG. 2). E).

The data (H in FIG. 2) output to the data bus 10 is received by the reception data buffer 320 of the receiving node 300 (J in FIG. 2), and the data is received by the reception parity buffer 330. Receive the parity (I in FIG. 2) output to the parity bus 30 (K in FIG. 2).

When data and parity are received, the parity check circuit 310 performs a parity check.

When the parity check result of the parity check circuit 310 indicates normal (L in FIG. 2), the data is not held in the reception data holding buffer 340 and the reception parity holding buffer 350 (M and N in FIG. 2). ,And,
The data error signal 20 is not made valid (O in FIG. 2).

In the transmitting node 100, since the data error signal 20 indicates invalid (O in FIG. 2), the transmission data holding buffer 220 and the transmission parity holding buffer 230
Are not held (F and G in FIG. 2).

Next, the operation of the embodiment of the present invention when a data parity error is detected will be described with reference to FIGS.
This will be described with reference to FIG.

When data to be transmitted to the data bus 10 is set in the transmission data register 160 of the transmitting node 100 (A in FIG. 3), the transmission data buffer 170
(FIG. 3B), the data is transmitted to the data bus 10 (FIG. 3H). At the same time, the parity generation circuit 180
Then, the parity of the transmission data is generated, and the parity is transmitted to the data parity bus 30 via the transmission parity buffer 190 (C in FIG. 3) (I in FIG. 3).

The contents of the transmission data buffer 170 are saved in the transmission data saving buffer 200 (D in FIG. 3), and the contents of the transmission parity buffer 190 are saved in the transmission parity saving buffer 210 (FIG. 3). E).

The reception data buffer 320 of the receiving node 300 receives the data (H in FIG. 3) output to the data bus 10 (J in FIG. 3), and stores the data in the reception parity buffer 330. Receive the parity (I in FIG. 3) output to the parity bus 30 (K in FIG. 3).

When the data and the parity are received, the parity check circuit 310 performs a parity check. When the parity check result of the parity check circuit 310 indicates an abnormality (L in FIG. 3), the reception data holding buffer 340 and the reception parity holding buffer 350
(M and N in FIG. 3), and the data error signal 20 is made valid (O in FIG. 3).

In the transmitting node 100, since the data error signal 20 indicates valid (O in FIG. 3), the transmission data holding buffer 220 and the transmission parity holding buffer 230
(F and G in FIG. 3).

[0042]

As described above, according to the present invention,
When data is transferred from the transmitting node to the receiving node via the data bus, error data and error parity at the time of an error are retained in both the transmitting node and the receiving node by the parity check of the receiving node. By reading the held data and parity, it is possible to easily specify an error bit, and it is possible to specify an error bit without observing an analog waveform.

The reason is that in the present invention, when the parity check result of the receiving node indicates an error, the data error signal is made valid and the received data
The contents of the buffer are held in the reception data holding buffer, and the contents of the reception parity buffer are held in the reception parity holding buffer. At the transmitting node, when the data error signal is valid, the contents of the transmission data saving buffer are stored. Is stored in the transmission data holding buffer, and the contents of the transmission parity saving buffer are held in the transmission parity holding buffer, so that both the receiving node and the transmitting node hold the error data and parity. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data holding method according to the present invention.

FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention, and is a timing chart showing the operation of each unit in FIG. 1 when a data parity error is not detected.

FIG. 3 is a diagram for explaining the operation of one embodiment of the present invention, and is a timing chart showing the operation of each unit in FIG. 1 when a data parity error is detected.

[Explanation of symbols]

 Reference Signs List 10 data bus 20 data error signal 30 data parity bus 100 data transmission / reception node 110 parity check circuit 120 reception data buffer 130 reception parity buffer 140 reception data holding buffer 150 reception parity holding buffer 160 transmission data Register 170 Transmission data buffer 180 Parity generation circuit 190 Transmission parity buffer 200 Transmission data saving buffer 210 Transmission parity saving buffer 220 Transmission data holding buffer 230 Transmission parity holding buffer 300 Data sending / receiving node 310 Parity check circuit 320 Receiving data Buffer 330 Receive parity buffer 340 Receive data holding buffer 350 Receive parity holding buffer 360 Transmit data level Star 370 transmission data buffer 380 parity generator 390 transmission parity buffer 400 sends data saving buffer 410 transmits the parity saving buffer 420 transmission data holding buffer 430 transmits the parity holding buffer

Claims (3)

[Claims] 1. A method for transmitting data from a transmitting node to a receiving node.
When transferring data via a bus, a means for holding error data and error parity at the time of error detection in the parity check of the receiving node, both in the transmitting node and the receiving node, An error bit is identified by reading the held data and parity. 2. A method for transmitting data from a transmitting node to a receiving node.
When transferring data via the bus, a data error is notified when the parity check result at the receiving node indicates an error, and the contents of the received data and the received parity are stored in a received data holding buffer and a received parity. In the holding buffer, the transmitting node temporarily saves the transmitted data and parity in a buffer, and when the data error signal is notified from the receiving node,
The transmitted data and the transmitted parity in error are held in a transmission data holding buffer and a transmission parity holding buffer, respectively, and the held data and the held parity of the transmitting node and the held data and the held parity of the receiving node are stored. A data holding method characterized in that data and parity error points are specified by reading and comparing. 3. A data bus for transferring data between a plurality of nodes in an information processing apparatus in which a plurality of nodes are connected by a bus, and a data parity bus for transferring a data parity generation result. A reception data buffer for receiving data from the data bus; a reception parity buffer for receiving parity from the data parity bus; and data stored in the reception data buffer. A parity check circuit for performing a parity check with the parity stored in the reception parity buffer; and a data storage unit for storing data in the reception data buffer when a result of the parity check circuit indicates a data parity error. A reception data holding buffer, and a data parity A reception parity holding buffer for holding the parity of the reception parity buffer when indicating a parity error; a data error signal that is valid when a result of the parity check circuit indicates a data parity error; A transmission data buffer for transmitting data to the data bus, a parity generation circuit for generating parity for transmission to the data parity bus, and a transmission for transmitting parity to the data parity bus A parity buffer, a transmission data saving buffer for temporarily saving transmission data, a transmission parity saving buffer for temporarily saving transmission parity, and data in the transmission data saving buffer when the data error signal is valid. A transmission data holding buffer for holding the And a transmission parity holding buffer for holding the parity of the transmission parity saving buffer when the data error signal is valid.When transmitting data from the transmitting node to the receiving node using the data bus, When a data parity error is detected, the reception data holding buffer of the receiving node, the reception parity holding buffer of the receiving node, the transmission data holding buffer of the transmission node, and the transmission node of the transmission node. A data holding method, wherein a data parity and an error bit of the data parity bus can be specified by reading data and parity held in a transmission parity holding buffer.