JP3095060B2 - ATM switch device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an ATM (Async).
The present invention relates to an ATM switch technology for routing (transfer mode) cells at an ATM switching node in a network and delivering the cells to a target destination, and more particularly to an ATM switch technology of a shared memory system.

[0002]

2. Description of the Related Art In a shared memory type ATM switch technology, all cells from an input line are temporarily written into a common memory in accordance with an output line of each destination, and the cells are timed for each output line. Read and perform switching.

FIG. 5 is a block diagram of a conventional ATM switch device 500 of a shared memory system. Referring to FIG.
A conventional ATM switch device is UTOPIA (Universal).
rsal Test & Operations PH
The original ATM switch device switches the cell data of one cell received from the outside via an interface of the Y Interface for ATM (hereinafter referred to as UTOPIA interface) and transmits it again to the outside via the UTOPIA interface. The operation will be described.

First, an operation of storing cell data received from the UTOPIA interface in a shared memory will be described.

[0005] Receive FIFO (First In First Out) connected to the UTOPIA interface
The write control unit 501 checks (polls) whether a cell can be transmitted from the PHY to each of a plurality of connected physical layers (hereinafter, referred to as PHYs), and determines a PHY that can be transmitted. When the cell data B01 is detected, the cell reception is started and the write control signal B00 is output to output the cell data B01.
Is written to the reception FIFO 502. Receive FIFO 502
When the timing at which the cell can be read from is detected,
FIFO read control means 50 for receiving read permission signal B02
Send to 3.

[0006] The reception FIF receiving the read permission signal B02
The O read control unit 503 uses a timing signal B03 indicating the head of the cell to be read and a read control signal B04 that controls reading from the reception FIFO 502 to transfer the cell data B to a switch core (hereinafter, referred to as SW core) 504.
Send 05.

The SW core 504 writes all cells from the input line according to the output line of each address,
It is composed of a shared buffer 505, which is a shared memory that is read out at a timing for each output line, and a queue management header conversion output arbiter 506 that performs cell address management, traffic control, header conversion processing, and the like.

Next, the operation of transmitting the cell data stored in the shared memory to the outside via the UTOPIA interface will be described.

[0009] The transmission FIFO read control means 507 polls each of the plurality of connected PHYs as to whether or not the PHY can receive cells, and then synchronizes with the UTOPIA interface cycle. To read out the data. By polling,
A polling result B06 represented by a bitmap and a polling valid timing signal B07 are generated, and the SW core 5
04.

[0010] Polling result B06 and valid timing B
07, the SW core 504 determines which PHY the cell data is to be output to,
05, and outputs a timing signal B08 indicating the head of the cell and cell data B09 to the transmission FIFO write control means 508.

The timing signal B08 and the cell data B09
The transmission FIFO write control unit 508 that has received the cell data B11 transmits the cell data B11 according to the write control signal B10 that controls writing to the transmission FIFO 509.
Write to. Further, based on the address value at the time of writing, a timing at which reading is possible from the transmission FIFO 509 is detected and transmitted to the transmission FIFO read control means 507 as a read permission signal B12.

The transmission F that has received the read permission signal B12
The IFO read control means 507 sends the transmission FIFO 5 in accordance with the operation timing of the UTOPIA interface.
09 read control signal B13 to transmit the cell data B1
4 is read and cell data is output to the UTOPIA interface.

The MPU interface 510 is connected to an MPU (not shown). The MPU sets the operation mode of the ATM switch device 500.

[0014]

Here, a diagnosis method for finding out whether the operation of the ATM switch device is normal and where the ATM switch device is located when there is a problem is considered. When performing this diagnosis, it is necessary to execute transmission and reception of various and large amounts of data. For this reason, when diagnosing the conventional ATM switch device 500, a dedicated measuring device having a UTOPIA interface is prepared and diagnosed.

The ATM switch device is composed of one or a plurality of LSIs. However, if the present LSI is incorporated in a network device, there is no means for checking the operation of a single unit. Furthermore, when starting up the evaluation of the initial LSI, problems on the board incorporating the initial LSI, LSI
If a failure occurs in the interface function, the evaluation must be interrupted because there is no alternative for data entry.

The problem to be solved by the present invention is that the internal basic operation can be confirmed without the need for a dedicated measuring device, and a self-diagnosis can be performed even after being incorporated as a network device. An object of the present invention is to provide an ATM switch device.

Another object is to provide an ATM switch device capable of evaluating an LSI even when data cannot be input due to a malfunction of an interface block function between the LSIs or a connection problem on an evaluation board for an actual LSI. It is to be.

[0018]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a shared memory type ATM switch device including a transmission and reception buffer for storing transmission and reception data and an MPU, and an output from the MPU. Means for transmitting predetermined test data to the reception buffer, and transmitting data output from the transmission buffer to the MPU.
Means for sending test data and transmission data to M
Provide an ATM switch device characterized by comparison by PU

Further, according to the present invention, in a shared memory type ATM switch device having a transmission and reception buffer for storing transmission and reception data and an MPU, means for transmitting predetermined test data output from the MPU to the reception buffer is provided. And a means for sending transmission data output from the transmission buffer to the MPU, wherein the test data and the transmission data are compared by the MPU.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An ATM switch device 100 according to a first embodiment of the present invention will be described with reference to FIG.

The difference from the conventional example is that the reception FIFO write control means 101 and the transmission FIFO write control means 108 of the ATM switch device 100 are connected to the selector 101a.
And that the test cell data A15 and A17 are output from the MPU (not shown) to the selectors 101a and 108a via the MPU interface 110, and that the reception FIFO 102 and the transmission FIFO
The cell data A16 and A18, which are the outputs of
This is to be connected to an MPU (not shown) via the U interface 110. Other configurations are the same as the conventional example.

The selector 101a selects one of the UTOPIA interface and the cell data output from the MPU in accordance with the instruction of the MPU, and transmits the cell data A01 to the reception FIFO 102. The cell data output from the MPU is obtained by writing desired data for one cell at a desired address one word at a time, and is predetermined test cell data A15. In addition, data can be referenced word by word from a desired address of the reception FIFO 102 via the MPU interface 110, and self-diagnosis of memory cells of the reception FIFO 102 can be performed.

Similarly, the transmission FIFO 109 can write cell data to a desired address via the MPU interface 105 and read cell data from the desired address. Therefore, the transmission F
Self-diagnosis of the memory cells of the IFO can be performed.

When an external device is connected, MP
Via the U interface 101, the reception FIFO 10
2. The data stored in the transmission FIFO 109 can be confirmed.

An ATM switch device 200 according to a second embodiment of the present invention will be described with reference to FIG.

The ATM switch device 200 has selectors 201 and 202 in addition to the ATM switch device 100.

The selector 201 has a read permission signal A02 received from the reception FIFO write control means 101 and a predetermined read permission test signal A19 output from the MPU.
Is selected by the instruction of the MPU, and the read permission signal A20 is output to the reception FIFO read control means 103.

By having the selector 201, the MP
Since the read permission signal A20 can be transmitted to the reception FIFO read control means 103 at an arbitrary timing according to the instruction of U, the read operation by the reception FIFO read control means 102 is executed at an arbitrary timing to receive the reception FIFO signal.
The cell data stored in the FO 102 can be stored in the shared buffer 105 of the SW core 104.

On the other hand, the selector 202 is provided with a set of the polling result data A06 and the polling valid timing signal A07 received from the UTOPIA interface by the transmission FIFO read control means 107, and a predetermined polling result test data A21 and an output from the MPU. Polling valid timing test signal A22
One of the sets is selected by the instruction of the MPU, and the polling result data A23 and the polling valid timing signal A24 are output.

By having the selector 202, the MP
Cell data can be read from the shared buffer 105 by operating the SW core 104 at an arbitrary timing according to the instruction of U. Thus, the cell data stored in the SW core 104 can be output to the UTOPIA interface in the same manner as the original operation of the ATM switch device.

Next, the self-diagnosis operation of the ATM switch device 200 will be described.

MPU receives test cell data A15
Write to IFO 102. The MPU transmits the read permission test signal A19 to the reception FIFO read control unit 103 via the selector 201, and
02 is started. With the cell read, a timing signal A03 indicating the head timing of the cell
Is transmitted to the SW core 104, and the cell is stored in the shared buffer 105 of the SW core 104.

The polling result test data A21 and the polling valid timing test signal A22 are connected to the selector 2
02 to the SW core 104 by transmitting the polling result data A23 and the polling valid timing signal A to the SW core 104.
Send 24.

The SW core 104 that has received the polling result data A23 and the polling valid timing signal A24
Reads a cell from the shared buffer 105, performs traffic control and header conversion processing, and outputs a timing signal A08.
And the cell data A09.

Transmission FI receiving timing signal A08
The FO write control means 108 generates an address to the transmission FIFO 109 and stores the cell data A09 in the transmission FIFO 10
9 is stored.

After storing the cell in the transmission FIFO 109, the MP
U reads the cell data A18 and confirms that the destination and the header conversion are correct.

An ATM switch device 300 according to a third embodiment of the present invention will be described with reference to FIG.

The ATM switch device 300 includes a selector 301 in addition to the ATM switch device 200. The selector 301 selects one of the read permission signal A12 output from the transmission FIFO write control means 108 and a predetermined read permission test signal A25 output from the MPU according to the instruction of the MPU, and selects the transmission FIFO read control means 107. Transmits the read permission signal A26 to

Transmission F from the MPU via the selector 301
By transmitting the read permission test signal to the FIFO read control means 107, the read operation of the transmission FIFO read control means 107 can be started at a desired timing.

An ATM switch device 400 according to a fourth embodiment of the present invention will be described with reference to FIG.

The ATM switch device 400 includes a selector 104a in addition to the configuration of the ATM switch device 300. Further, the test cell data A27 is supplied to the selector 104a via the MPU interface 110 and the MPU (not shown).
Output from Further, the cell data stored in the shared buffer 105 is referred to as the cell data A28 by the MPU via the MPU interface 110.

Next, the operation of the ATM switch device 400 will be described. This operation is an operation of writing test cell data from the MPU to the shared buffer 105 and an operation of the shared buffer 10.
5 to read the cell data from the MPU.

The test cell data write operation is performed as follows. The MPU can write desired data to a desired address of the shared buffer 105 by transmitting the test cell data A27 to the selector 104a via the MPU interface 110 and transmitting it to the shared buffer 105.

The cell data stored in the shared buffer 105 during the test cell data write operation or the original operation of the ATM switch device is referred to by the MPU via the MPU interface 110 as the cell data A28. Can be. Therefore, a memory test of the shared buffer 105 can be performed.

ATM switch devices 200, 300 and 4
00 is A by using a selector in combination.
It is possible to isolate and diagnose the inside of the TM switch device or the UTOPIA interface and the SW core to identify the location where the problem occurs.

For example, the selector 101a and the selector 20
1 is used, the reception FIFO read control means 10
Operation check 3 can be performed. The test cell data A15 is stored in the reception FIFO 102 via the MPU.
After writing for the cells, a read permission test signal A19 is output to the reception FIFO read control means 103. Receive F
The IFO read control unit 103 reads the cell data A05 from the reception FIFO 102 and stores the cell data A05 in the shared buffer. By reading and comparing the cell data stored in the shared buffer via the MPU, it is possible to confirm whether the reception FIFO read control unit 103 is operating normally.

The selector 104a and the selector 202
Is used, the transmission FIFO write control unit 108
Operation can be confirmed. The test cell data A27 is stored in the shared buffer 105 via the MPU, and the polling result test data A23 and the polling valid timing signal A24 are output to the SW core 104.
Cell data is read from the shared buffer 105 and stored in the transmission FIFO 109. By reading and comparing the cell data stored in the transmission FIFO 109 via the MPU, it is possible to confirm whether the transmission FIFO write control unit 108 is operating normally.

Further, when an external device is used, the UTO
The normal operation of the PIA interface can be confirmed.

For example, the reception FIFO write control means 10
When it is desired to confirm the operation check of No. 1, the cell is received via the UTOPIA interface, and the cell data stored in the reception FIFO 102 is read out via the MPU. By comparing the read cell data with the input cell data, the reception FIFO write control unit 101 determines that the UTOPIA
Synchronize with the interface to check whether it was received normally.

Transmission FIFO read control means 107
If it is desired to confirm the operation of
The test cell data is written into the transmission FIFO 109 via the PU, and the read permission signal A26 is transmitted from the MPU to the transmission FIFO 109.
Output to the O-read control means 107. The transmission FIFO read control unit 107 reads cell data from the transmission FIFO 109 and outputs the cell data to an external device via the UTOPIA interface. Cell data and MP output to external device
By comparing the cell data set from U, UTOP
It is possible to confirm whether or not transmission is normally performed from the transmission FIFO read control unit 107 in synchronization with the IA interface.

[0051]

As described above, according to the ATM switch device of the present invention, the operation can be confirmed by supplying dummy data to the ATM switch device by MPU access. For this reason, even after the ATM switch device is incorporated as a network device, it is possible to easily confirm whether or not there is a problem in the ATM switch device.

Even when there is a problem in the ATM switch device, the inside of the ATM switch device can be traced by separating the inside of the ATM switch device between the outside and the reception FIFO, the SW core, and the outside of the transmission FIFO. The location of occurrence can be easily specified.

Although the present invention has been described based on the embodiments, the present invention is not limited to these embodiments, and it is understood that changes and improvements can be made within the ordinary knowledge of those skilled in the art. Of course.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional ATM switch device.

[Explanation of symbols]

100, 200, 300, 400, 500 ATM switch device 101 Reception FIFO write control means 102 Reception FIFO 103 Reception FIFO read control means 104 SW core 105 Shared buffer 106 Queue management header conversion output arbiter 107 Transmission FIFO read control means 108 Transmission FIFO write Control means 109 Transmission FIFO 110 MPU interface 101a, 104a, 108a, 201, 202, 30
1 Selector A00 Write control signal A01 Cell data A02 Read permission signal A03 Timing signal A04 Read control signal A05 Cell data A06 Polling result A07 Polling valid timing signal A08 Timing signal A09 Cell data A10 Write control signal A11 Cell data A12 Read permission signal A13 Read Control signal A14 Cell data A15 Test cell data A16 Cell data A17 Test cell data A18 Cell data A19 Read permission test signal A20 Read permission signal A21 Polling result test data A22 Polling valid timing test signal A23 Polling result data A24 Polling valid timing signal A25 Reading Permission test signal A26 Read permission signal A27 Test cell data A28 Serde B00 Write control signal B01 Cell data B02 Read permission signal B03 Timing signal B04 Read control signal B05 Cell data B06 Polling result B07 Polling valid timing signal B08 Timing signal B09 Cell data B10 Write control signal B11 Cell data B12 Read permission signal B13 Read control Signal B14 Cell data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/24-12/28 H04L 12/56

Claims (5)

(57) [Claims] An ATM switch device of a shared memory system including a reception buffer for storing reception data and an MPU, a reception buffer write control unit for controlling writing to the reception buffer, and a control for reading from the reception buffer. Receiving buffer read control means for performing the following: a read permission signal which is a signal generated by the reception buffer write control means, and which is a signal for permitting the reception buffer read control means to read the reception buffer;
And a selector for selecting one of predetermined read permission test signals output from the MPU according to an instruction of the MPU and outputting the selected signal to the reception buffer read control means. An ATM switch device for outputting the cell data. 2. A shared memory type ATM switch device including a transmission buffer for storing transmission data and an MPU, comprising: a set of polling result data and a polling valid timing signal input from outside the ATM switch device; A selector configured to select and output any one of a set of predetermined polling result test data and a polling valid timing test signal output from the MPU in accordance with an instruction of the MPU; An ATM switch device for outputting input cell data to the MPU. 3. An ATM switch device of a shared memory system including a transmission buffer for storing transmission data and an MPU, a transmission buffer write control means for controlling writing to the transmission buffer, and a control for reading from the transmission buffer. And a read enable signal, which is a signal generated by the transmission buffer write control means, and which is a signal for permitting the transmission buffer read control means to read the transmission buffer.
And a selector that selects one of predetermined read permission test signals output from the MPU according to an instruction of the MPU and outputs the selected signal to the transmission buffer read control unit. An ATM switch device for outputting the cell data. 4. A shared memory type A having a transmission and reception buffer for storing transmission and reception data and an MPU.
In the TM switch device, one of predetermined test cell data output from the MPU and received cell data input from outside the ATM switch device is selected according to an instruction from the MPU, and the received data is selected as cell data. A first selector for outputting to a buffer, and one of transmission cell data output from a shared memory of the ATM switch device and predetermined test cell data output from the MPU selected by an instruction of the MPU. A second selector that outputs cell data to the transmission buffer, a reception buffer write control unit that controls writing to the reception buffer, a reception buffer read control unit that controls reading from the reception buffer, The signal generated by the reception buffer write control means , And the read enable signal is a signal for permitting reading of the reception buffer to the reception buffer read control means,
A third selector for selecting one of predetermined read permission test signals output from the MPU in accordance with an instruction from the MPU, and outputting the selected signal to the reception buffer read control means; A set of polling result data and a polling valid timing signal input from the MPU, and a set of predetermined polling result test data and a polling valid timing test signal output from the MPU. An ATM switch, wherein the receiving buffer outputs the cell data to the MPU, and the transmission buffer outputs the cell data to the MPU. apparatus. 5. The ATM switch device according to claim 4, further comprising: a transmission buffer write control unit that controls writing to said transmission buffer; and a transmission buffer read control unit that controls reading from said transmission buffer. A read permission signal, which is a signal generated by the transmission buffer write control means, and which is a signal for permitting the transmission buffer read control means to read the transmission buffer;
A fifth selector that selects one of predetermined read permission test signals output from the MPU in accordance with an instruction from the MPU and outputs the selected signal to the transmission buffer read control unit. ATM switch device.