JPH11149366A - Multi-bit comparing circuit and memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-speed operation by providing an exclusive OR circuit, calculating and inputting the wired-OR logic of its output to a decision circuit and outputting a signal indicating a match or mismatch, and suppressing the potential of a wired-OR node by using a potential suppressing circuit. SOLUTION: When one of 1-bit comparing circuits SG1 to SGn finds that input data Din matches comparison data Dcp, a current flows to a transistors Q1 or Q3 connected to a node Na in each of other 1-bit comparing circuits having found mismatches and a current (i) is drawn from the node Na. When a mismatch is one bit, a current flowing to the base-side diode D1 of a transistor Q11 in a decision device 10 becomes i+ia=ti/4 obtained by adding a current ia(=i/4) flowing to a transistor Q13 to the drawn current (i). The potential at the node Na becomes lower than that at a node Nb by a forward potential difference based upon the difference in current density between the two diodes D1 and D2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology which is effective when applied to a data comparison circuit and a multi-bit data comparison circuit at high speed. The present invention relates to an associative memory having a data match detection function and an address comparison function. The present invention relates to a technology effective for use in a cache memory or the like. In this specification,
The multi-bit data means all data of 2 bits or more, and the word data is not limited to its name, but includes all information including a plurality of bits such as an address as long as it is treated as data. .

[0002]

2. Description of the Related Art Conventionally, associative memories and cache memories have been proposed as memories having a function of comparing multi-bit data. The associative memory is a memory configured to specify a part of the storage content and read the position where the content is stored or the remaining content instead of accessing by specifying the address. Department,
The first memory unit stores data (search target data) to be compared with data (search data) input from the outside, and the second memory unit matches the search data with the search target data in the comparison. Stores the data to be retrieved. For this reason, the associative memory has a multi-bit comparison function of detecting coincidence between data input from the outside and data held inside, in addition to the storage function inherent in the memory.

In a system having a cache memory, an address tag memory for storing a tag address of data in the cache memory for determining whether data to be read is in the cache memory, and a data memory for storing data. And a multi-bit comparison circuit for comparing the input address with the tag address.

A multi-bit comparison circuit compares two data and outputs a high-level (or low-level) signal if even one bit does not match. Conventionally, a multi-bit comparison circuit composed of bipolar transistors is used. Constitutes a 1-bit comparison circuit with an exclusive-OR circuit composed of series gates, prepares a number of series gates corresponding to the number of data bits, and outputs their outputs to an ECL of two to three inputs.
(OR gate) consisting of (emitter-coupled logic) circuit
Some are configured to receive a final output from a circuit.

[0005]

In a conventional multi-bit comparison circuit using a series gate and an ECL circuit, as the number of data bits increases, the number of cascade-connected gate stages increases. There is a problem that the speed cannot be increased due to an increase. In addition, the conventional multi-bit comparison circuit uses a method in which a current is converted to a voltage by a resistor to obtain a signal amplitude, so that the amplitude is relatively large, and the current value changes in accordance with the number of mismatched bits to change the amplitude. Also changed.

An object of the present invention is to provide a multi-bit comparison circuit that can operate at high speed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, an exclusive OR circuit composed of series gates and the like is provided for the number of bits of data to be compared,
The outputs of these outputs are wired-ORed and input to a decision circuit such as an ECL circuit to output a signal indicating match / mismatch, and the potential of the wired-OR node is suppressed using a potential suppression circuit such as a diode. It is something to do.

According to the above-mentioned means, since the outputs of the plurality of series gates are input to the decision circuit by taking the wired-OR logic, the number of gate stages constituting the decision circuit is reduced, the delay time is shortened, and the wired time is reduced. Or
Since the potential of the node is suppressed, the amplitude of the signal can be suppressed irrespective of the number of mismatched bits, thereby achieving a high-speed comparison operation.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a multi-bit comparison circuit according to the present invention. In FIG. 1, SG0, SG1, ‥‥ S
Gn is a 1-bit 1-bit comparison circuit composed of a series gate, and 10 is the 1-bit comparison circuits SG0, SG1,
This is a determination circuit to which the output of SGn is commonly input.

The 1-bit comparison circuit SG has a pair of transistors Q1 and Q2 which are commonly connected to each other to form an upper-stage first current switch, and a pair of transistors Q3 and Q4 which form an upper-stage second current switch. Transistor pairs Q5, Q each having a collector connected to the emitter and a common connection to the emitter
6 and a constant current source CI1 connected to a common emitter of the transistor pairs Q5 and Q6.
The input data Din is input to the bases of the transistors Q1 and Q4, and the reference voltage Vref1 is applied to the bases of the transistors Q2 and Q3 forming a pair with the transistors Q1 and Q4.

The comparison data Dcp is applied to the base of a transistor Q6 constituting the lower stage current switch, and the reference voltage Vref2 is applied to the base of Q5.
Further, the collectors of the transistors Q2 and Q4 are connected to a power supply voltage Vcc such as a ground potential, and the collectors of the transistors Q1 and Q3 are connected to all the one-bit comparison circuits SG.
0, SG1,... SGn are connected to a node Na which takes a wired-OR logic.

Thus, the one-bit comparison circuit SG
0, SG1, and SGn are input data Din, respectively.
Is the same as the comparison data Dcp, a current path is formed such that the current i flowing through the constant current source CI1 flows through the transistor Q2-Q5 or Q4-Q6.
When in is different from the comparison data Dcp, the constant current source CI1
Current i flowing through the transistor Q1-Q5 or Q3-
A current path is formed to flow through Q6. That is, if at least one of the one-bit comparison circuits SG0, SG1,... SGn has a mismatch between the input data Din and the comparison data Dcp, the circuit operates so as to draw current from the node Na.

The determination circuit 10 includes a diode D1 connected between the node Na and the power supply voltage Vcc and the one-bit comparison circuits SG0, SG1,... SGn in a state where no current is drawn from the node Na. The node Na is also used to supply a predetermined bias current to the diode D1.
A bias circuit 11 including a resistor R1 and a transistor Q13 connected in series between the power supply voltage Vee and a resistor R1;
An ECL circuit 12 composed of a pair of transistors Q11 and Q12 commonly connected to an emitter and having the potential of the node Na applied to one base, their collector resistors Rc1 and Rc2, and a constant current source CI2 connected to a common emitter; A constant voltage circuit 13 comprising a diode D2 and a transistor Q14 connected in series between Vcc and Vee for generating a reference voltage Vref3 at the base of the transistor Q12 at a potential intermediate between the potentials at the node Na.
And an emitter follower circuit 14 connected to the output node of the ECL circuit 12.

The transistor Q13 and the resistor R1 are connected to the current ia flowing through the transistor Q13 and the resistor R1.
The element constants are set so that 1/4 of the current i flowing in each of 1, SGSGn flows.
The transistors Q13 and Q14 have their bases connected to the collector of the transistor Q13 to form a current mirror circuit, and are designed such that the emitter sizes of Q13 and Q14 are 1: 2, so that the collector flowing to Q14 is The current ib is set to be twice the current ia flowing through Q13, that is, 1/2 of the current i of the 1-bit comparison circuit SG. The diodes D1 and D2 are designed to have the same characteristics.

The transistor Q13 is replaced with a diode, and similarly, the transistor Q13 is １ ／ of i and の of ib.
May flow. In short, ia <i
b, i, ia, so that the condition of i + ia> ib is satisfied.
ib may be determined. The output emitter follower circuit 14 includes a transistor Q20 having a collector connected to the power supply voltage Vcc and a base connected to the collector of the transistor Q12 of the ECL circuit 11, and a constant current source CI3 connected to the emitter of the transistor Q20. It is configured.

Next, the operation of the multi-bit comparison circuit will be described.

All 1-bit comparison circuits SG0, SG
When the input data Din and the comparison data Dcp match in 1, .SIGMA.SGn, a current flows through the transistor Q2 or Q4 whose collector is connected to the power supply voltage Vcc, and a current flows from the node Na. Do not pull. Therefore, the current flowing through the diode D1 on the base side of the transistor Q11 in the determination circuit 10 is equal to the current ia (= i / 4) flowing through the transistor Q13. On the other hand, the current ib flowing through the diode D2 on the base side of the transistor Q12 is always constant (i / 2). That is, ia <ib.

Incidentally, the amount of forward voltage drop of the diode depends on the current density flowing through the diode, and as shown by the solid line A in FIG. 4, the current density is much smaller than the voltage drop characteristic due to the resistance (broken line B). Has a characteristic that the voltage drop amount increases as the value increases. Therefore, node Na
Is higher than the potential of the node Nb by a forward potential difference based on the difference between the current densities of the two diodes D1 and D2. As a result, the transistors Q11 and Q12 forming the current switch have Q11 turned on, and Q1
By turning off the transistor 2, the collector voltage of the transistor Q12 becomes high, the transistor Q20 of the output emitter follower circuit is turned on, and a high-level (Vcc) signal is output.

On the other hand, 1-bit comparison circuits SG0, SG1,
When the input data Din does not match the comparison data Dcp in any of SGn, a current flows through the transistor Q1 or Q3 connected to the node Na in the mismatched 1-bit comparison circuit, and the current i is subtracted from the node Na. Become. Therefore, if the mismatch is 1 bit, the current flowing through the diode D1 on the base side of the transistor Q11 in the determination circuit 10 is equal to the extraction current i of the transistor Q1.
I + ia obtained by adding the current ia (= i / 4) flowing through
= 5i / 4.

At this time, the current ib flowing through the diode 2 on the base side of the transistor Q12 is always constant (i / 2).
Therefore, the current 5i / 4 flowing through the diode D1 becomes larger than the current ib (= i / 2) flowing through the diode D2, and the potential of the node Na becomes two diodes D1,
The potential of the node Nb becomes lower than the potential of the node Nb by a forward potential difference based on the difference in the current density of D2. As a result, transistors Q11 and Q12 forming the current switch are connected to Q11
Are turned off and Q12 is turned on, the collector voltage of Q12 is lowered, and the transistor Q20 of the output emitter follower circuit is turned off, and a low level (Vee) signal is output.

Further, the one-bit comparison circuits SG0, S
When the input data Din and the comparison data Dcp do not match in two or more of the circuits G1, .SIGMA.SGn, a current flows through the transistor Q1 or Q3 connected to the node Na in the mismatching 1-bit comparison circuit, and the mismatch does not occur from the node Na. The current for the number of circuits is drawn. Therefore, if the number of mismatches is k bits, the current flowing through the diode D1 on the base side of the transistor Q11 in the determination circuit 10 is the current ia (= i / 4) flowing through the transistor Q13 as the extraction current (i × k). Is added. However, unlike a resistor, as shown by a solid line A in FIG. 4, the voltage does not change so much even if the current increases, so that the potential change of the node Na, that is, the signal amplitude also decreases, and the speed of the comparison operation increases. It becomes possible.

FIG. 2 shows another embodiment of the multi-bit comparison circuit according to the present invention.

In this embodiment, an ECL circuit 15 is provided instead of the clamping diode D1 in the first embodiment, and the common emitter of the emitter-coupled transistor pair Q15, Q16 constituting the ECL circuit is connected to a one-bit comparison circuit SG.
0 to SGn connected to a common current extraction node Na,
This is to suppress the potential of the node Na. The clamp ECL circuit 15 includes one transistor Q
The base of the transistor 15 is applied with the potential of the connection node Nc of the series resistors R11 and R12 connected between the power supply voltage Vcc and the node Na, and the base of the other transistor Q16 is 0.1 to 0 lower than the power supply voltage Vcc. When a reference voltage Vref4 lower by about .2 V is applied, and the extraction current i flows through the resistors R11 and R12, the potential of the node Nc changes to the reference voltage Vref4.
The resistance values of R11 and R12 are set so as to be lower. The reference voltage Vref3 is (Vref4 / 2) + VBB
Only the power supply voltage Vcc.

In the multi-bit comparison circuit of this embodiment, if the input data Din and the comparison data Dcp match in all the 1-bit comparison circuits SG0, SG1,. Flows through the transistor Q2 or Q4 connected to the power supply voltage Vcc and does not draw current from the node Na, so that the node Nc of the ECL circuit for clamping 15 has a level close to Vcc, turning on the transistor Q15 and turning off the transistor Q16. Is done. As a result, the potential of the current extraction node Na becomes
The potential is set lower than Vcc by the base-emitter voltage VBE of transistor Q15. As a result, the judgment circuit 1
Transistor Q1 which forms the current switch within 0
1 and Q12, when Q11 is turned on and Q12 is turned off, the collector voltage of Q12 is increased and the transistor Q20 of the output emitter follower circuit is turned on to output a high level (Vcc) signal.

On the other hand, 1-bit comparison circuits SG0, SG1,
When the input data Din does not match the comparison data Dcp in any of SGn, a current flows through the transistor Q1 or Q3 connected to the node Na in the mismatched 1-bit comparison circuit, and the current i is subtracted from the node Na. Become. Therefore, a current i flows through the resistors R11 and R12, the node Nc of the clamping ECL circuit 15 becomes lower than the reference voltage Vref4, and the transistor Q15 is turned off.
16 is turned on. As a result, the potential of the current extracting node Na is made lower than Vref4 by the base-emitter voltage VBE of Q16. As a result, the transistor Q1 constituting the current switch in the decision circuit 10
1 and Q12, when Q11 is turned off and Q12 is turned on, the collector voltage of Q12 is lowered, the transistor Q20 of the output emitter follower circuit is turned off, and a low level (Vee) signal is output.

Further, the 1-bit comparison circuits SG0, S0
When the input data Din and the comparison data Dcp do not match in two or more of the circuits G1, .SIGMA.SGn, a current flows through the transistor Q1 or Q3 connected to the node Na in the mismatching 1-bit comparison circuit, and the mismatch does not occur from the node Na. The current for the number of circuits is drawn. Therefore, if the number of mismatches is k bits, the clamping ECL circuit 1
The current flowing through the resistors R11 and R12 in 5 is the sum (i × k) of the extraction currents. However, at this time, a current flowing from the transistor Q16 to the node Na flows through the clamp ECL circuit 16 in the same manner as in the case where one bit does not match. Therefore, the potential of the node Na is higher than Vref4 by Q16.
, The potential of the node Na hardly changes even if the extraction current increases, that is, the signal amplitude becomes small, and the comparison operation can be sped up.

FIG. 3 shows a configuration example of a cache memory as an example of an application system using the multi-bit comparison circuit. In the figure, reference numeral 100 denotes a multi-bit comparison circuit having a configuration as shown in FIG. 1, 20 denotes a tag array in which tag addresses are stored, and 30 denotes data in which data corresponding to tag addresses stored in the tag array is stored. The multi-bit comparison circuit 100 compares the tag portion of the input address with the tag address read from the tag array 20.
If all the bits match, a high-level signal H indicating a hit is output, the gates G0 to Gn are opened, and the data read from the data array 30 to the data register 40 at that time is output. . On the other hand, when even one bit does not match in the multi-bit comparison circuit 100, a low-level signal / M indicating a mishit is output.

When a signal / M indicating a mishit is output, a microprocessor or the like that receives the signal determines that there is no desired data in the data array 30 and accesses a main memory (not shown) to access the desired data. , Or transfer a block including the data to the cache memory to replace the block. In addition,
In FIG. 3, reference numeral 50 denotes a decoder for reading data from the tag array 20 and the data array 30 to decode an externally input address signal, and reference numeral 60 denotes a sense amplifier circuit for amplifying a signal read from the tag array 20.

As described above, the multi-bit comparison circuit of the above embodiment is provided with an exclusive-OR circuit composed of series gates and the like for the number of bits of data to be compared and taking a wired-OR logic of their outputs to perform ECL. Since a signal indicating match / mismatch is output by inputting the signal to a determination circuit including a circuit and the like, and the potential of the wired OR node is suppressed using a potential suppression circuit such as a diode, the number of gate stages of the determination circuit is reduced. And the delay time is shortened, and the potential of the wired-OR node is suppressed, so that the signal amplitude can be suppressed regardless of the number of mismatched bits, thereby achieving a high-speed comparison operation. This has the effect.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the embodiment, the 1-bit comparison circuits SG0 to SGn are configured by series gates composed of bipolar transistors.
It is also possible to configure a bit comparison circuit.

In the above description, mainly the case where the invention made by the present inventor is applied to a cache memory or an associative memory, which is the background of application, has been described. However, the present invention is not limited to this. The present invention can be widely used for a semiconductor integrated circuit having a circuit for determining coincidence between multi-bit data.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a multi-bit comparison circuit capable of operating at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a multi-bit comparison circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing a second embodiment of the multi-bit comparison circuit according to the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a cache memory as an example of a semiconductor integrated circuit including a multi-bit comparison circuit.

FIG. 4 is an explanatory diagram showing voltage-current characteristics of a diode.

[Explanation of symbols]

 SG0 to SGn 1-bit comparison circuit D1 Clamping diode 10 Judgment circuit 11 Bias circuit 12 ECL circuit 13 Constant voltage circuit 15 Clamping ECL circuit 20 Tag array (first memory unit) 30 Data array (second memory unit) 40 Data Register 100 Multi-bit comparison circuit

Claims (6)

[Claims] 1. A plurality of exclusive OR circuits for comparing corresponding bits of two data consisting of a plurality of bits,
A determination circuit that outputs a signal indicating a match or mismatch between the two data based on a wired logic result of the output of these exclusive OR circuits; and a potential suppression circuit that suppresses the potential of the wired logic node. A multi-bit comparison circuit, characterized in that: 2. The multi-bit comparison circuit according to claim 1, wherein said potential suppression circuit comprises a diode connected between a power supply voltage terminal and said wired logic node. 3. The determination circuit includes: a bipolar transistor having a base connected to the wired logic node; a bipolar transistor having a base applied with a reference voltage; and a constant current source commonly connected to the emitters thereof. An emitter-coupled logic circuit, a bias circuit for supplying a steady current smaller than the operating current of each of the exclusive OR circuits to the diode, a diode having characteristics corresponding to the diode, and connected in series with the diode. 3. A constant voltage circuit for generating the reference voltage by flowing a current corresponding to a steady current of the bias circuit.
2. The multi-bit comparison circuit according to 1. 4. The multi-bit comparison circuit according to claim 1, wherein said exclusive-OR circuit is constituted by a bipolar series gate. 5. A first memory unit for storing an index address, a second memory unit for storing data associated with the address, an input address and an address read from the first memory unit. A cache memory configured to output data read from the second memory unit when all bit matches are detected by the address comparison circuit. A cache memory, wherein the address comparison circuit is constituted by the multi-bit comparison circuit according to claim 1, 2, 3, or 4. 6. A first memory unit storing data to be searched to be compared with input search data, and a data comparing circuit for comparing the input search data with the data to be searched in the first memory unit. And data to be taken out when a match is determined by the data comparison circuit.
An associative memory including a memory unit, wherein the data comparison circuit is configured by the multi-bit comparison circuit according to claim 1, 2, 3, or 4.