JPH11110245A - Evaluation package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the integrated debugging including the real time properties at a low cost and with high accuracy by deciding whether the storage area storing an instruction to be analyzed is a specific area and analyzing the instruction stored in a mapped storage area when a specific storage area is decided. SOLUTION: A mapping means 15 performs the mapping to a storage area of a RAM 14 in regard to a specific storage area that has high access frequency while a program is executed among those storage areas of a ROM 11. A specific area discrimination means 16 decides whether the storage area storing an instruction to be analyzed by an execution control means 12 is a specific area among those storage areas of the ROM 11. When the means 16 decides a specific storage area, the means 12 analyzes the instruction that is stored in a storage area where the specific storage area is mapped among those storage areas of the RAM 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an evaluation package which is housed in a package compatible with a package to be mounted on a mass-produced machine, is integrated into an LSI, and performs a predetermined process based on a program built-in system.

[0002]

2. Description of the Related Art In recent years, terminals and other small electronic devices of mobile communication systems have many functions by mounting microprocessors and DSPs that are inexpensive, have high performance, and have low power consumption. It is becoming possible to flexibly adapt to needs.

[0003] Among such electronic devices, in particular, for an apparatus that requires real-time performance and in which a program for determining the functions of the microprocessor or DSP described above is written in a mask ROM during mass production, the real-time performance is required. The process of debugging the program including the confirmation of the process and the process of designing the mask pattern and manufacturing the engineer sample to be performed in parallel for this mask ROM are factors that influence the flow of the overall production process. Probability is high.

Accordingly, in the process of developing such a device, a rewritable PROM is used to efficiently perform the above-described comprehensive test including real-time performance while accurately simulating the operating environment in the field. Evaluation packages that can be used instead of mask ROMs and that can be replaced are often used. FIG. 6 is a diagram illustrating a configuration example of a DSP mounted on a mass production machine.

In FIG. 1, a register file 92, a data memory 93, and an operation unit 94 are connected to an internal bus 95 in addition to an input / output register 91 forming an input / output port.
2. The data memory 93 and the operation unit 94 are connected to corresponding input / output terminals of the program control unit 96. An output of the program control unit 96 is connected to an address terminal of a mask ROM 97, and a data output of the mask ROM 97 is connected to a corresponding input of the program control 96 via an instruction register 98 and an instruction decoder 99.

In the DSP having such a configuration, a program for realizing desired signal processing is stored in the mask ROM 97 in advance, and the mask ROM 97 is stored in the program control unit 9.
The instruction code (machine language) stored at the address specified by 6 is held in the instruction register 98. The instruction decoder 99 decodes the instruction code, and the program control unit 96 determines an area of the mask ROM 97 in which a subsequent instruction code is stored based on the result of the decoding (hereinafter, such an operation is referred to as “execution control”). "). Further, the program control unit 96 includes an input / output register 91,
Among the register file 92, the data memory 93, and the operation unit 94, the one related to the execution of the instruction decoded as described above is instructed to perform an operation necessary for the execution of the instruction.

On the other hand, the input / output register 91 transfers predetermined information between the outside and the register file 92 or the data memory 93 under the control of the program control unit 96. The operation unit 94 similarly performs an operation on the data stored in the register file 92 and / or the data memory 93 under the control of the program control unit 96, and outputs the result of the operation to these register files. 92 or the data memory 93.

That is, the input / output register 91, the register file 92, the data memory 93, and the operation unit 94
The above-described operation is repeated as appropriate according to a procedure determined by a program stored in the mask ROM 97 in advance, so that signal processing based on a program built-in method is realized. By the way, in the process of developing and debugging a program to be stored in the mask ROM 97, the mask ROM
Since the memory element 97 is not a rewritable memory element, for example, as shown in FIG. 7, a PROM 101 which substitutes the memory element and a scan path described later (here, for simplicity, JTAG (Joint Test Action Group )
Assume that it conforms to the /IEEE1149.1 standard and can be shared with scan tests. An evaluation package including an address buffer (AB) 103 that enables the PROM 101 to be accessed by both the scan path 102 and the program control unit 96 is used.

Hereinafter, the above-mentioned evaluation package is referred to as a “first conventional example”. In such an evaluation package, when a program stored in the PROM 101 is to be updated, the scan path 102 stores, in the PROM 101, a sequence of instruction codes indicating a new program from outside and these instruction codes. An address of an area to be written and a write command are given.

Therefore, the contents of the PROM 101 are appropriately rewritten, and the contents are updated, whereby debugging of the above-described program proceeds. As prior art related to the present invention (hereinafter referred to as "second conventional example"), for example, as disclosed in Japanese Patent Application No. 4-199425, PROM and its PRO are disclosed.
There is a control program development device that replaces the mask ROM by copying all the contents of the M storage area and has a static RAM (hereinafter, referred to as “SRAM”) used for debugging.

[0011]

In the first conventional example described above, since the access time of the PROM 101 is longer than the access time of the mask ROM 97, for example,
Debugging including confirmation of real-time performance, such as "processing of audio signals divided in units of frames is surely completed for each frame cycle", is impossible.

Further, as a technique for confirming such a real-time property, a combination of modules relating to a functional unit among modules constituting a program to be debugged is individually written in the PROM 101. Several evaluation packages are available,
There is a method in which these evaluation packages are appropriately replaced during debugging.

However, such a method is inefficient because the debugging process is unnecessarily divided due to replacement of the evaluation package, and it is impossible to confirm the real-time performance comprehensively. Was. In the second conventional example, the SRAM is a PROM or a mask ROM.
Although the access time is shorter than that of the above, since the circuit scale per storage area is large, it is difficult to arrange as an alternative circuit in the area where the mask ROM is to be arranged among the areas of the chip where the mask ROM is to be mounted. Was.

That is, since the layout on the chip accommodated in the evaluation package is different from the layout of the chip on which the mask ROM is to be mounted, unnecessary cost is required, and the characteristics of the circuits other than the SRAM are not necessarily required. No compatibility with the chip was obtained. Furthermore, if it is essential to use a chip larger than the chip on which the mask ROM is to be mounted, the package that can accommodate the large chip will also be large, so the package to be mounted on a mass production machine will be large. It has been difficult to realize an evaluation package that can be replaced.

[0015] It is an object of the present invention to provide an evaluation package which can perform comprehensive debugging including real-time processing at low cost and with high accuracy.

[0016]

FIG. 1 is a block diagram showing the principle of the present invention.

According to the first aspect of the present invention, a ROM 11 in which a program is stored in advance and which can be rewritten,
An execution control means 12 for reading and analyzing a program stored in a ROM 11 in instruction units, and an operation execution means 1 for executing an operation of the instruction analyzed by the execution control means 12
3, a RAM 14 having a smaller storage area size than the ROM 11 and having a shorter access time, and a specific storage area which is frequently accessed during the execution of a program among the storage areas of the ROM 11. Mapping means 15 for performing mapping;
Specific area determining means 16 for determining whether or not the storage area in which the instruction analyzed by the execution control means 12 is stored is a specific storage area among the storage areas of M11;
When the result of the discrimination performed by the specific area discriminating means 16 is true, the execution control means 12 maps a specific one of the storage areas of the RAM 14 where the result of the discrimination is obtained. The analysis is performed on the instructions stored in the.

According to a second aspect of the present invention, in the evaluation package according to the first aspect, the specific storage area is indicated as information stored in the ROM 11. According to a third aspect of the present invention, in the evaluation package according to the first aspect, a ROM is provided.
For each single or a plurality of instructions stored in the storage area 11, the frequency analyzed by the execution control means 12 is measured, and the storage areas storing these instructions are stored in the storage area of the RAM 14 in descending order of the frequency. And a specific area selecting means 21 for selecting a specific storage area within the range of the size, and the mapping means 15 performs mapping for the specific area selected by the specific area selecting means 21.

According to a fourth aspect of the present invention, in the evaluation package according to any one of the first to third aspects, the execution control means 12 includes a specific area determining means 16 in a storage area of the RAM 14. Means for shortening the cycle time required for reading an instruction to a value adapted to the access time of the RAM 14 for a storage area to which a specific storage area for which the result of determination made by the above is true is mapped. I do.

According to a fifth aspect of the present invention, in the evaluation package according to any one of the first to fourth aspects, the arithmetic execution means 13 executes, for each operation target given in a predetermined format, Processing delay monitoring means for measuring the required execution time of the processing performed in the procedure of the operation to be performed, comparing the required execution time with a preset upper limit value and the required execution time, and obtaining a magnitude relationship between the two. 31 is provided.

In the evaluation package according to the first aspect of the present invention, a program is stored in the ROM 11 in advance. The mapping means 15 includes the ROM 1
One of the storage areas, which is frequently accessed in the process of executing the above-described program, is assigned a R
The mapping to the storage area of the AM 14 is performed. The execution control means 12 reads and analyzes the above-mentioned program in instruction units, and the operation execution means 13 executes the operation of the instruction thus analyzed.

In the process of performing the arithmetic operation in this manner, the specific area determining means 16 determines that the storage area in which the command analyzed by the execution control means 12 has been stored as described above among the storage areas of the ROM 11. It is determined whether the storage area is the specific storage area described above. When the result of the determination is true, the execution control means 12 analyzes the instruction stored in the storage area of the storage area of the RAM 14 to which the specific storage area from which the result of the determination is obtained is mapped. set to target.

The RAM 14 has a ROM 11
And the access time is short. Therefore, as long as the size is equal to or larger than the sum of the sizes of the main specific areas in the storage area of the ROM 11, the rewriting of the ROM 11 is appropriately performed, so that the real-time performance can be checked while the size of the RAM 14 is kept small. Debugging of the above-described program is efficiently and accurately performed.

[0024] In the evaluation package according to the second aspect of the present invention, in the evaluation package according to the first aspect, the specific storage area is an R storage.
It is shown as information stored in OM11. That is,
Since a specific storage area to be mapped to the storage area of the RAM 14 among the storage areas of the ROM 11 is reliably specified without using a dedicated external terminal or a test scan path, the efficiency and reliability of debugging are reduced. Enhanced.

In the evaluation package according to the third aspect of the present invention, in the evaluation package according to the first or second aspect, the specific area selecting means 21 is a single or a single area stored in the storage area of the ROM 11. The frequency of analysis by the execution control means 12 is measured for each of a plurality of instructions, and the storage area storing these instructions is selected as a specific storage area within the range of the storage area of the RAM 14 in descending order of the frequency. I do. further,
The mapping means 15 performs mapping for the specific area selected in this way.

Therefore, in the storage area of the ROM 11,
3. Debugging of a program including confirmation of real-time performance in the same manner as the evaluation package according to claim 1 or 2, even when a specific storage area frequently accessed is changed by some factor. Is efficiently and accurately performed. In an evaluation package according to a fourth aspect of the present invention, in the evaluation package according to any one of the first to third aspects, the execution control means 12 determines a specific area in the storage area of the RAM 14. For a storage area to which a specific storage area for which the result of the determination made by the means 16 is true is mapped, the cycle time required for reading an instruction is reduced to a value adapted to the access time of the RAM 14.

That is, since the instruction mapped to a specific storage area is read out faster as the access time of the RAM 14 is shorter, it is stored in the storage area of the ROM 11 within the time required for the execution of the operation performed by the operation executing means 13. The delay caused when reading the instruction is reliably compressed. In an evaluation package according to a fifth aspect of the present invention, in the evaluation package according to any one of the first to fourth aspects, the processing delay monitoring means 31 is provided in a predetermined format. For each calculation target, the required execution time of the processing performed in the procedure of the calculation execution performed by the calculation execution means 13 is measured, and the required execution time is compared with a preset upper limit value and this required execution time. Obtain the magnitude relationship between the two.

That is, since it is determined in real time whether or not desired real-time characteristics and responsiveness are achieved, the accuracy of debugging is enhanced.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 is a diagram showing an embodiment corresponding to the first to fifth aspects of the present invention. In the figure, components having the same functions and configurations as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted here. The difference between this embodiment and the conventional example shown in FIG.
101, a RAM 61 having a storage capacity smaller than that of the PROM 101, a program control unit 62 in place of the program control unit 96, and a transfer execution control unit connected to the program control unit 62 and the scan path 102. An address buffer (AB) 103a is provided in place of the address buffer 103, and a first output of the transfer execution control unit 63 is
3a, the second output of the transfer execution control unit 63 is connected to one input of an address buffer (AB) 64, and the address output of the program control unit 62 is connected to the address buffer 103a. And the output of the address buffer 64 is connected to the RAM 61.
At the point connected to the address input.

The correspondence between the present embodiment and the block diagram shown in FIG.
, The program control unit 62 corresponds to the execution control unit 12, the instruction register 98, the instruction decoder 99, and the program control unit 62 correspond to the operation execution unit 13,
M61 corresponds to the RAM 14, and includes the scan path 102, the transfer execution controller 63, and the address buffers 103a and 103a.
4 corresponds to the mapping means 15, the specific area discriminating means 16, and the specific area selecting means 21.

FIG. 3 is a diagram for explaining the operation of the present embodiment corresponding to the first, second and fourth aspects of the present invention. Less than,
The operation of the present embodiment according to the first, second, and fourth aspects will be described with reference to FIGS.

A program to be debugged is stored in the PROM 101 in advance as in the conventional example. Among instruction codes constituting such a program, a sequence of instruction codes indicating a procedure of frequently executed operation (for example, an operation of calculating a product sum at a high frequency to realize a filtering process) is stored. The address and size of the area (hereinafter, referred to as “copied area”) are specified in advance based on the configuration of the corresponding program, and the scan path 102
To the transfer execution control unit 63 via

For simplicity, the addresses and sizes of these copied areas are as shown in FIG.
In the storage area of the PROM 101, an N1 word area (hereinafter, referred to as a "first area") adjacent to an area indicated by an address A1, and an N2 word area (hereinafter, referred to as "first area") adjacent to an area indicated by an address A2. "Second region").

When the combination (A1, N1) and (A2, N2) of the address and the size are given to the first area and the second area, the transfer execution control unit 63 temporarily holds the combination. The instruction codes and constant strings stored in the first area and the second area are stored in the RA.
After copying into the first N1 byte area and the following N2 byte area in the storage area of M61, the program control unit 62 is notified of this.

When recognizing the notification, the program control unit 62 performs execution control in the same manner as in the conventional example, thereby
The addresses are sequentially output to the OM 101. The transfer execution control unit 63 determines that such an address is one of A1 to A1 + (N1-1) or A2 to A2 + (N2-1) (an address indicating one of the first area and the second area). Is determined, and if the result of the determination is false, the RAM 61
And the reading of the PROM 101 is permitted.

The PROM 101 has a program control unit 62
The instruction code stored in the area indicated by the address given by is given to the instruction register 98. However, if the result of the above determination is true, the transfer execution control unit 63 restricts reading of the PROM 101 and permits reading of the RAM 61 instead of the PROM 101.

The transfer execution control section 63 outputs an offset address to be applied to the normal addressing for one of the first area and the second area where the above-mentioned reading is permitted. Further, the RAM 61 is provided with a mapping address indicated by the sum of the above-described offset address via the address buffer 64 and a part of the address provided by the program control unit 62, and is stored in an area indicated by the mapping address. The instruction code is given to the instruction register 98.

When the result of the above-mentioned determination is false, the transfer execution control section 63 gives a WAIT signal to the program control section 62. On the contrary, when the result is true, the transfer execution control section 63 gives the WAIT signal. Absent. As described above, according to the present embodiment, only the sequence of instruction codes that are likely to be executed frequently are stored in the RAM 61 having a short access time,
Instruction codes not included in these instruction code strings are PR
In addition to being stored in the OM 101, these instruction codes are sequentially executed at high speed while maximizing the access time of the RAM 61.

That is, since the size of the RAM 61 to be mounted is kept small and real-time performance is secured with high accuracy, comprehensive debugging and performance confirmation can be performed as compared with the first and second conventional examples. It is performed inexpensively and efficiently. In the present embodiment, the addresses and sizes of the first area and the second area are externally set to the scan path 10.
2 are provided to the transfer execution control unit 63 via the PROM 10.
1 is written in a predetermined area of the storage area,
At the time of start-up, the transfer execution control section 63 may read these areas to be similarly provided.

In the present embodiment, the contents of the first area and the second area are stored in the RAM by the transfer execution control unit 63.
Although the copy is performed for the corresponding area 61, for example, the copy may be performed in the same manner in the process of executing the initialization program written in the PROM 101. Further, in the present embodiment, for the WAIT signal described above,
In the bus cycle in which no pulse width is indicated and the RAM 61 is accessed, the program control unit 62
Has not been given to anything. However, the WAIT
The signal may have any pulse width if the debugging of the program accompanied by the confirmation of the real-time property is performed reliably, and the signal is given to the program control unit 62 in a bus cycle in which the RAM 61 is accessed. You may be.

FIG. 4 is a diagram for explaining the operation of the present embodiment corresponding to the third aspect of the present invention. The difference between the present embodiment and the embodiment corresponding to the first, second, and fourth aspects is that the content of the storage area of the PROM 101 is RAM
The area is copied to the storage area 61 and the area to be replaced by the RAM 61 is appropriately updated as described below.

In the following, for the sake of simplicity, it is assumed that none of the storage areas of the PROM 101 is replaced by the storage area of the RAM 61 at startup. Transfer execution control unit 63
Is a PROM 101 and a RAM 6 as shown in FIG.
One storage area is managed for each block composed of adjacent areas with a predetermined size (here, 64 words are assumed for simplicity).

In the following, the area of the PROM 101 is composed of K blocks, and the area of the RAM 61 is L
Assume that it is composed of (<K) blocks. further,
The transfer execution control unit 63 has a count register individually corresponding to these K blocks.

The transfer execution control unit 63 is an address consisting of only upper bits used for identifying the K blocks among the addresses given by the program control unit 62 (hereinafter, referred to as “upper address”). ) Is extracted and the value of the count register corresponding to the upper address of the K count registers corresponding to these blocks is integrated based on the moving average method.

Therefore, as shown in FIG. 4, the frequency (histogram) at which the instruction codes stored in the first to Kth blocks in the storage area of the PROM 101 are executed is stored in each of the K counting registers. The integrated value shown is obtained. Hereinafter, the process of obtaining the integrated value in this manner is referred to as “training”. The transfer execution control unit 63
For example, every time signal processing for a predetermined number of frames is completed, or every time a predetermined period elapses,
Among the K counting registers described above, the Ps corresponding to the first to L-th registers in descending order of the held integrated value.
A block of the ROM 101 (hereinafter, referred to as “substituted block”) is specified.

Further, the transfer execution control unit 63
1 and manages the areas of the L blocks included in the first block. Of these blocks, blocks other than the blocks to be continuously allocated to the same block to be replaced (hereinafter referred to as “new replacement block” and the new replacement block) The block to which is to be allocated is referred to as a “new replacement block.”) Is allocated under this area management.

Further, the transfer execution control unit 63 sequentially copies the contents of the corresponding new substitutive blocks based on the cycle stealing method for each of the new substitutive blocks newly allocated in this manner, and performs the duplication. Is completed, an existing “substitute block” is identified, and a corresponding new substituted block is identified as an existing “substitute block”.

Further, the transfer execution control unit 63 manages the correspondence between each of the blocks to be replaced and the replacement blocks under the above-described area management, and furthermore, these replacement blocks i (1 ≦ 1).
For (i ≦ L), it is determined whether or not the combination (Ai, Ni) of the head address Ai and the size Ni corresponds to the area given by the address given by the program control unit 62 and the result of the determination Is false, the PROM 101 is read while the reading of the RAM 61 is regulated.
Is read.

However, if the result of the determination is true, the transfer execution control unit 63
While reading from the RAM 61 is restricted. That is, according to the present embodiment, the frequency of access to the area of the PROM 101 is monitored on a block basis, and the block with the high frequency is replaced by the area of the RAM 61. The area of the RAM 61 is determined in real time as compared with the embodiment corresponding to the invention according to claim 1, which is determined in advance based on the structure of the program and is not updated in the process of executing the program. RAM6 that can be used flexibly for debugging including
The restriction on debugging according to the upper limit of the size of 1 is relaxed.

Although the moving average method is applied in the present embodiment, for example, counting by simple integration or integration based on exponential smoothing may be performed for each frame to be processed. Further, in the present embodiment, the size of the block is kept constant. However, the size is, for example, reduced in real time by applying an embodiment corresponding to the invention described in claim 5 described later. If the unsecured state is frequently detected, the number may be appropriately increased or decreased.

Further, in the present embodiment, no method for calculating the size of the RAM 61 is described. However, the size of the RAM 61 is determined within the storage area of the PROM 101.
Any value may be set as long as it is equal to or greater than the product of the size and number of blocks to be replaced in parallel by 61.

Hereinafter, an embodiment corresponding to the invention described in claim 5 will be described. The difference between this embodiment and the embodiment corresponding to the first to fourth aspects of the present invention is that the control output of the program control unit 62 and the corresponding output of the scan path 102 are indicated by a dotted line in FIG. Is connected to a real-time determining unit 65, and the output of the real-time determining unit 65 is such that a determination signal described later is obtained.

FIG. 5 is a diagram showing the configuration of the real-time determination unit. In the figure, an output of the above-described scan path 102 is connected to an input of a threshold register 71, and an output of the threshold register 71 is connected to one input of a comparator 72. The other input of the comparator 72 is connected to the output of the execution cycle counter 73, and the count input of the execution cycle counter 73 is supplied with a clock signal from a clock generation circuit (not shown). Execution cycle counter 73
Is connected to the control output of the program control unit 62.

The correspondence between the present embodiment and the block diagram shown in FIG. 1 is the same as the correspondence described above, except that the real-time determination unit 65 corresponds to the processing delay monitoring means 31. is there. Hereinafter, the operation of the present embodiment will be described with reference to FIGS. The threshold register 71 stores the maximum execution time required to complete the signal processing in real time for each frame (here, it is assumed that the frame is an audio frame for simplicity) to be subjected to signal processing. A bit string indicating a value is given from the outside via the scan path 102 in advance.

When no frame to be subjected to the above-mentioned signal processing is given, the program control unit 62 forcibly resets the execution cycle counter 73 because there is no need to perform any real-time processing. This restricts the execution cycle counter 73 from counting clock signals.

Further, when starting the above-described signal processing for a new frame, the program control unit 62 allows the counting operation of the execution cycle counter 73, and the execution cycle counter 73 sets the period during which such signal processing is performed. Counts the clock signal described above. Therefore,
The count value given by the execution cycle counter 73 indicates the time required for the signal processing for each frame described above.

The comparator 72 compares the count value with the maximum value held in the threshold register 71 as described above, and outputs a determination signal indicating that the former exceeds the latter, if so. As described above, according to the present embodiment, the time required for calculation is increased to such an extent that the real-time property is not maintained.
Since the identification is reliably performed, debugging and evaluation of the overall performance of the device on which the DSP according to the present embodiment is mounted can be performed with high accuracy, and the RAM 61 is combined with the size and number of the blocks described above. Size and PRO
The arrangement of the programs stored in M101 can be efficiently optimized.

In the present embodiment, the above-described determination signal is output to the outside of the DSP via a specific pin. However, the determination signal may be output to the outside via the scan path 102, for example. Are stored in a specific status register (not shown) constituting the register file 92, or stored in a specific area of the data memory 93, and are appropriately referred to in the course of processing of a program for realizing signal processing, and It may be used as an activation factor or the like of an appropriate process.

In each of the above-described embodiments, a DSP having an instruction system with a fixed word length stores a PR in which an instruction code constituting a program to be debugged is stored.
Although the storage area of the OM 101 is replaced by the storage area of the RAM 61, the present invention provides a D
It is also applicable to SP.

Further, PRO thus substituted
The storage area of M101 is not limited to the storage area in which the instruction code is stored. For example, the storage area in which constants such as coefficients defining the filtering characteristics are stored when the access frequency is high is the same. To be replaced. In each of the embodiments described above, the inventions described in claims 1 to 5 are applied to a DSP.
The processor is not limited to P, and performs a predetermined information processing based on a program built-in method, is implemented as an LSI, and is required to perform the information processing in real time.
The present invention can be applied to a microprocessor or any other information processing device.

Further, in each of the above-described embodiments, the transfer execution control unit 63 and the real-time property determination unit 65 are configured as dedicated hardware. May be partially or entirely constituted by a single or a plurality of processors realizing equivalent functions. In each of the above-described embodiments, the format of the RAM 61 is not shown at all. However, if the access time is shorter than that of the PROM 101 and the power consumption and other environmental conditions are adapted, a static R
The invention is not limited to the AM, and a dynamic RAM may be applied.

Further, in each of the above-described embodiments, each block is configured as a set of a plurality of predetermined words. However, if area management and mapping based on the area management are reliably performed, these blocks may be used. The block of
It may consist of a single word or a different number of words.

[0064]

As described above, according to the first aspect of the present invention, as long as the size of the RAM is equal to or larger than the sum of the sizes of the main specific areas in the storage area of the ROM, the rewriting of the ROM is appropriately performed. By doing so, debugging including confirmation of real-time performance is efficiently and accurately performed while the size of the RAM is kept small.

Further, in the invention according to the second aspect, the efficiency and reliability of debugging are improved as compared with the invention according to the first aspect. Further, according to the third aspect of the present invention, even if a specific storage area that is frequently accessed among the storage areas of the ROM changes due to some factor, As in the invention, debugging of a program including confirmation of real-time performance is efficiently and accurately performed.

According to the fourth aspect of the present invention, the delay generated when reading the instruction stored in the storage area of the ROM in the required operation time is reliably compressed. Further, in the invention according to the fifth aspect, the accuracy of debugging is enhanced as compared with the inventions according to the first to fourth aspects. That is, electronic devices to which these inventions are applied are:
Comprehensive function and performance inspections and confirmation of characteristics in almost the same operating environment as the field
In addition, since it is performed accurately and at low cost, the reliability is improved and the cost is reduced.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the invention according to claims 1 to 5;

FIG. 2 is a diagram showing an embodiment corresponding to the first to fifth aspects of the present invention.

FIG. 3 is a diagram for explaining the operation of the present embodiment corresponding to the invention described in claims 1, 2 and 4;

FIG. 4 is a diagram for explaining the operation of the present embodiment corresponding to the invention described in claim 3;

FIG. 5 is a diagram illustrating a configuration of a real-time property determination unit.

FIG. 6 is a diagram illustrating a configuration example of a DSP mounted on a mass production machine.

FIG. 7 is a diagram illustrating a configuration example of an evaluation package of the DSP illustrated in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ROM 12 execution control means 13 arithmetic execution means 14,61 RAM15 mapping means 16 specific area discrimination means 21 specific area selection means 31 processing delay monitoring means 62,96 program control part 63 transfer execution control parts 64,103,103a address buffer (AB) 65 real-time determination unit 71 threshold register 72 comparator 73 execution cycle counter 91 input / output register 92 register file 93 data memory 94 operation unit 95 internal bus 97 mask ROM 98 instruction register 99 instruction decoder 101 PROM 102 scan path

Claims (5)

[Claims] A ROM in which a program is stored in advance and which can be rewritten; an execution control means for reading and analyzing the program stored in the ROM in instruction units; An arithmetic execution unit for performing an arithmetic operation; a RAM having a smaller storage area size than the ROM and having a shorter access time; and a specific storage area of the storage area of the ROM which is frequently accessed during the execution of the program. Mapping means for mapping a storage area to the storage area of the RAM; and whether or not a storage area in the ROM storage area in which an instruction analyzed by the execution control means is stored is the specific storage area And a specific area determining means for determining whether the specific area is determined. When the result of the discrimination is true, an instruction stored in a storage area to which a specific storage area from which the result of the discrimination is obtained is mapped out of the storage areas of the RAM. Evaluation package featuring 2. The evaluation package according to claim 1, wherein the specific storage area is indicated as information stored in a ROM. 3. The evaluation package according to claim 1, wherein a frequency analyzed by the execution control means is measured for each of a single or a plurality of instructions stored in a storage area of the ROM, and the frequency is measured in descending order. And a specific area selecting means for selecting a storage area in which these instructions are stored as a specific storage area within a range of the size of the storage area of the RAM. An evaluation package that performs mapping. 4. The evaluation package according to claim 1, wherein the execution control means determines that a result of the determination made by the specific area determination means in the storage area of the RAM is true. An evaluation package comprising means for reducing a cycle time required for reading an instruction to a value adapted to an access time of the RAM, for a storage area to which a specific storage area is mapped. 5. The evaluation package according to claim 1, wherein each of the calculation objects provided in a predetermined format is executed by an operation execution unit. A processing delay monitoring means for measuring a required execution time of the processing to be performed, comparing the required execution time with a preset upper limit value and the required execution time, and obtaining a magnitude relationship between the two. Evaluation package.