JPWO2002073411A1 - Memory test method, information recording medium, and semiconductor integrated circuit - Google Patents

Abstract

A method for testing a memory of a semiconductor integrated circuit having a CPU (102) provided with an instruction queue (103), memories (107, 108), and a bus (105) connecting the CPU and the memory includes: The test program is executed by the CPU, the memory is accessed via the bus by executing the test program, and the fetch of the test program after the test program is once stored in the instruction queue is repeatedly performed from the instruction queue instead of the bus. By the loop queue operation of the instruction queue, no branch instruction is required to enable the same test program to be repeatedly executed. The test program to be repeatedly executed may be repeatedly fetched from the instruction queue, and the memory read / write access for the memory test and the memory access for the instruction fetch do not conflict on the bus. The test efficiency of an on-chip memory of a semiconductor integrated circuit is improved.

Description

Technical field
The present invention relates to a technique for testing an on-chip memory in a semiconductor integrated circuit, and more particularly to a technique effective when applied to a test method for a system LSI such as a data processing device, a microprocessor, and a single-chip microcomputer having a memory.
Background art
With the development of microfabrication technology, very large-scale circuits can be mounted on semiconductor integrated circuits (LSIs). Therefore, the capacity of a memory circuit such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or a flash memory mounted on a system LSI such as a single-chip microcomputer has been dramatically increased. These memory circuits are mounted at higher density than logic circuits such as a CPU (Central Processing Unit), and circuits such as memory cells and sense amplifiers are analog circuits. Required. For this reason, a test mode is provided in which the LSI can be operated or controlled as if it were a single memory IC (Integrated Circuits) only at the time of testing, and a test similar to the single memory IC is performed from an external tester. Methods have been used. However, as the operating speed of the system LSI increases, there is a problem that a more sophisticated and expensive tester corresponding to both the logic IC and the memory IC is required, and the test time is increased because the test is divided into two passes. . For this reason, a memory BIST (Build-In Self Test) circuit has been provided which generates a test pattern inside the chip and supports the test.
As a memory BIST technology, as described in Japanese Patent Application Laid-Open No. 2000-30483, a sequencer for generating a test pattern and a device for generating data to be read / written are fixedly embedded in a chip as hardware, As described in JP-A-11-15740, a simple memory test processor is built in, a test program is externally supplied to the processor at the time of testing, and the program is executed to generate a test pattern by software. And so on. However, in the former method, it is necessary to determine a test method at the time of design, and it is difficult to cope with various failure events of the memory. In recent years, the CPU core is distributed as IP (Intellectual Property) module data, and can be created by processes of various manufacturers. Therefore, various modes can be assumed for a memory failure event. Therefore, it is advisable that the test pattern is fixed. Not. In the latter method, the test pattern can be determined at the time of an actual test, not at the time of design, so that it has high flexibility and is suitable for the IP conversion of the CPU core. This requires a large amount of hardware resources and increases the chip area, which is problematic in terms of cost. Further, it is necessary for a test designer to write a test program in a special language, and it is not preferable to assume module data used by various users.
As a processor for executing the test program, a CPU used in a normal operation may be used in addition to a processor dedicated to the test. For example, as described in Japanese Patent Application Laid-Open No. 10-511790, the test program is stored in an internal memory. There is a method of arranging the test program in a part of the cache memory, which is a kind, causing the CPU to execute the test program, and testing the rest of the cache memory. By using this method, the amount of hardware to be added for testing can be reduced, so that there is an advantage that the chip manufacturing cost can be reduced. In addition, since the test program is not limited to a dedicated processor but may be provided for a CPU that is normally used, there is an advantage that a test program can be created in an assembly language or the like to which a user is familiar.
However, in the above-described conventional technique of performing a test by causing a CPU to execute a program, a test of the remaining built-in memory is performed in a state where a test program is arranged in a part of a built-in memory such as a cache memory. Have been found by the present inventors.
First, when memory access for instruction fetch and test conflicts with the bus connecting the CPU and the built-in memory, there is a possibility that a stall may occur with respect to instruction execution of the CPU, and the test efficiency is reduced. Was. In addition, since the CPU determines whether the cache memory is good or not, the CPU needs to execute an instruction for determining whether the data read from the cache memory matches the expected value. There is a problem that the ratio of instructions to be executed is reduced, and the test time is longer than that of the BIST technology using a dedicated test sequencer. In short, in addition to executing instructions for memory read access and write access for the memory test, the number of instruction executions for comparison and the like increases, and the memory test time relatively increases. In addition, the memory test program is to execute a certain operation such as memory read / write over the entire area of the memory by changing only the address. Therefore, the memory test program needs to be a loop type program. Instructions are required, which also reduces the ratio of read / write instructions. In a CPU without a branch prediction function, a branch instruction itself requires a plurality of execution cycles, so that the number of cycles required for a test increases more than the number of instructions increases. Furthermore, since the CPU cannot usually access a plurality of memories having different address mappings at the same time, there are a plurality of memories to be tested or a case where the memories are divided into a plurality of pages (a plurality of memory blocks). However, these memories cannot be accessed in parallel to perform a test, and the test must be performed sequentially, resulting in a longer test time.
As a memory test sequence, for example, there is a method called a 13N test. The 13N test is discussed in IEE Design and Test of Computers February (1989) pp. 26-34 (IEEE DESIGN & TEST OF COMPUTERS, FEBRUARY 1989, pp. 26-34). This is a test method for SRAM, which is generally known as a test for a built-in memory of a system LSI. In the 13N test, for example, pattern 0 is written to the entire memory area in the ascending order of the address, and the processes of reading the written pattern 0, writing the pattern 1, and reading the pattern 1 are executed in ascending order for each address. The read data is compared with the expected value. In order to perform such processing by executing the program of the CPU, a read command for pattern 0, a write command for pattern 1, a read command for pattern 1 and an increment instruction for address, a match determination command for pattern 0 data, and a pattern 0 mismatch were found. In this case, a branch instruction for performing error processing, a pattern 1 data match determination instruction, a branch instruction for performing error processing when pattern 1 does not match, a loop counter decrement and loop end determination instruction, and a loop not completed In such a case, a program including a branch instruction to the head of the loop or the like must be used. As is apparent from the example of the program, the number of instruction execution cycles such as the match determination, branch, and the decrement instruction of the loop counter is larger than that of the memory read instruction or the write instruction.
An object of the present invention is to efficiently determine a test sequence at the time of test execution, not at the time of chip design, and to use a CPU as a sequencer to reduce the amount of hardware resources required for a test. The purpose of the present invention is to provide a method that can be tested.
Another object of the present invention is to provide a semiconductor integrated circuit that can easily realize the above-described test method for a built-in memory.
Still another object of the present invention is to provide an information recording medium storing IP module data such as a CPU, which can contribute to shortening a development period of a semiconductor integrated circuit which can easily realize the above-described built-in memory test method. It is in.
Another object of the present invention is to provide a method for testing a CPU and an on-chip memory accessed by the CPU, and a test program capable of contributing to an improvement in development efficiency of a semiconductor integrated circuit and information recording circuit design data. It is to provide a recording medium.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Disclosure of the invention
[1] << Memory test method >> In a memory test method for testing a memory of a semiconductor integrated circuit having a CPU having an instruction queue, a memory, and a bus connecting the CPU and the memory, a test program is stored in the instruction queue. The CPU executes the test program to perform memory access via the bus, and the fetch of the test program once the test program is stored in the instruction queue is repeatedly performed from the instruction queue instead of the bus. Is what you do.
Similarly, a memory test method for testing the memory of a semiconductor integrated circuit having a CPU having an instruction queue, a memory connected to the CPU via a bus, and a determination circuit connected to the memory and the bus, comprises: The test program is stored in the instruction queue, the test program is executed by the CPU to perform memory write access and memory read access, and the memory read access data is compared and determined by the determination circuit with an expected value. The fetch of the test program after the execution is repeatedly performed from the instruction queue instead of the bus.
First, the memory test method employs a repeat operation in which the read pointer of an instruction queue in a FIFO (First-In First-Out) format is cyclically looped and the same storage information is used a plurality of times. There is no need to use a branch instruction to make the program repeatedly executable. Second, a test program to be repeatedly executed may be repeatedly fetched from the instruction queue, so that memory read / write access for a memory test and memory access for an instruction fetch do not conflict on the bus. Therefore, the branch instruction can be eliminated from the test program, and since there is no need to repeatedly fetch the same instruction from the bus connected to the CPU, a memory access instruction such as a move instruction for truly performing a memory test can be executed. Therefore, the test efficiency of the semiconductor integrated circuit for the on-chip memory can be improved.
In the above test method, the content is determined by the test program of the CPU, and the test sequence can be determined not at the time of chip design but at the time of test execution. As a result, the on-chip CPU is used as a test sequencer for the semiconductor integrated circuit to be tested. By doing so, it becomes extremely easy to adopt the BIST method that requires less hardware resources for testing.
[2] << IP module data >> Attention is paid to the IP module data of the CPU. The design data such as the IP module data of the CPU read by the computer is recorded on a recording medium and provided. The design data includes an instruction queue, a bus, an instruction decoder that decodes an instruction supplied via the instruction queue or the bus, and circuit data of a control unit. An operation mode in which the instruction decoder decodes a predetermined repeat instruction and instructs the control unit to repeatedly fetch the program to be repeated from the instruction queue after the program to be repeated is once stored in the instruction queue. Has the function of setting If the CPU is designed using the circuit data stored in the recording medium, the development period of the semiconductor integrated circuit that enables the test method of the built-in memory can be shortened.
Focusing on the IP module data of the CPU and the like and the test program, the design data of the CPU and the test program executable by the CPU realized by the design data are recorded on an information recording medium in a computer-readable manner and provided. . The design data includes circuit data of an instruction queue, a bus, an instruction decoder, and a control unit. The instruction decoder decodes a predetermined repeat instruction and temporarily stores a program to be repeated in the control unit in the instruction queue. A function of setting an operation mode in which the fetch of the program to be repeated after the execution can be repeated from the instruction queue. The test program is a program for a memory test stored in the instruction queue in the operation mode and causing the CPU to repeatedly execute a memory access process via a bus and a memory access address update process.
According to this computer-readable information recording medium, the design data as IP module data facilitates the design and development of a semiconductor integrated circuit using a CPU. In such a memory test for an on-chip memory of a semiconductor integrated circuit, an on-chip CPU may execute the test program. The on-chip CPU supports the repeat function of the instruction queue as a memory test function, and eliminates branch instructions from the test program. Therefore, a memory test program optimized for CPU hardware is developed from the beginning. You don't have to. Therefore, a user who develops a semiconductor integrated circuit using data of an IP module such as a CPU can efficiently design a circuit of the CPU and test design for an on-chip memory, and can develop a semiconductor integrated circuit more efficiently.
Since the test program for the memory test is executed by the on-chip CPU, it can be described in an assembly language or the like used for program development of the CPU, and can be easily changed according to the use of the semiconductor integrated circuit or a failure event. . Therefore, when providing the IP module data of the CPU, the user of the IP module data can easily cope with various memory tests only by providing a sample program as a test program for a memory test.
[3] << LSI >> Attention is focused on a semiconductor integrated circuit to which the above-described on-chip memory test method can be applied. The semiconductor integrated circuit has a CPU, a memory, and a bus connecting the CPU and the memory on a semiconductor chip. The CPU includes an instruction queue, an instruction decoder for decoding instructions supplied via the instruction queue or the bus, and a control unit. The instruction decoder controls the operation mode in which a predetermined repeat instruction is decoded, so that a program to be repeated can be repeatedly fetched from the instruction queue after the program to be repeated is once stored in the instruction queue. Can be set in the section.
According to the semiconductor integrated circuit, the on-chip CPU supports a repeat operation of the instruction queue as a memory test function, and can eliminate a branch instruction from a test program.
In the operation mode, the CPU executes the program to input data read from the memory and provide a determination circuit for comparing a logical value of the input data with an expected value, and determining a determination result by a semiconductor. You may comprise so that output is possible outside a chip | tip. It is also possible to remove the comparison instruction for the comparison judgment from the test program executed by the CPU, and it is possible to further improve the memory test efficiency.
At this time, by providing a dedicated bus separate from the bus as a path for supplying read data from the memory to the determination circuit, it is possible to avoid a situation in which read data and write data compete on the bus, and to improve the memory test efficiency. Can be further improved.
From the viewpoint of further improving the test efficiency, when the memory has a plurality of memory blocks, each memory block is preferably mapped to the same address and enabled to operate in parallel in response to the setting of the operation mode. At this time, the determination circuit only needs to be able to compare and determine the memory read data output in parallel from the plurality of memory blocks in parallel with the expected value. As a result, a parallel test can be performed, and the efficiency of the memory test can be further improved.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a system LSI such as a microcomputer which is an example of a semiconductor integrated circuit according to the present invention. In a system LSI 100 shown in FIG. 1, a CPU core 101, a DMA (Direct Memory Access Controller) controller 119, a bus controller 120, a peripheral module 121, and a fuse circuit 115 are formed of a single semiconductor substrate (semiconductor chip) such as monocrystalline silicon. ) Is formed by a semiconductor integrated circuit manufacturing technique such as CMOS.
The CPU core 101 includes a CPU 102, a DSP (Digital Signal Processor) 104, a cache memory 106, a general-purpose memory 107, an XY memory 108, and a BIST 110. The CPU 102 has an instruction control unit, an operation unit, and the like. The instruction control unit fetches and decodes an instruction constituting a program, and the operation unit performs operation processing, memory access processing, and the like according to the result of the decoding, and executes the instruction. I do. The DSP 104 is an arithmetic unit such as a coprocessor specialized for speeding up digital signal processing. The DSP 104 uses an XY memory 108 connected by an XY bus 109 for various digital signal processing operations such as a product-sum operation. The cache memory 106 temporarily stores relatively frequently used programs and data among the programs and data stored in the ROM 131 and the RAM 132 outside the chip. The general-purpose memory 107 is used as a work area of the CPU 102 or a temporary storage area of data. The BIST module 110 is a test circuit used for testing an on-chip memory and the like.
The CPU 102, DSP 104, cache memory 106, general-purpose memory 107, XY memory 108, and BIST module 110 are connected by a high-speed CPU bus 105. The cache memory 106, the general-purpose memory 107, the XY memory 108, and the BIST module 110 are also connected to a system bus 118 for connecting to the outside of the CPU core 101. The cache memory 106 is configured to operate as a bridge circuit between the CPU bus 105 and the system bus 118 during non-cache access. That is, when the memory access target of the CPU 102 is a non-target area of the cache by the cache memory 106, the cache memory 106 functions as a bridge circuit that can connect the bus 105 and the bus 118. The general-purpose memory 107 and the XY memory 108 are internally divided into four pages (four memory blocks).
The CPU 102 has an instruction queue 103 built therein. Instructions are prefetched into the instruction queue 103 using the empty timing of the buses 105 and 118. Particularly, in the present invention, the instruction queue 103 is operated as a repeat queue or a loop queue in which a test program is stored when the general-purpose memory 107 and the XY memory 108 are tested, and the stored test program can be repeatedly used. In short, it is not necessary to fetch the repeatedly executed test program from the bus 105 through the cache memory 106 every time. Therefore, it is possible to suppress or reduce the occurrence of a state in which the memory read / write data of the memory test competes with the test program on the bus 105, and realize an efficient memory test. The details of the instruction queue 103 will be described later.
The BIST module 110 outputs a bistable enable signal (BISTEN) 140 indicating whether or not the memory test mode is set, to the general-purpose memory 107 and the XY memory 108. Read data read from the general-purpose memory 107 in the memory test operation is supplied to the BIST module 110 via the dedicated data bus 141, and read data read from the XY memory 108 in the memory test operation is supplied to the BIST module 110 via the dedicated data bus 142. Is done. The BIST module 110 compares the read data from the buses 141 and 142 with the expected value data, and outputs a test result signal 111 from the external terminal 112 to the outside of the chip. Thus, the read data and the write data of the memory test do not compete with each other on the bus 105. In this regard, the memory test can be made more efficient.
In addition, the BIST module 110 provides the general-purpose memory 107 with address information to be rescued (rescue address information) for relieving the memory by replacing the defective portion with a redundant memory area when a part of the memory is defective. The rescue information is output to the general-purpose memory 107 via the signal 113. Further, a fuse circuit 115 for nonvolatilely storing the rescue information obtained by the memory test is provided. The rescue information is input / output via a data signal 114 between the fuse circuit 115 and the BIST module 110. The fuse circuit 115 is controlled to write the relief information from the BIST module 110 in accordance with a fuse circuit control signal 116 input via an external terminal 117 for controlling the fuse circuit.
The DMAC 119 controls data transfer between memories and between the memory and the input / output circuit in accordance with the initial settings of the CPU. The bus controller 120 performs interface control relating to the bus width and transfer speed of information transmission via the external bus 130. The peripheral module 121 has peripheral functions such as a timer and a serial interface. The external bus 130 includes, but is not limited to, a mask ROM (Read Only Memory), an EPROM (Erasable and Programmable Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory, a DRAM, etc.) RAM 132, an ASIC module 133 and the like.
In the normal operation mode of the system LSI 100, when the CPU 102 accesses the general-purpose memory 107 or the XY memory 108 via the CPU bus 105, only one page in each of the memories 107 and 108 specified by the address is to be accessed. In the case of read access, read data is read into the CPU 102 via the CPU bus 105, and in the case of write access, write data on the CPU bus 105 is written to the memory cell of the page to be accessed.
When a test program for a memory test is executed, writing is performed on a specific register in the BIST module 110, and a memory test mode (BISTEN is "1") is set. In the memory test mode, when there is a read access by the CPU 102, the read data from the general-purpose memory 107 and the XY memory 108 are not output to the CPU bus 105 but are supplied to the BIST module 110 via the dedicated buses 141 and 142. . In this memory test mode, each page of the general-purpose memory 107 and the XY memory 108 is read in parallel, and 32 bits × 4 (number of pages) × 2 (number of memories) = 256 bits are output to the BIST module 110. Is done. At the time of writing, the same data is simultaneously written to each page. The BIST module 110 compares read data sent from each page of the memories 107 and 108 with expected value data written in a register in the module in advance. Notifies that a mismatch has occurred. The memory address relating to the mismatch is held in the BIST module 110 as rescue information. This rescue information is stored in the fuse circuit 115 composed of a nonvolatile storage element so as not to be lost even when the power is turned off.
Here, a method of the 13N test which is one of the test sequences of the on-chip memory will be described in advance with reference to FIG. This test is divided into five phases L0 to L4, and a certain pattern 0 (all bits 0 and checker pattern) and its inverted pattern 1 (all bits 1 and inverted checker pattern) are read / written. It has become. In the L0 phase (850), pattern 0 is written to the entire memory area in ascending address order. In the L1 phase (851), processing of reading pattern 0, writing pattern 1, and reading pattern 0 written in the L1 phase is executed for each address in ascending order. In the L2 phase (852), processing of reading pattern 1 written in the L1 phase, writing pattern 0, and reading pattern 0 is executed for each address in ascending order. The L3 phase (853) and the L4 phase (854) are obtained by changing the address order of the L1 and L2 phases in descending order. As will be described in detail later, the test program executed by the CPU 102 is a program for performing the 13N test.
In FIG. 16, R0 means pattern 0 read, W0 means pattern 0 write, R1 means pattern 1 read, and W1 means pattern 1 write.
FIG. 2 illustrates in detail connection states of circuit blocks related to a memory test. At the time of the memory test, the CPU 102 repeatedly executes the test program using the repeat function. At that time, the CPU 102 issues an instruction fetch to the CPU bus 105 only in the first loop of the repeated execution of the test program (repeat loop). The instruction fetch is issued to the cache memory 106, and is read from the cache memory 106 when a cache hit occurs, or from outside the chip via the system bus 118 and the bus controller 120 when a cache miss or cache is not used. become. In the second and subsequent loops, instructions are read from the instruction queue 103 in the CPU 102, and no instruction fetch is issued to the CPU bus 105. In short, once the test program is stored in the instruction queue 103, the fetch of the test program is repeatedly performed from the instruction queue 103 instead of the bus 105.
When the CPU 102 executing the test program executes write access to the memory to be tested, a bus command bus (CPU bus command bus) 201, an address bus (CPU address bus) 203, and a data bus (CPU data bus) 203 of the CPU bus 105. Required value is output. When the control signal BISTEN 140 output from the BIST module 110 is “L”, writing is performed only on the only page specified by the address, but when BISTEN is “H”, writing is performed in parallel on all pages. Is done. When the CPU 102 executes the read access, necessary values are output to the bus command bus 201 and the address bus 202 of the CPU bus 105. When the control signal BISTEN is "L", only the page specified by the address outputs data to the CPU data bus 203, but when the control signal BISTEN is "H", all pages are read in parallel. , The general-purpose memory 107 and the XY memory 108 output read data to dedicated data buses 141 and 142 connected to the BIST module 110. The dedicated data buses 141 and 142 are provided here in 32 bits × 8, that is, for 256 bits according to the number of pages (8 pages). At this time, no read data is supplied to the CPU data bus 203. The BIST module 110 decodes the values of the CPU bus command bus 201 and the CPU address bus 202, and if the control signal BISTEN is “H” and is a read cycle, is output to the dedicated data bus 141 or 142 from each of the memories 107 and 108. The data is compared with an expected value set in a register in the BIST module 110 in advance, and when a mismatch occurs, a signal (FAIL) 204 is asserted and output to the outside of the chip via an external terminal (FAIL) 205. Notify mismatch. In addition, the occurrence of the mismatch is recorded in the status register in the BIST module 110, and the operation is performed so that the occurrence of the mismatch can be read out from the CPU 102 to be known later. If a mismatch occurs, it is determined whether the bit can be rescued. If the bit cannot be rescued, a rescue impossible signal 206 is output from the rescue impossible terminal 207 to the outside of the chip, and the fact is notified to the outside. The BIST module 110 can also store the address where the mismatch has occurred in an internal register. When the repair bit (redundant bit) of the general-purpose memory 107 is used, the BIST module 110 outputs the fuse data 114 to the fuse circuit 115 so that the address of the bit to be repaired can be written in the fuse circuit 115. Further, the BIST module 110 can output a rescue information signal 113 indicating an address to be rescued to the general-purpose memory 107 based on the data read from the fuse circuit 115 or the value of an internal register. . The operation of writing data to the fuse circuit 115 is performed by writing data from the BIST module 110 according to an instruction from a fuse control terminal 117 of the chip (generally from a tester at the time of a test before shipment). The fuse circuit 115 is a nonvolatile memory, and in this embodiment, is configured by a small-capacity flash memory.
FIG. 3 illustrates details of the BIST module 110. The BIST module 110 includes a comparator 251, an address decoder 252, a register unit 253, a rescue determination unit 254, and a fuse control unit 255. Here, eight 32-bit comparators 251 are provided to perform a simultaneous parallel test on a total of eight pages, four pages each of the general-purpose memory 107 and the XY memory 108.
The comparator 251 notifies the address decoder 252, the rescue judging unit 254, and the register unit 253 of an 8-bit comparison result signal 263 indicating whether or not there is a mismatch in the comparison result of each of the eight pages. The address decoder 252 decodes the values of the CPU bus command bus 201 and the CPU address bus 202, and determines whether or not it is a read cycle. In the case of a read cycle, a comparison enable signal 256 is asserted for each comparator 251 to activate the comparator 251. The expected value used by the comparator 251 can be selected from two types depending on the address, and an expected value selection signal 257 is notified to the comparator 251. This is to make it possible to dynamically switch between pattern 0 and pattern 1 in a 13N test, for example. When the comparison result from the comparator 251 does not match, the address decoder 252 outputs the corresponding error address 258 to the rescue judging section 254 and the register section 253. The rescue judging section 254 judges whether or not rescue is possible based on the error address, and outputs a rescue impossible signal 206 from the rescue impossible terminal 207. If a mismatch occurs in the comparator 251, a FAIL signal 204 is output from the FAIL terminal 205. Assertions of the FAIL signal 204 and the rescue-impossible signal 206 can be masked according to the settings in the register section 253. Further, the rescue judging section 254 generates rescue data to be written in the fuse circuit 115 based on the error address information, and outputs this to the register section 253 as a rescue data signal 264. The fuse control unit 255 inputs and outputs a fuse data signal 114 to and from the fuse circuit 115 and outputs a rescue information signal 113 as rescue data to the general-purpose memory 107. Although details of the register section 253 will be described later, two kinds of expected value signals 260 and 261 and an MS signal 262 for designating ON / OFF of the comparator for each memory page are output to the comparator 251. . Further, it outputs a signal 265 for masking the assertion of the FAIL terminal 205 and the non-repairable terminal 207 to the rescue determination unit 254 based on the register setting. Further, an address limit signal 266 for determining the upper limit of each address of the general-purpose memory 107 and the XY memory 108 based on the setting of the register unit 253 is output to the address decoder 252. Further, the register unit 253 can input and output the FD signal 267 as relief data to the fuse control unit 255.
FIG. 4 shows a plurality of registers held by the register unit 253. The register unit 253 has registers denoted by 301 to 307, and each of them can be accessed via the CPU bus 105, the cache memory 106, and the system bus 118 by non-cache access of the CPU 102.
The expected value registers (BISTDR0 and BISTDR1) 301 hold two types of expected values for comparison. An address register (BISTFAR0, BISTFAR1, BISTFAR2, BISTFAR3) 302 stores an error address at which a mismatch has occurred. A fuse data register (BISTDR) 303 stores data for writing relief address information generated from an error address to a fuse circuit. The status register (BISTSR) 304 records that there is a mismatch for each page. A module select register (BISTMS) 305 holds control information for controlling whether to test for each page. The control register (BISTCR1) 306 holds control information for controlling the ON / OFF of the memory test mode, the fail stop mode, and the rescue information. The address limit control register (BISTCR2) 307 holds control information that determines the test range of each page when simultaneously testing memories of different sizes.
The expected value registers (BISTDR0, BISTDR1) 301 are 32-bit registers each holding an expected value for comparison. If bit 18 of the CPU address bus 202 is "0", one of the registers (BISTDR0, BISTDR1) 301 If BISTDR0) is "1", the other register (BISTDR1) is used. These are used for switching between pattern 0 and pattern 1 in the 13N test. Each of the address registers (BISTFAR0, BISTFAR1, BISTFAR2) 302 is a 32-bit register. The general-purpose memory can be rescued for each page, and it is necessary to hold up to four error addresses. The fuse data register (BISTDR) 303 is a 32-bit register for holding data to be written to the fuse circuit 115. The data is automatically generated by the rescue judging unit 254 based on the error address and written into the register. The status register (BISTSR) 304 is an 8-bit register, and its initial value is all bits “0”. However, when a mismatch occurs by a test, “1” is written to a bit corresponding to each page. S13 to S10 correspond to each page of the XY memory 108, and S03 to S00 correspond to each page of the general-purpose memory 107.
A module select register (BISTMS) 305 is an 8-bit register that controls whether a test is performed for each page. When each bit is "1", test is on, and when each bit is "0", test is off. However, even if the test is set to OFF, the read / write of the memory itself is not stopped, and the comparator 251 operates so as not to perform the comparison. M13 to M10 correspond to each page of the XY memory 108, and M03 to M00 correspond to each page of the general-purpose memory 107.
The control register (BISTCR1) 306 is an 8-bit register and has an enable bit EN for turning on / off the entire memory test function. Writing "1" in this bit enables the memory test function. The BISTEN signal 140 becomes “H”, and the operation of each memory switches to the memory test mode. The C0 bit controls the mask of the FAIL signal 204, and when set to "1", the FAIL signal 204 is not asserted even if a mismatch occurs. Similarly, the C1 bit controls the mask of the non-recoverable signal 206. When the bit is set to "1", the non-recoverable signal is not asserted even if an unrecoverable error occurs. The C2 bit controls whether the rescue information for the general-purpose memory is generated from the data from the fuse circuit 115 or from the data in the fuse data register (BISTD DR) 303. Then, the fuse data register (BISTFDR) 303 is selected. The initial value is “0”.
The control register (BISTCR2) 307 is an 8-bit register and specifies the size of one page of the XY memory 108 and the general-purpose memory 108. SZ12 to SZ10 correspond to the XY memory 107, and SZ02 to SZ00 correspond to the general-purpose memory 107. Each set value and storage capacity is a combination of 000: 4k, 001: 8k, 010: 16k, 011: 32k, 100: 64k, 101: 128k, 110: 256k, and 111: 512k bytes.
FIG. 5 illustrates the configuration of one page of the XY memory 108 as a representative of the general-purpose memory 107 and the XY memory 108 to be subjected to the memory test.
In the example of FIG. 5, the size of one page is 4 kbytes, has a memory mat 357 of 4 kbytes, and a memory cell in units of 32 bits for the memory mat 357 is selected by the address decoder 360.
The XY memory 108 is connected to three buses, a CPU bus 105, an XY bus 109, and a system bus 118. The arbitration circuit 351 includes a bus command bus 201 of the CPU bus, an address bus 202 of the CPU bus, and a bus command bus of the XY bus. 211, an XY bus address bus 212, a system bus bus command bus 221, and a system bus address bus 222 are decoded to determine which bus is to be accessed. The priority order is system bus> XY bus> CPU bus, but the test program is configured to access only from CPU bus 105 during a memory test. The address is selected by the address selector 353 according to the address selection signal 352 from the arbitration circuit 351. The upper plurality of bits of the address signal selected by the address selector 353 are supplied to the enable control circuit 356 and used for selecting a memory mat, and the remaining lower address bits are supplied to the address decoder 360 and used for selecting a memory cell. You.
At the time of write access, write data to the memory mat 357 is selected by the write data selector 355 in accordance with the data selection signal 354. The output buffers 203B, 213B, and 223B select which data bus to output the value of the read data from the memory mat 357 at the time of reading.
The enable control circuit 356 decodes the command, address, and control signal (BISTEN) 140 selected by the arbitration circuit 351 to determine whether to activate the memory mat 357, the write control circuit 358, and the sense amplifier 359. . That is, when BISTEN 140 is "L", the upper address bits are decoded so that each page responds to a different address. However, when BISTEN 140 is "H", all pages respond to the same address. Decode as you would.
Although not shown, the configuration of one page of the general-purpose memory 107 is the same as that of FIG. 5 except that the XY bus 109 is not connected and the memory size is different, so that the detailed description is omitted. .
FIG. 6 illustrates an address map of the general-purpose memory 107. This figure shows an example in which the general-purpose memory 107 has 32 pages of 32 kbytes per page and has a total of 128 kbytes. Although not particularly limited, a 4-Mbyte space is allocated to the general-purpose memory in consideration of expandability, and the present embodiment has a configuration in which an actual memory exists in 128 Kbytes. In the case of this configuration, the address map when BISTEN 140 is "L (= 0)" is as shown in FIG. The four pages are allocated to “U0L: 0xA55F0000 to 0xA55F7FFF”, “U0H: 0xA55F8000 to 0xA55FFFFF”, “U1L: 0xA5600000 to 0xA5607FFF”, and “U1H: 0xA5608000 to 0xA5608FFF”. The symbol 0x means that the subsequent value is a hexadecimal number. The shaded area 401 in FIG. 6A becomes a shadow, and the enable signals UPAGE0LEN, UPAGE0HEN, UPAGE1LEN and UPAGE1HEN of each page have values as shown on the right side of FIG. 6A. On the other hand, when BISTEN 140 is “H (= 1)”, the address map is as shown in FIG. In this case, all pages are allocated to 32 kbytes of 0xA50000000 to 0xA5007FFF, and the enable signal of each page is also asserted at the same address. In this case, access to the area 402 indicated by "x" in FIG. 6B is invalid because no page responds.
FIG. 7 illustrates a configuration of the enable control circuit 356 for realizing the address map of FIG. FIG. 7 shows the logic of four pages collectively. When the command 452 is read or write and the BISTEN 140 is “L”, the upper 31 bits to 20 bits (A31 to A20) of the address are 0xA540 to 0xA57F, and when the BISTEN140 is “H”, the upper address decoder 451 is 0xA500. In the case of ０0xA53F, it operates to assert the enable signal (UMEMENT) 453. The enable signals (UPAGE0LEN, UPAGE0HEN, UPAGE1LEN, UPAGE1HEN) 470 to 473 of each page are used to decode the UMEMEN 453, the BISTEN 140, the address bits A21 and A15, and the decode circuits (U0LDEC) 460, (U0HDEC) 461, (U1LDEC) 462, and (U1LDEC1) 462, and (U1LDEC) 462, U1 ) 463 to be generated. The address bit A21 is an address bit that determines 0xA5400000 to 0xA55FFFFF or 0xA5600000 to 0xA57FFFFF. The address bit A15 determines whether the upper half or lower half of the area of 0xA5400000 to 0xA55FFFFF and the upper half of the area of 0xA5600000 to 0xA57FFFFF. Or the lower half. When BISTEN 140 is "L", ENOR (exclusive negative OR gate) 480 functions as an inverter, and enable signals (UPAGE0LEN) 470, (UPAGE0HEN) 471, (UPAGE1LEN) 472, and (UPPAGE1HEN) 473 of each page are exclusively used. Asserted. On the other hand, when BISTEN 140 is "H", ENOR 480 functions as a buffer, and asserts enable signals 470 to 473 of each page in parallel only when both bits A21 and A15 of the address are "0" and UMENN is "1". When the address has any other condition, the operation is performed such that all the enable signals 470 to 473 are negated irrespective of UMEN.
FIG. 8 illustrates an address map of the XY memory 108. This figure shows an example in which the XY memory 108 has 4 pages of 4 kbytes per page and a total of 16 kbytes. In consideration of expandability, the XY memory 108 is allocated a 128 kbyte space from 0xA50000000 to 0xA501FFFF, and the present embodiment has a configuration in which an actual memory exists in 16 kbytes. Although not shown, the space of 0xA5002000 to 0xA50FFFFF is treated as a shadow of the space of 0xA50000000 to 0xA501FFFF. In the case of this configuration, the address map when BISTEN 140 is "L" is as shown in FIG. The four pages are respectively assigned to “X0: 0xA5000000-0xA5007FFF”, “X1: 0xA5008000-0xA5008FFF”, “Y0: 0xA5017000-0xA5017FFF”, and “Y1: 0xA5018000-0xA5018FFF”. In this case, the shaded area 501 in FIG. 8 becomes a shadow, and the enable signals (XPAGE0EN, XPAGE1EN, YPAGE0EN, YPAGE1EN) of each page have values as shown on the right side of FIG. 8 (a). On the other hand, when BISTEN 140 is "H", the address map is as shown in FIG. In this case, all pages are allocated to “0xA50000000 to 0xA5000FFF”, and the enable signals (XPAGE0EN, XPAGE1EN, YPAGE0EN, YPAGE1EN) of each page are also asserted at the same address. Access to the area 502 indicated by “x” in FIG. 8B is invalid because no page responds. The difference from the general-purpose memory 107 shown in FIG. 6 is that when the BISTEN 140 is “H”, the shadow area 501 is eliminated. This is because, in the present embodiment, the memory size is smaller than the general-purpose memory 107. Therefore, if the shadow is left during the simultaneous test, for example, in the L1 phase of the 13N test, the XY memory 107 is executed during the L1 phase of the general-purpose memory. Is performed a plurality of times in the L1 phase, thereby breaking the state expected at the start of the next L2 phase.
FIG. 9 illustrates the configuration of the enable control circuit 356 for realizing the address map. The upper address decoder 551 operates to assert the XMEMENB 553 when the command 552 is read or write and the upper bits 31 to 20 of the address are 0xA50. The AMASK circuit 554 decodes the bits A14, A13, and A12 of the address, the XMEMENB 553, and the BISTEN 140 to generate the XMEMEN 555. When BISTEN is “0”, XMEMEN = XMEMENB regardless of the bits A14, A13, and A12 of the address. However, when BISTEN140 is “1”, when bits A14, A13, and A12 of the address are “000”. Only in this case, XMEMEN = XMEMENB, and otherwise, XMEMEN is "0". The enable signal for each page is generated by decoding the XMEM 555, the BISTEN 140, and the address bits A16 and A15 by the decode circuits (X0DEC) 560, (X1DEC) 561, (Y0DEC) 562, and (Y1DEC) 563. When BISTEN 140 is “L”, ENOR 580 operates as an inverter, and enable signals (XPAGE0EN) 570, (XPAGE1EN) 571, (YPAGE0EN) 572, and (YPAGE1EN) 573 of each page are exclusively asserted. On the other hand, when BISTEN 140 is "H", ENOR 580 works as a buffer, and only when address bits A16 and A15 are both "0" and XYMEM 555 is "1", enable signals 570-573 for each page are asserted at the same time, and the address is asserted. In other conditions, the operation is performed such that all the enable signals 570 to 573 are negated regardless of the XYMEMEN 555.
FIG. 10 illustrates the details of the CPU 102 mainly on the configuration of the instruction fetch. An arithmetic unit 610 includes a general-purpose register, an arithmetic and logic unit, an address register, a data buffer register, a temporary register, a control register, and the like connected to an internal bus (not shown). CPU address bus 202 is connected to an address register, and CPU data bus 203 is connected to a data buffer register.
The instruction queue 103 has, for example, an instruction buffer 103BF having a buffer area of 12 stages, and a read pointer 103RP and a write pointer 103WP for causing the instruction buffer 103BF to perform a FIFO operation. The read pointer 103RP is a loop counter for specifying a buffer area for performing a read operation, and the count value CNTR is set to # 0 to # 11. The write pointer 103WP is a loop counter for designating a buffer area for performing a write operation, and the count value CNTW is set to # 0 to # 11. As for the read pointer 103RP and the write pointer 103WP, the write pointer 103WP is incremented each time a write operation is performed, and the read pointer 103RP is incremented each time a read operation is performed, based on the initial values. The state in which the count value CNTR of the read pointer 103RP has caught up with the count value CNTW of the write pointer 103WP is a state in which significant storage information is not held in all of the 12-stage buffer areas, in other words, the state is temporarily stored in the buffer area. The stored information indicates an empty (empty) state in which all the reading has been completed. The state in which the count value CNTW of the write pointer 103WP has caught up with the count value CNTR of the read pointer 103RP is a state in which significant storage information is held in all of the 12-stage buffer areas, in other words, all the buffer areas are still in the state. This means a full state in which the storage information is not read.
The instruction buffer 103B fetches an instruction from the CPU data bus 203. The instruction read from the buffer 103B or the instruction on the CPU data bus 203 is selected by the selector 603 and supplied to the instruction register (IR) 601. The instruction latched in the IR 601 is decoded by the instruction decoder 602, and the arithmetic operation by the arithmetic unit 610 is controlled in accordance with the decoded result, and the instruction control unit 607 is controlled.
The instruction control unit 607 causes the selector 603 to select an instruction fetch path to the IR 601 by the selection signal SEL, and generates an increment signal INCR for the read pointer 103RP and an increment signal INCW for the write pointer 103WP. The instruction control unit 607 controls generation of a memory access cycle via the operation unit 610 for instruction fetch or instruction prefetch, and controls operation of writing (push) and reading (pull) of an instruction in the instruction queue 103. Further, control for operating the instruction queue 103 as a repeat queue or a loop queue is performed.
The instruction prefetch control function of the instruction control unit 607 will be described. The instruction control unit 607 receives the count value CNTR of the read pointer 103RP and the count value CNTW of the write pointer 103WP, and detects the full empty state of the instruction buffer 103. If the instruction buffer 103B is not in a full state, the instruction control unit 607 uses a vacant timing of the data bus 203 to prefetch an instruction from the cache memory 106 or the external ROM 131 or RAM 132 to the instruction buffer 103B. Is generated by the calculation unit 610. The instruction address at this time is generated using a program counter or the like. The instruction supplied to the data bus 203 in this memory cycle is held in the instruction buffer 103B, and the value of the write pointer 103WP is incremented by the increment signal INCW.
The instruction fetch control function of the instruction control unit 607 will be described. If the instruction buffer 103B is not empty at the timing of fetching the instruction to the IR 601, the instruction read from the instruction buffer 103B is latched by the IR 601 via the selector 603. After reading from the instruction buffer 103B, the read pointer 103RP is incremented. If the instruction buffer 103B is empty at the timing of fetching the instruction to the IR 601, the arithmetic unit 610 generates a memory cycle for fetching the instruction from the cache memory 106 or the external ROM 131 or the RAM 132, and in this memory cycle, The instruction obtained on the bus 203 is latched by the IR 601 via the selector 603.
The repeat queue control function of the instruction control unit 607 will be described. The instruction set of the CPU 102 includes a repeat instruction. This repeat instruction specifies the first instruction address, the last instruction address, and the number of repetitions to be repeatedly executed. When the instruction decoder 602 decodes the repeat instruction, it controls the instruction address generation by the arithmetic unit 610 and the instruction fetch to the instruction control unit 607 so that the instruction from the first instruction address to the last instruction address is repeatedly executed a designated number of times. Thus, a repeat loop is formed. At this time, the instruction decoder 602 gives the instruction control unit 607 an instruction to operate the instruction queue 103 as a repeat queue. That is, the instruction decoder 602 sets the repeat queue mode flag 607F in the instruction control unit 607 by decoding the repeat instruction, and sets the number of repeat loops and the number of instructions to be executed in each repeat loop in the register 607R. After this operation is performed, the instruction control unit 607 resets the values of the read pointer 103RP and the write pointer 103WP to the initial values before shifting to the execution of the first instruction specified by the repeat instruction, and in the first repeat loop, The instruction is fetched from the cache memory 106 or the external ROM 131 or RAM 132 to the IR 603, and the fetched instruction is executed. In parallel with this, an operation of sequentially accumulating instructions of the first repeat loop in the instruction queue 103 is performed. From the second repeat loop, the instructions stored in the instruction buffer 103B are sequentially read and executed. At this time, every time the count value of the read pointer 103RP reaches the set value (the number of instructions) of the register 607R, the instruction control unit 607 returns the count value CNTR to the initial value by the reset signal RES, and performs the ring counter operation. When the number of times of execution of the repeat loop ends the set value of the register 607R (the number of times of repeat loop), the repeat queue mode flag 607F is reset, whereby the instruction control unit 607 ends the control of the repeat queue operation for the instruction queue 103. I do.
As described above, when the repeat loop is used, the instruction control unit 607 determines the length of the repeat loop, and when the length is within the instruction queue (12 instructions or less in this example), the instruction queue 103 Control is performed such that the instruction once stored and read is not immediately discharged, but is reserved for the second and subsequent repeat loops. As a result, an instruction fetch is required only for the first time in the repeat loop, but no instruction fetch is required for the second and subsequent times in the repeat loop, so that the CPU bus 105 can be used efficiently. . In addition, since the process of returning to the beginning in the repeat loop does not require a branch instruction, the program itself constituting the loop is shortened. By using such a repeat instruction in a test program for a memory test, the speed of the memory test can be increased.
FIG. 11 exemplifies a test flow in the case where the relief for the general-purpose memory 107 is not performed. First, in step 651, initialization of the BIST module 110 is performed. More specifically, the C2 bit of the control register BISTCR1 is set to “0”, and the rescue information signal 113 is generated from BISTRDR (303). In addition, all bits “0”, which is a setting of “do not use the relief bit”, are written in BISTRDR. With the above setting, the relief bit is not used. In addition, the C0 bit of BISTCR1 is set to "0", and when a mismatch occurs, the FAIL terminal 205 is asserted. Further, expected values for pattern 0 and pattern 1 are set in BISTDR0 and BISTDR1 (301). Next, in step 652, "1" is written to the EN bit of BISTCR1, and the mode shifts to the memory test mode. As a result, BISTEN 140 becomes "1".
Next, in step 653, the CPU 102 is caused to execute a repeat instruction for a memory test, and to perform a memory access for a memory test, update of an access address, and the like according to a repeat loop test program. Next, in step 645, the data read from the memory is compared with the expected value written in the register. This comparison is performed for each page in the BIST module 110 in parallel. Next, the comparison result is determined in step 655, and if a mismatch has occurred in any one of the pages, the FAIL terminal, which is an external terminal, is asserted in step 656, the test is terminated as a defective product. .
If no mismatch has occurred in the comparison result, the loop counter is decremented in step 657. Next, in step 658, it is determined whether or not the loop counter has become 0. If not, the process returns to step 653. This operation is repeated until the loop counter becomes 0, and if no inconsistency occurs during that time, it is determined to be PASS. All of the processes of steps 654 to 658 are performed by hardware. When the entire test is configured for each of a plurality of phases, such as the 13N test, the above-described series of operations is repeated by the number of phases, and the one determined as PASS at the stage when the final phase ends is a non-defective product.
In FIG. 11, steps 656 and 657 are processing by hardware, and the other steps are processing by software.
FIG. 12 exemplifies a test flow in a case where the relief is performed on the general-purpose memory 107. First, in step 701, the BIST module 110 is initialized. Specifically, the C2 bit of the control register BISTCR1 (306) is set to "0", and the rescue information signal 113 is generated from BISTRDR (303). In addition, ALL0 which is a setting of “do not use the relief bit” is written in BISTRDR. With the above setting, the relief bit is not used. Also, the C0 bit of BISTCR1 is set to "1" so that the FAIL terminal 205 is not asserted even when a mismatch occurs. Further, expected values for pattern 0 and pattern 1 are set in BISTDR0 and BISTDR1 (301). Next, in step 702, "1" is written to the EN bit of BISTCR1, and the mode shifts to the memory test mode. As a result, BISTEN 140 becomes "1".
Next, in step 703, the CPU 102 is caused to execute a repeat instruction for a memory test, and to perform a memory access and an access address update for the memory test according to a repeat loop test program. In step 704, the data read from the memory is compared with the expected value written in the register. This comparison is performed for each page in the BIST module 110 in parallel. Next, in step 705, the comparison result is determined. If a mismatch has occurred in any one of the pages, it is determined in step 706 whether the mismatched address can be repaired. Here, it is assumed that up to one address can be relieved for each page of the general-purpose memory 106. Therefore, when a mismatch occurs at a plurality of locations in the same page or when a mismatch occurs in the XY memory 108 having no repair bit, it is determined that the repair is impossible. When it is determined that rescue is possible, information for generating the rescue information signal 113 is written to BISTRD. If it is determined that the repair is impossible, the non-recoverable terminal 207 is asserted in step 707, and the test is terminated as a defective product. If no inconsistency has occurred in the comparison result, or if it is determined that inconsistency has occurred but rescue is possible, the loop counter is decremented in step 708. Next, in step 709, it is determined whether or not the loop counter has become 0. If not, the process returns to step 703. This operation is repeated until the loop counter becomes zero. All of the processes in steps 704 to 709 are performed by hardware.
When the loop counter becomes 0, the process proceeds to step 710, and if no mismatch has occurred during that time, it is determined that the loop counter is normal (PASS). If a mismatch has occurred, the process proceeds to step 711 because remedy is possible. If a mismatch that can be remedied has occurred at the stage of the above-described test, data necessary for generating the rescue information signal 113 is automatically written in the register (BISTDR) under the control of the BIST module 110. Therefore, next, a test of the repair bit is performed using the repair information. The test operation itself is the same as that described above, but in the initial setting of the BIST module in step 712, the C0 bit of BISTCR1 is set to “0”, and when a mismatch occurs, the FAIL terminal (205) is asserted. To be done. Since rescue has already been used, the occurrence of further mismatch means that the rescue bit is also defective. In this case, the FAIL terminal is asserted in step 717, and it is determined to be defective. The operations of steps 713 to 719 are the same as steps 702 to 709, respectively. If no inconsistency has occurred at the end of the test, the rescue is successful, and the data of BISTRDR is written to the fuse circuit 115 in step 720, and the test ends.
In FIG. 13, steps 704, 707, 708, 711, 715, 717, and 718 are processing by hardware, step 720 is processing by a tester, and the other steps are processing by software.
FIG. 13 shows an instruction sequence for performing a 13N test on the system LSI of FIG. 1 in an assembly language. The repeat instruction (REPEAT) is an instruction for designating a start address, an end address, and the number of loops of a repeat loop, and has a syntax of “REPEAT start address, end address, loop number designation register”. The start address and the end address can each be specified by the label of the assembly language program. As shown in FIG. 16, the 13N test consists of five phases L0 to L4, where L0 is a repeat loop of one instruction (750), and L1 to L4 are repeat loops of three instructions (751, 752). , 753, 754). The reason why two types of address pointer registers R2 and R3 are prepared for reading is to switch the expected values of pattern 0 and pattern 1 by bit A18 of the address. As shown in FIGS. 6B and 8B, in this example, when BISTEN 140 is “1”, the general-purpose memory 107 and the XY memory 108 are mapped to 0xA50000000 to 0xA5007FFF. The initial value of the pointer is set to 0xA500000. Since each page of the memory is accessed with a 32-bit width, the initial value of the loop counter is set to 0x2000.
FIG. 14 shows a timing chart of the CPU bus 105 and the BIST-dedicated data buses 141 and 142 during the execution of the phase L1 of the instruction sequence shown in FIG. R. L is a long word (32 bit) read command; L indicates a long word write command, RD0 indicates 13N test pattern 0 read data, RD1 indicates pattern 1 read data, and WD1 indicates pattern 1 write data. According to this, for example, it takes three cycles / loop to execute the phase L1 of the 13N test. Further, a parallel test can be performed on eight pages in combination with the general-purpose memory 107 and the XY memory 108.
Here, as a comparative example, a case will be described in which the CPU tests an on-chip memory when the CPU does not have a repeat loop function and does not have a dedicated circuit for comparison determination. As a program according to a comparative example for performing a 13N test, a test program for executing the L1 phase can be described, for example, as shown in FIG. R0 to R7 are registers of the CPU, R0 is a memory address, R1 is expected value data for pattern 0, R2 is write data / expected value data for pattern 1, R3 is a storage location of pattern 0 read data, and R4 is a pattern destination. One read data storage destination, R7, is a loop counter. This program is composed of 9 instructions, each of which reads pattern 0 by an instruction 901, writes pattern 1 by an instruction 902, reads pattern 1 and increments an address by an instruction 903, and determines coincidence of pattern 0 data by an instruction 904. Branch for performing error processing when pattern 0 does not match in instruction 905, match determination of pattern 1 data with instruction 906, branch for performing error processing when pattern 1 does not match with instruction 907, instruction 908 Decrementing the loop counter and determining loop end, and branching to the beginning of the loop when the loop has not been completed by instruction 909, respectively.
FIG. 18 shows a timing chart of a bus connecting the CPU and the built-in memory when the test program according to the comparative example is arranged in the cache memory and a test of the built-in memory that can be accessed for one cycle is executed. This shows the fourth loop when the memory to be tested is allocated from 0xA500000. One cycle requires 11 cycles. Of these, only the read command 951 of pattern 0, the write command 952 of pattern 1, and the read command 953 of pattern 1 actually test the memory. Only three cycles are spent. The remaining eight cycles are an instruction fetch cycle 954 of the program itself and a cycle 955 by the comparison instruction. Further, since the data that can be received and compared by the CPU is one data per cycle, a simultaneous parallel test cannot be performed even when a plurality of memories to be tested exist, and it is necessary to test sequentially.
In FIG. 18, JIF is a branch instruction fetch, NIF is a normal instruction fetch, and R.I. L is longword read, W.L. L indicates long word write, NOP indicates non-operation, RD0 indicates read data 0, RD1 indicates read data 1, and WD1 indicates write data 1.
Comparing the case of the present invention in FIGS. 13 and 14 with the case of the comparative example in FIGS. 16 and 17, the latter requires 11 cycles / loop to execute the phase L1 of the 13N test. In the case of the present invention, there are three cycles / loop. Further, in the case of the comparative example, only one memory page can be tested at the same time. On the other hand, according to the present invention, a simultaneous parallel test of eight pages can be performed, and the memory test can be further speeded up. it can. That is, focusing on the L1 phase of the 13N test, in the comparative example, the test of the general-purpose memory requires “11 cycles × 8 k loops × 4 pages = 352 k” steps, and the test of the XY memory requires “11 cycles × 1 k loop × 4 steps”. Pages = 44k "steps are required, for a total of 396k steps. On the other hand, in the present invention, all the memories need only be performed in "3 cycles × 8 k loops = 24 k" steps, and it can be seen that the speed is increased by 396/24 = 16.5 times.
FIG. 15 shows another example of the semiconductor integrated circuit according to the present invention. In the example of FIG. 1, the cache memory 106 is not set as a test target, but in the example of FIG. 15, the cache memory 106 is also set as a test target. Specifically, the BISTEN 140 is also output to the cache memory 106, and a BIST dedicated data bus 143 is provided from the cache memory 106 to the BIST module 110, and the BIST module 110 transmits the BIST module 110 from the general-purpose memory 107, the XY memory 108, and the cache memory 106. Can be subjected to parallel comparison determination processing. By making the bridge function of the cache bus 106 between the CPU bus 105 and the system bus 118 usable even in the memory test mode, a parallel test including the cache memory 106 can be performed. In short, in the memory test mode, the cache memory 106 is arranged in the memory space of the CPU 102 and can be read / written by specifying an address.
In the example shown in FIG. 15, the XY memory 108 and the cache memory 106 are also configured to be rescuable, and rescue information signals 144 and 145 are output from the BIST module 110 to each of them.
FIG. 19 illustrates the procedure of developing and manufacturing a semiconductor integrated circuit having a self-test function as represented in FIG. According to FIG. 19, a desired semiconductor integrated circuit is planned, its specifications are determined, and based on this, a logic design (S1), a layout design (S2), a photomask creation (S3), and a manufacture (S4). , A function test (S5), a memory test (S6), and a shipping process (S7). The development and manufacture of a semiconductor integrated circuit can be performed by one semiconductor integrated circuit manufacturer. Nowadays, there is a case where division of labor is divided between a so-called foundry which is responsible only for the manufacture of semiconductor integrated circuits and a so-called fabless which specializes exclusively in the design of semiconductor integrated circuits and has no manufacturing section. The fabless adopts a business form in which, for example, logic design and, if necessary, layout design are performed, and the subsequent processes are outsourced to a foundry, and the final product is received and shipped. For example, in FIG. 19, FB is positioned as fabless processing, and FD is positioned as foundry processing.
In the development design process such as the logic design (S1) and the layout design (S2), it is possible to use past design resources and use circuit design data distributed as IP module data today. . The IP module data is design data (also referred to as software IP module data) that specifies circuit modules such as the CPU 102 and the DSP 104 in a logical description language such as HDL (Hardware Description Language), or design data specified by mask pattern data. (Also referred to as hardware IP module data). Normally, IP module data is packaged with debugging information in addition to circuit design data.
In order to enable the means for improving the efficiency of the on-chip memory test described in FIG. 1 and the like to be easily applied to the development of other semiconductor integrated circuits, circuit design data for specifying a circuit configuration for that purpose must be stored in an IP module. What is necessary is just to be able to provide it as simple design data.
For example, focusing on the CPU, the circuit data of the CPU 102 having the loop queue function described with reference to FIG. 10 may be provided as the soft IP module data or the hard IP module data. In short, such circuit data may include respective circuit data of the instruction queue 103, the bus 105, the instruction decoder 602 for decoding the instruction supplied via the instruction queue 103 or the bus 105, and the control unit 607. The instruction decoder 602 decodes a predetermined repeat instruction and instructs the control unit 607 to repeat fetch of the program to be repeated from the instruction queue after the program to be repeated is once stored in the instruction queue 103. It is only necessary to realize a function of setting an operation mode to be performed. This function may be described by HDL or specified by a specific circuit mask pattern.
The design data of the CPU 102 may be provided together with a test program executable by the CPU 102 realized by the design data. The test program is a program for a memory test that is stored in the instruction queue 103 in an operation mode such as the loop queue mode and causes the CPU 102 to repeatedly execute a memory access process and a memory access address update process via the bus 105. I just need.
The design data and the test program may be provided by being stored in a computer-readable information recording medium (also simply referred to as a recording medium). For example, the recording medium includes a compact disk-only memory (CD-ROM), a compact disk-recordable (CD-R), a compact disk-rewritable (CR-RW), and a digital video-memory (DVD-ROM). And a computer-readable recording medium such as a DVD-RAM (Digital Video Disk-Random Access Memory) and an FD (Floppy Disk).
FIG. 20 shows an example of a system for developing a semiconductor integrated circuit. In FIG. 1, reference numerals 1, 2, and 3 denote computer devices such as an engineering workstation, which are connected to an information processing network. The information processing network is a system such as a LAN (Local Area Network), a WAN (Wide Area Network) such as the Internet, a wireless communication network, and the like, and what is indicated by 4 is an optical fiber, an ISDN line, or It means a transmission medium such as a wireless line. The transmission medium 4 is connected to, but not limited to, the host computer device 5 and the computer devices 1, 2, and 3 typically shown via communication adapters 6, 7, and 8 such as routers and terminal adapters. I have.
Although not particularly limited, the computer device 1 includes a processor (MPU) 9, a display controller (DISPC) 13, a network controller (NETC) 14, and a main memory (DRAM) 15 are connected. A floppy disk controller (FDC) 20, a keyboard controller (KEYC) 21, and an integrated device electronics controller (IDEC) 22 connected to the circuit are provided. The DISPC 13 performs drawing control on the video RAM (VRAM) 24, and controls display of the drawn display data on the display (DISP) 23. The NETC 14 is connected to the communication adapter 6 and performs buffering of transmission / reception information, communication protocol control, and the like. The DRAM 15 is used as a program area and a work area of the MPU 9. The floppy disk drive 16 is connected to the FDC 20 to read information from and write information to a floppy disk 25 which is an example of a recording medium. The keyboard 17 is connected to the KEYC 21. A hard disk drive (HDD) 18 and a CD-ROM drive (CDRD) 19 are connected to the IDEC 22. The HDD 18 has a magnetic disk as another example of the recording medium. The CDRD 19 has a CD-ROM 26 which is another example of the recording medium. The other computer devices 2 and 3 are configured in the same manner as described above.
When developing and designing a semiconductor integrated circuit using the computer device 1, for example, circuit design data such as a CPU provided on a floppy disk 25 or a CD-ROM 26 is read and temporarily stored in a hard disk drive device 18. At this time, the circuit data of the CPU described in FIG. 10 and the test program are stored in the floppy disk 25 and the CD-ROM 26. The test program may be provided not only on a recording medium such as the CD-ROM 26 but also via an information processing network. When designing a semiconductor integrated circuit using the computer device 1, by using the circuit data of the CPU 102 provided on the floppy disk 25 or the CD-ROM 26, the memory on-chip in the semiconductor integrated circuit can be efficiently used as described above. The development period of a semiconductor integrated circuit that can be tested quickly can be shortened. That is, the design and development of the semiconductor integrated circuit using the circuit data of the CPU 102 such as the IP module data provided on the floppy disk 25 or the CD-ROM 26 can be facilitated. In the memory test for the on-chip memory of the semiconductor integrated circuit developed and manufactured in such a manner, a test program provided on the floppy disk 25 or the CD-ROM 26 is loaded on the semiconductor integrated circuit, and the on-chip What is necessary is just to make the CPU execute the test program. Since the on-chip CPU supports the repeat queue function of the instruction queue 103 as a memory test function and enables elimination of a branch instruction from a test program, a memory test program optimized for CPU hardware can be executed. No need to develop from the beginning. As described above, a user who develops a semiconductor integrated circuit by using IP module data of a CPU or the like can improve the efficiency of the circuit design of the CPU and the test design for the on-chip memory. it can.
Since the test program for the memory test is executed by the on-chip CPU, the test program can be described in an assembly language or the like used for developing the program of the CPU. Can be easily changed. Therefore, when providing the IP module data of the CPU, the user of the IP module data can easily cope with various memory tests only by providing a sample program or the like as a test program for the memory test. .
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention.
For example, the respective configurations of the instruction queue having the loop queue mode, the memory corresponding to the memory test mode, and the BIST module are not limited to the above examples, and can be appropriately changed. For example, if the data bus is 32 bits and the instruction has a fixed length of 16 bits, the instruction queue may prefetch the instruction in units of 16 bits. In accordance with this, the instruction queue may prefetch instructions in 32-bit units. Further, the operation control content of the instruction queue in the loop queue mode is not limited to the above. Further, the on-chip module of the semiconductor integrated circuit is not limited to the above example, and can be appropriately changed. Further, the computer device constituting the development system of the semiconductor integrated circuit is not limited to being connectable to a network, but may be used stand-alone.
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
That is, since the instruction queue is operated as a loop queue, it is not necessary to use a branch instruction to enable the same test program to be repeatedly executed. Then, a test program to be repeatedly executed may be repeatedly fetched from the instruction queue, so that memory read / write access for memory test and memory access for instruction fetch do not conflict on the bus. Therefore, it is possible to eliminate the branch instruction from the test program, and it is not necessary to repeatedly fetch the same instruction from the bus connected to the CPU, so that the test efficiency of the semiconductor integrated circuit for the on-chip memory can be improved. Become.
If the design data of the CPU capable of setting the repeat queue mode is recorded and provided on a recording medium, the CPU can be designed using such design data, so that the on-chip memory can be efficiently tested. The development period of a semiconductor integrated circuit can be shortened.
By providing a memory test program using a CPU developed with the design data together with the design data on a recording medium and providing the same, the design and development of a semiconductor integrated circuit using the CPU can be facilitated. In a memory test for an on-chip memory of a semiconductor integrated circuit, the on-chip CPU only has to execute the test program, and the circuit design of the CPU and the test design for the on-chip memory can be made more efficient, and the development of the semiconductor integrated circuit can be made more efficient. be able to.
By providing a comparison / determination circuit for a memory test as dedicated hardware separate from the CPU, a comparison instruction for comparison / determination can be removed from a test program executed by the CPU. Test efficiency can be improved. When the read data to be compared and determined is led to the comparison and determination circuit through the dedicated bus, it is possible to avoid a situation in which the write data for the memory test competes with the read data on the bus.
Industrial applicability
INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit such as a data processor, a microcomputer, or a single-chip microcomputer having a built-in memory, and a test technique thereof.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a system LSI such as a microcomputer which is an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a block diagram illustrating in detail a connection state of circuit blocks related to a memory test.
FIG. 3 is a block diagram illustrating details of the BIST module.
FIG. 4 is an explanatory diagram of the registers held by the register section of the BIST module.
FIG. 5 is a block diagram illustrating the configuration of one page of the XY memory.
FIG. 6 is an explanatory diagram illustrating an address map of a general-purpose memory.
FIG. 7 is a logic circuit diagram illustrating the configuration of an enable control circuit for realizing the address map of FIG.
FIG. 8 is an explanatory diagram illustrating an address map of the XY memory.
FIG. 9 is a logic circuit diagram illustrating the configuration of an enable control circuit for realizing the address map of FIG.
FIG. 10 is a block diagram showing an example of a CPU.
FIG. 11 is a flowchart illustrating a procedure of a memory test in a case where relief is not performed on a general-purpose memory.
FIG. 12 is a flowchart showing an example of a procedure of a memory test when performing relief on a general-purpose memory.
FIG. 13 is an explanatory diagram showing an instruction sequence for performing the 13N test in an assembly language.
FIG. 14 is a timing chart of the CPU bus and the BIST-dedicated data bus during the execution of the phase L1 of the instruction sequence shown in FIG.
FIG. 15 is a block diagram illustrating a system LSI as another example of the semiconductor integrated circuit according to the present invention.
FIG. 16 is an explanatory diagram showing a technique of a 13N test which is one of the test sequences of the on-chip memory.
FIG. 17 is an explanatory diagram illustrating a test program for executing the L1 phase as a program according to a comparative example for performing a 13N test.
FIG. 18 is a timing chart of a bus connecting the CPU and the built-in memory when the test program according to the comparative example of FIG.
FIG. 19 is a flowchart illustrating the development and manufacturing procedure of a semiconductor integrated circuit having a self-test function as typified by FIG.
FIG. 20 is a block diagram showing an example of a system for developing a semiconductor integrated circuit.

Claims (8)

A method for testing a memory of a semiconductor integrated circuit having a CPU with an instruction queue, a memory, and a bus connecting the CPU and the memory,
The test program is stored in the instruction queue, and the CPU executes the test program to perform memory access via the bus. Once the test program is stored in the instruction queue, the test program is fetched in place of the bus. A memory test method, which is repeatedly performed from a queue. A method for testing a memory of a semiconductor integrated circuit having a CPU with an instruction queue, a memory connected to the CPU via a bus, and a determination circuit connected to the memory and the bus,
The test program is stored in the instruction queue, the test program is executed by the CPU to perform memory write access and memory read access, and the memory read access data is compared and determined by the determination circuit with an expected value. A memory test method, wherein fetching of a stored test program is repeatedly performed from an instruction queue instead of the bus. A recording medium on which design data read by a computer to determine the function of the CPU is recorded,
The design data includes respective circuit data of an instruction queue, a bus, an instruction decoder that decodes an instruction supplied via the instruction queue or the bus, and a control unit,
The instruction decoder controls the operation mode in which a predetermined repeat instruction is decoded so that the fetch of the program to be repeated after the program to be repeated is once stored in the instruction queue can be repeated from the instruction queue. A computer-readable recording medium having a function of setting in a section. An information recording medium on which computer-readable recording of CPU design data and a test program executable by the CPU realized by the design data,
The design data includes circuit data of an instruction queue, a bus, an instruction decoder, and a control unit,
The instruction decoder controls the operation mode in which a predetermined repeat instruction is decoded, so that a program to be repeated can be repeatedly fetched from the instruction queue after the program to be repeated is once stored in the instruction queue. Has the function of setting
The information recording method according to claim 1, wherein the test program is a program for a memory test stored in an instruction queue in the operation mode and causing the CPU to repeatedly execute a memory access process and a memory access address update process via a bus. Medium. A semiconductor integrated circuit having a CPU, a memory, and a bus connecting the CPU and the memory on a semiconductor chip,
The CPU includes an instruction queue, an instruction decoder for decoding instructions supplied through the instruction queue or the bus, and a control unit,
An operation mode in which the instruction decoder decodes a predetermined repeat instruction and instructs the control unit to repeatedly fetch the program to be repeated from the instruction queue after the program to be repeated is once stored in the instruction queue. A semiconductor integrated circuit characterized in that it is possible to set the following. In the operation mode, the CPU executes the program, inputs data read from the memory, and has a determination circuit for comparing a logical value of the input data with an expected value. 6. The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is configured to be able to output to outside. 7. The semiconductor integrated circuit according to claim 6, wherein a dedicated bus separated from the bus is provided as a path for supplying read data from a memory to the determination circuit. The memory has a plurality of memory blocks, and the memory blocks are mapped to the same address and enabled to operate in parallel in response to the setting of the operation mode,
8. The semiconductor integrated circuit according to claim 7, wherein said judgment circuit is capable of comparing and judging memory read data output from a plurality of memory blocks in parallel with an expected value.

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