JPH1041436A - Manufacture of semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the application of electroless Au-plating for manufacturing multilayered semiconductor package in excellent PCT resistance and high reli ability by forming a multilayered electric insulating layer using thermosetting polyphenylene ether resin, containing no glass cloth. SOLUTION: In order to improve the bonding properties onto an electric insulating layer 20, base processing 15 such as chemical processing, etc., is performed on the surface of the electric insulating layer 20 on a metallic plate 10. Next, the electric insulating layer 20 is formed using a thermosetting polyphenylene ether resin of high thermal resistant at Tg value of 180 deg.C and absorption rate of at most 0.05% excluding a glass cloth. Through these processes, the chemical resistance and the humidity resistance for providing the required insulating property under a specific humidity environment are improved. Accordingly, the application of electrodless Au-plating is made possible, thereby a multilayered a semiconductor package in excellent PCT resistance and high reliability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package using a metal plate as a package substrate.

[0002]

2. Description of the Related Art A semiconductor package using a metal plate as a substrate is formed by forming a wiring pattern on the surface of the metal plate via an electrical insulating layer and drawing the semiconductor device. It has excellent heat dissipation, electrical characteristics, sufficient strength and high reliability. As the electrical insulating layer, a thermosetting resin such as an epoxy resin or a bismaleimide-based polyimide resin, a thermoplastic resin, or the like is used.

[0003]

However, in the above-mentioned resin forming the electric insulating layer, epoxy resin is superior in cost as a general-purpose material. However, in order to resist deformation in drawing, a mixture is added. If flexibility is given, the Tg point will be lowered and bonding will not be possible, which is not suitable for semiconductor packages. Bismaleimide-based polyimide resins have high heat resistance and excellent dimensional stability, but have the disadvantage of high water absorption and cannot withstand PCT. Further, since the thermoplastic resin is melted by heat, a single-layer structure can be formed, but an electrical insulating layer for a multi-layer structure cannot be formed. Further, it is needless to say that glass cloth is not suitable because it is damaged during drawing. The present invention has been made in view of such a problem, and in a semiconductor package formed by drawing a metal plate, an electric connection is made by using a thermosetting PPE resin having high heat resistance and low water absorption without using glass cloth. An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor package having excellent PCT resistance by enabling application of electroless gold plating by forming an insulating layer.

[0004]

In order to achieve the above object, a package according to the present invention has the following configuration. That is, in a semiconductor package formed by forming a wiring pattern on the surface of a metal plate via an electrical insulating layer and drawing, the Tg value is 180 ° C., high heat resistance, and the water absorption is 0.05%.
It is small as below, has good chemical resistance, good adhesion strength with copper foil, etc., and also has good electrical properties. It is characterized in that an insulating layer is formed.

[0005]

According to the present invention, in a semiconductor package formed by forming a wiring pattern on the surface of a metal plate via an electrical insulating layer and drawing, a high heat resistance, a Tg value of 180 ° C.
By forming an electrical insulating layer using a thermosetting PPE resin having a water absorption of 0.05% or less without using a glass cloth, electroless gold plating can be applied and high reliability with excellent PCT resistance Of the present invention can be provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. FIG. 1 is an explanatory view showing a method for manufacturing a single-layer semiconductor package according to the present invention, in order to facilitate understanding of the method for manufacturing a multilayer semiconductor package according to the present invention. FIG. 1A shows a metal plate 10 used as a package substrate. Since the metal plate 10 is subjected to drawing in a later step, a material that can easily secure an elongation of about 5% or more so as to minimize deformation during the drawing is preferable. In this embodiment, a copper plate having a thickness of 0.4 mm was used.
The metal plate 10 is subjected to a base treatment 15 such as a chemical treatment on the surface on which the electrical insulating layer is to be formed, in order to improve the adhesion to the electrical insulating layer. FIG. 1B shows a metal plate 10 subjected to a base treatment.
2 shows a state in which the electric insulating layer 20 is formed by deposition. Although the electrical insulating layer 20 is formed by applying a thermosetting PPE resin in a film form, a method of applying a liquid resin may be used. Even if the thickness of the electrical insulating layer 20 is about 20 μm, sufficient electrical insulation can be obtained. The electrical insulating layer 20 is required to have a heat resistance of 260 ° C. or higher in the soldering step and a Tg value of 140 ° C. or higher to prevent softening in the bonding step. Further, since electroless gold plating is performed in a later step, chemical resistance is also required, and furthermore, moisture resistance is required in order to have required insulation under a predetermined humidity environment. It is a feature of the present invention to form a multilayer structure by applying a thermosetting PPE resin without a glass cloth as a material for forming an electrical insulating layer satisfying these required characteristics. FIG. 1 (c)
Shows a state in which a copper foil 30 for forming a wiring pattern is adhered to the electrical insulating layer 20. The copper foil 30 has a thickness of 10 so that the wiring pattern does not break during the drawing process in the subsequent step.
It is necessary that an elongation of about% can be secured. A metal foil other than a copper foil can be used as long as it has the required elongation and electrical characteristics. In this embodiment, 18 to 3
5 μm copper foil was used. FIG. 1D shows a state where a required wiring pattern 40 is formed. In this embodiment, the wiring pattern 40 was formed by etching the copper foil 30 by applying a normal pattern forming method. FIG. 1E shows a state in which after forming a gold plating resist layer 50 covering portions other than the portion to be subjected to electroless gold plating, the electrical insulating layer 20 covering the semiconductor element mounting surface of the metal plate 10 is removed. Since the gold plating resist layer 50 also needs to satisfy the same required characteristics as the electrical insulating layer 20, it is preferable to form the gold plating resist layer 50 using a thermosetting PPE resin. FIG. 1 (f) shows that the metal plate 10 is drawn using a press machine, and the recessed portion 10 a for mounting the semiconductor element, the step surface 10 b for supporting the inner lead 45, and the mounting surface 10 c for mounting the external connection terminal are formed. This shows a molded state. At this time, since no wiring pattern is formed at the connection portion between the accommodation recess 10a and the step surface 10b, the inclination can be made steep to shorten the bonding distance, and the connection between the step surface 10b and the mounting surface 10c can be reduced. The part is wiring pattern 4
0, since it is bent together with the electrical insulating layer 20 and the gold plating resist layer 50, it is important to form a gently inclined surface in order to prevent problems such as disconnection of the wiring pattern 40. In the present embodiment, two-step drawing of the step surface 10b and the mounting surface 10c is performed. Depending on the product, it can be formed in one or more stages. FIG. 1 (g) shows the inner lead 4
FIG. 5 is a cross-sectional view of a semiconductor package in which connection pads 46 and the like are subjected to electroless gold plating. It is also possible to thicken the electroless gold plating only on the inner leads 45 using a mask. Thereafter, the semiconductor chip is mounted by wire bonding or the like, and solder balls are attached to complete the package assembly.

FIG. 1 shows a method of manufacturing a single-layer semiconductor package according to the present invention. FIG. 2 is an explanatory view showing a method of forming a wiring pattern in multiple layers, which is a feature of the present invention. Note that FIG. 2 shows only the characteristic portions that are formed in multiple layers.
FIG. 2A shows a state in which a copper foil 30 is formed on a metal plate 10 via an electrical insulating layer 20 using the above-mentioned thermosetting PPE resin. FIG. 2B shows a state in which the copper foil 30 is etched to form a hole 20 a in a required portion in order to electrically connect the metal plate 10 and a required wiring pattern 40. The hole 20a is for providing a connection hole 70 for interlayer connection in the electrically insulating layer 20. FIG. 2 (c)
A state in which a connection hole 70 is provided in the electrically insulating layer 20 by irradiating a laser beam to the portion of the hole 20a is shown. FIG. 2 (d)
The state where the conductive portion 80 is formed on the inner wall surface of the connection hole 70 by copper plating is shown. At this time, the copper plating layer 85 is also formed on the surface of the copper foil 30. FIG. 2E shows that the copper foil 30 and the copper plating layer 85 are etched to form the electrical insulating layer 20.
5 shows a state in which a required wiring pattern 40 supported by is formed. The wiring pattern 40 is electrically connected to the metal plate 10 via the conductive part 80. FIG. 2 (f) shows that in order to further form a wiring pattern on the upper layer of the wiring pattern 40,
Further, a state in which the electric insulating layer 201 and the copper foil 301 are formed by adhesion is shown. FIG. 2G shows a state in which the steps from FIG. 2F to FIG. 2B to FIG. 2E have been performed. In this way, multiple layers of wiring patterns can be formed while maintaining electrical conduction one after another.

[0008]

According to the semiconductor package of the present invention,
A thermosetting PPE resin having a high heat resistance, a Tg value of 180 ° C. and a water absorption of 0.05% or less, in a semiconductor package formed by forming a wiring pattern on the surface of a metal plate via an electrical insulating layer and drawing. Is used without using a glass cloth to form an electrical insulating layer, so that electroless gold plating can be applied, and a highly reliable multilayer semiconductor package with excellent PCT resistance can be provided. The present invention
Of course, it can be widely applied to substrates such as COB, LCC, BGA, and MCM.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing one embodiment of a method of manufacturing a semiconductor package according to the present invention.

FIG. 2 is an explanatory view showing a method for manufacturing a multilayer wiring pattern according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Metal plate 20 Electrical insulation layer 30 Copper foil 40 Wiring pattern 45 Inner lead 46 Connection pad 50 Gold plating resist layer 60 Nickel / gold plating 70 Connection hole 80 Conductive part 85 Copper plating layer 201 Electrical insulation layer 301 Copper foil 401 Wiring pattern 801 conductive part

[Procedure amendment]

[Submission date] October 7, 1996

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

Claims (1)

[Claims] 1. A wiring pattern for connecting a semiconductor element and an external connection terminal is formed on one surface of a substrate formed of a metal plate via an electrical insulating layer, and the wiring pattern and the electrical connection are formed together with the substrate. By drawing the insulating layer, a housing recess for mounting the semiconductor element, one or more step surfaces for supporting the wiring pattern around the housing recess, and external connection terminals around the step surface are formed. In a method of manufacturing a semiconductor package for forming a mounting surface for bonding, a multilayer structure is formed by using a thermosetting polyphenylene ether resin (hereinafter, referred to as a PPE resin) without a glass cloth as the electrical insulating layer. A method of manufacturing a semiconductor package, comprising: forming a semiconductor package;