JPH1039276A - Liquid crystal panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the picture quality and to prevent a liquid crystal from being degraded by connecting switching elements to terminal positions and a fixed potential lower than threshold values of TFTs and turning on the switching elements in synchronization with the rising and the falling of ON voltage waveforms of the TFTs(thin film transistor) to suppress the variation of field through voltages. SOLUTION: In respective switching elements 28i, drains and sources of TFTs are connected between a terminal position P of gate bus lines 24i and a first wiring 29 and gates are alternately connected to a second wiring 30 and a third wiring 31 for every other line. A fixed potential VOFF being lower than threshold values of TFT(j ,i) of pixels 27(j ,i) is applied to the first wiring 29. Moreover, first and second control signals S1 , S2 are applied to the first and second wirings 30, 31. The first and second control signals S1 , S2 are changed to second potential levels in synchronization with the raising and the falling of the ON voltage of the TFTs and the switching elements 28i to be connected to respective gate bus lines 24i are turned on in response to these changes and potentials of the lines are pulled down to the fixed potential VOFF.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal panel using a TFT (Thin Film Transistor) as a switching element, and more particularly, to improving the image quality and preventing the liquid crystal from deteriorating by suppressing the variation of the field-through voltage. The present invention relates to a liquid crystal panel intended.

[0002]

2. Description of the Related Art FIG. 4 is a schematic plan view of a conventional liquid crystal panel. In this figure, for convenience of illustration,
The number of pixels is much smaller than the actual number (6 × 6 pixels). 4, 1 is a liquid crystal panel, the liquid crystal panel 1 includes a data bus lines 2 ₁ to 2 ₆ six laid in the vertical direction of the screen, laid out in the lateral direction 6
A gate bus line 3 ₁ to 3 ₆ of the present, and a 6 × 6 pixels laid at the intersection of each line, each pixel in the same size and the same configuration all made of a transparent conductive material such as ITO It is composed of a pixel electrode 4 and a TFT 5.

A data line driving circuit 6 outputs a display voltage for one line (6 pixels) to all data bus lines 2 _j (j is 1 to 6) in synchronization with a horizontal scanning signal (not shown). Is a gate line drive circuit that outputs a predetermined “TFT ON signal” (described later) to each gate bus line 3 _i (i is 1 to 6) in line sequence in synchronization with a horizontal scanning signal.

FIG. 5 is a detailed layout diagram of each pixel. In this figure, the TFT 5 is an amorphous Si TFT using a part of each of the data bus line 2 _j and the gate bus line 3 _i as a drain electrode or a gate electrode and using an amorphous Si 8 formed on a glass substrate as a channel layer.
But it is not limited to this. It may be a polycrystalline SiTFT.

In FIG. ₁ , the display voltage written to the pixel electrode 4 is reduced by enlarging a part of the next-order gate bus line 3 _{i + 1} and making the enlarged portion face the pixel electrode 4. The additional capacitance C _ADDi for holding is formed (additional capacitance method), but is not limited to this. A “storage capacitor type” in which the counter electrode of the pixel electrode 4 is drawn out at a terminal different from the gate bus line may be used. However, it is emphasized that the parasitic capacitance of the gate bus line is larger in the case of the additional capacitance method, and the problem of the later-described variation in the field-through voltage is likely to be caused.

FIG. 6 is a circuit diagram of the additional capacitance system. Elements common to those in FIG. 5 are denoted by the same reference numerals.
In FIG. 6, C _ADDi and C _{ADDi + 1} are the additional capacitances described above,
C _{LC i} and C _{LCi + 1} is (also referred to as common electrodes) common electrode and the liquid crystal electrode 4 liquid crystal capacitor formed between the V _COMM, C
_gdi , C _{gdi + 1} , C _gsi , C _{gsi + 1} , C _dsi and C _{dsi +
1} is the inter-electrode capacitance of _TFT5 , C _gCOMMi and C
_{gCOMMi + 1} is a common electrode V _COMM and a gate bus line 2 _i , 2
_This is the capacitance formed between _{i + 1} . The suffix “g” of the code is the gate electrode of the TFT 5, “s” is the source electrode,
“D” indicates a drain electrode.

FIG. 7 is a model diagram of FIG. 6, focusing on the (i + 1) th gate bus line 3 _{i + 1} . According to this model diagram, the total parasitic capacitance C of the gate bus line 3 _{i + 1} is given by the following equation.

[0008]

(Equation 1)

FIG. 8 and the following equation are a model diagram in the storage capacity method and a formula for calculating the parasitic capacitance C 'of the gate bus line _{3i + 1} . In FIG. 8 and the following equation,
C _ST is the storage capacity.

[0010]

(Equation 2)

[0011]

By the way, the writing time of one line in the liquid crystal panel is within a certain time determined by the width of the "TFT ON signal" from the gate bus line driving circuit (see reference numeral 7 in FIG. 4). Must complete.
However, the TFT ON signal is a “rectangular” pulse whose width is uniquely determined by the horizontal scanning frequency. In general, a rectangular pulse has a rising or falling current change (di / dt). Because it is large, it is easily affected by the time constant in the signal path, and the actual rising and falling waveforms are curvilinear along the time constant curve.
A waveform having a large curvature is referred to as a "waveform rounding is large". Moreover, since the waveform rounding increases toward the end of a signal path (a gate bus line in a liquid crystal panel), the following applies. As described in detail above, there has been a problem that the dispersion of the field-through voltage of the liquid crystal voltage becomes large, which causes deterioration of image quality and liquid crystal.

Hereinafter, the above problem will be described in detail. FIG. 9 is an equivalent circuit for one line of the liquid crystal panel. In this figure, reference numeral 10 denotes an input terminal of a TFT ON signal (that is, an output terminal of the gate bus line driving circuit 7 in FIG. 4), and this terminal 10 is a wiring 11 between the gate bus line driving circuit 7 and the liquid crystal panel. Through to the gate bus line 12 of the liquid crystal panel. R ₁₁ and C ₁₁ represent the resistance component and capacitance component of the wiring 11, respectively. Gate bus line 12 represents are equivalent for each pixel, R _12, and C ₁₂ of each pixel is a resistance component and a capacitance component of each pixel (corresponding to the above C or C '), respectively.

Now, two points a on the data bus line 12,
Focusing on b, consider the waveform delay of the TFT ON signal at each point. a is a point closest to the terminal 10. The TFT ON signal at this point a is referred to as Sa for convenience. b is the point farthest from the terminal 10 (in other words, at the end of the data bus line). The TFT ON signal at this point b is referred to as Sb for convenience.

FIG. 10 shows two TFT ON signals Sa and S.
It is a waveform comparison figure of b. Both signals Sa and Sb are 1
This is a rectangular pulse that changes from rising to falling in a predetermined writing period Tx allocated within the horizontal scanning period. Waveform rounding of the signal Sa is those minute caused by the time constant of R ₁₁ and C _11, waveform distortion of the signal Sb, the R ₁₁ and the time constant of the C _11, several more lines of pixels fraction R _This is a large one caused by the time constant obtained by adding ₁₂ and C ₁₂ . Therefore, the fall of the signal Sb is considerably delayed as compared with the signal Sa. It should be noted that the rise is delayed, but is ignored because it has no direct relationship with the field-through voltage.

FIG. 11 is a waveform diagram of each electrode of the TFT.
An arbitrary gradation potential (Vd for convenience) is applied to the drain electrode of the TFT.
When a TFT-on signal is applied to the gate electrode in a state where a display voltage having the above-mentioned voltage is applied, the TFT is turned on at the time when the TFT-on signal becomes sufficiently high (time t0 when it coincides with the peak voltage Vg for convenience). Turn on immediately. Therefore, the potential of the source electrode (or pixel electrode) starts to change toward the electric potential Vd of the drain electrode, after reaching Vd at time T _1, at the time T ₂ of the fall of the TFT-on signal, a predetermined voltage It stabilizes only at the lowered potential. This predetermined voltage and Vg
Is the field-through voltage, which is a voltage given by the following equation.

[0016]

(Equation 3)

Here, C _gs is the gate-source capacitance of the TFT, C _ds is the drain-source capacitance, C _LC is the pixel electrode capacitance, C _ADD is the additional capacitance, and ΔVg is the amplitude of the TFT ON signal. As can be understood from the equation, the field-through voltage is affected by the gate-source capacitance C _gs among the inter-electrode capacitance of the TFT. This is because an abrupt potential change component (particularly, a falling component of the FET ON signal) on the gate bus line jumps into the pixel electrode through this capacitance. The rising component is canceled by writing a signal from the data bus line, but the falling component remains as it is. When this residual component appears as a DC component,
Since a direct current voltage is constantly applied to the liquid crystal, which has various adverse effects on the panel characteristics (burn-in, flicker or afterimage, etc.), the common electrode voltage of the liquid crystal pixel (V _COMM )
Is accurately matched to the positive and negative center levels of the source electrode waveform, thereby reducing the DC component to zero.

However, such a measure is effective only when there is no variation in the field-through voltage. Therefore, as long as the variation is not suppressed, it is impossible to reduce the DC component to zero over the entire panel. To any extent, adverse effects such as partial burn-in, flicker or afterimages are inevitable. Therefore, an object of the present invention is to improve the image quality and prevent the deterioration of the liquid crystal by suppressing the variation of the field-through voltage.

[0019]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a plurality of gate bus lines and a large number of data bus lines arranged in an intersecting manner, and each of the gate bus lines and the data bus lines. In a liquid crystal panel including a pixel arranged at an intersection, each pixel includes a TFT having a gate electrode connected to the gate bus line, a drain electrode connected to the data bus line, and a source electrode connected to the pixel electrode. A switch element having one end connected to an end position (or a position close to the end; hereinafter, representatively referred to as an end position) of the gate bus line and the other end connected to a constant potential lower than a threshold value of the TFT; Control means for turning on the switch element for a predetermined time in synchronization with the fall of the TFT ON voltage waveform applied to the gate bus line. And butterflies.

According to this, (a) the TFT is turned on from the rise to the fall of the TFT ON voltage waveform on the gate bus line, and writes the voltage of the data bus line to the pixel electrode during the ON period. , (B), the switch element is turned on simultaneously with the “falling” of the TFT on-voltage waveform, and connects the terminal position of the gate bus line to “constant potential below the threshold value of the TFT”. ,
Since the fall of the TFT ON voltage waveform at the end position of the gate bus line becomes sharp and coincides with or close to the fall time at the start position of the line, the variation of the field-through voltage is suppressed.

The control means of the present invention turns on the switch element connected to the i-th gate bus line for a predetermined time in synchronization with the fall of the TFT-on voltage waveform applied to the i-th gate bus line. It is desirable that the switch be turned on (for convenience, referred to as a “line-only method”). Note that i is 1 to n, and n is the number of vertical lines.

If the line-only system is not used, the switch elements connected to the i-th gate bus line are all T elements.
Since it is turned on in synchronization with the fall of the FT-on signal waveform, the rising portion of the i-th TFT-on voltage waveform is cut only during the ON period of the switch element, and the width of the i-th TFT-on voltage waveform is reduced. It is. This leads to the disadvantage of insufficient writing, particularly in the case of a high definition liquid crystal panel in which the writing time per pixel is extremely short. If you use a line-only system,
Such an inconvenience does not occur because the ith switch element is turned on only once during one vertical scanning period.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view of a layout of a main part of a liquid crystal panel of this embodiment employing a line-only system.
Denotes a liquid crystal panel, 21 denotes a gate line driving circuit, and 22 denotes a control circuit (control means).

In the following description, i is 1 to n,
j is 1 to m, n is the number of vertical lines, and m is the number of pixels in one line. For example, the XGA standard (n × m = 768 ×
In the case of the liquid crystal panel of 1024), i ranges from 1 to 768, and j ranges from 1 to 1024. LCD panel 20
Represents m data bus lines 23 _j (in the figure, the m-th gate bus line 23 _m is shown), and n
Gate bus lines 24 _i (in the figure, n-2 of them)
Three gate bus lines 2 from the nth to the nth
4 _n−3 , 24 _n−1 , and 24 _n are arranged in a cross shape, and at each cross point, a TFT 25 _{(j, i)} and a pixel electrode 26
_{Although the} pixel 27 _{(j, i)} composed of _{(j, i)} is arranged in common with the conventional example (FIG. 4), the difference is that a so-called black matrix portion outside the effective display area has the following configuration. I do.

That is, in the black matrix portion,
n switch elements 28 _i (in the figure, three switch elements 28 _n−3 , 28 _n−3 from n−2 to n)
_n-1, and it is) shows a 28 _n, vertically laid down by three wires of the panel (the first wiring 29, the second wiring 30, and the third wiring 31) and the are provided, each switch Element 28
_{For i} , for example, a TFT is used, and the drain of the TFT is
Between the sources, the end position P _i of the gate bus line 24 _i having the same subscript (may be a position near the end) and the first wiring 29.
And the gates are alternately connected to the second wiring 30 and the third wiring 31 line by line.

The TF of the pixel 27 _{(j, i)} is
T25 (j, _i) is given a constant potential V _OFF below the threshold, also, the second wiring 30, the first control signal S ₁ is supplied from the control circuit 22, further, a third Wiring 31
Is also supplied with a second control signal S ₂ from the control circuit 22. Here, the first and second control signals S ₁ , S _1
2 is a signal having the following characteristics. (1) The first control signal S ₁ is set to 1 during the odd-numbered horizontal scanning period.
Times occurs, the second control signal S ₂ is generated once to the even-numbered horizontal scanning period. However, when n is an odd number. When n is an even number, odd and even in the horizontal scanning period are switched. (2) The potential levels of the first and second control signals S ₁ and S ₂ are normally at a first potential level sufficient to turn off the switch element 28 _i , but the gate line drive circuit 21
In synchronism with the fall of the TFT on-voltage waveform generated at the switch element 28 _i
Is turned on), and the second potential level is maintained for a predetermined time (about the maximum delay time of the fall of the TFT on-voltage waveform).

FIG. 2 shows the TFT on-voltage waveform at the end position P _i of the gate bus line 24 _i (for the sake of convenience, the same number as the line number) and the first and second control signals S
₁ is a chart showing the timing relationship between S _2. For the reason described at the beginning, the TFT ON voltage waveform 24 _n−2 (or 2) at the terminal position P _i of the gate bus line 24 _i.
4 _n ) and 24 _n-1 fall slowly,
In this embodiment, the first and second control signals S ₁ and S ₂ are TF
The potential changes to the second potential level in synchronization with the fall of the T-on voltage waveform, and in response to this, each gate bus line 24
_{Since the} switch element 28 _i connected to _i is turned on, the potential of each gate bus line 24 _i is reduced to the constant potential V _OFF at the same time as the fall of the TFT ON voltage waveform.
The falling of the waveform can be made steep. As a result, it is possible to reduce the time difference between the falling of the start position of the gate bus line 24 _i (the position close to the gate line drive circuit 21) at the terminal positions P _i, suppress variations in the field-through voltage at the outset be able to.

In this embodiment, the gate bus line 2
4_iInto odd and even groups, and each group
Control signal (S₁, S_Two), But this
Not limited to For example, writing time to pixels is relatively long
When applied to a liquid crystal panel, the first control signal S₁
And the second control signal S_TwoAnd the third control signal S _Three
And the third control signal S_ThreeThe all switch elements
28_iMay be shared.

In FIG. 3, the third control signal S ₃ periodically changes to the second potential level every horizontal scanning period. Here, when the respective periods of the second potential level are identified by reference numerals A to F, in the period A, the n-6th TFT
The falling of the ON signal 24 _n−6 is cut, the falling of the (n−5) th TFT on signal 24 _n−5 is cut in the period (b), and the n−4th TFT on signal 2 in the period (c).
Since the fall of 4 _n−4 is cut and the fall of the (n−1) th TFT ON signal 24 _n−1 is cut during the period, the same operation and effect as described above can be obtained. .

However, in this example, there is a disadvantage that the rising portion of the TFT ON signal is unintentionally cut. That is, the rising portion of the (n−5) th TFT ON signal 24 _n−5 is cut in the period (a), the rising portion of the (n−4) th TFT ON signal 24 _n−4 is cut in the period (b), and n in the period (c). The rising portion of the _third TFT ON signal 24 _n−3 is cut off,.
During the period, the rising portion of the n-th TFT ON signal 24 _n is cut, so that the present invention can be applied only when the writing time to the pixel falls within the time (Tα) after the cut.

[0031]

According to the present invention, it is possible to suppress the variation of the field-through voltage, to further improve the image quality, and to completely prevent the deterioration of the liquid crystal. Not a particularly advantageous effect is obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a layout of a main part of an embodiment.

FIG. 2 is a timing chart of a TFT on-voltage waveform and a control signal according to one embodiment.

FIG. 3 is a timing chart of a TFT ON voltage waveform and a control signal according to another embodiment.

FIG. 4 is a schematic plan view of a conventional liquid crystal panel.

FIG. 5 is a detailed layout diagram of pixels.

FIG. 6 is a circuit diagram of an additional capacitance method.

FIG. 7 is a model diagram of an additional capacity method.

FIG. 8 is a model diagram of a storage capacity method.

FIG. 9 is an equivalent circuit diagram for one line of a conventional liquid crystal panel.

FIG. 10 is a waveform comparison diagram of two TFT ON signals Sa and Sb.

FIG. 11 is a waveform diagram of each electrode of a TFT.

[Explanation of symbols]

P _i : terminal position V _OFF : constant potential 22: control circuit (control means) 23 _j : data bus line 24 _i : gate bus line 25 _i : TFT 26 _i : pixel electrode 27 _i : pixel 28 _i : switch element

Claims (2)

[Claims] A plurality of gate bus lines and a plurality of data bus lines arranged in an intersecting manner, and pixels arranged at respective intersections of the gate bus lines and the data bus lines, wherein each pixel has a gate electrode. Connecting to the gate bus line, connecting the drain electrode to the data bus line,
In addition, in a liquid crystal panel including a TFT having a source electrode connected to a pixel electrode, one end is connected to an end position or a position close to the end of the gate bus line, and the other end is set to a constant potential lower than a threshold value of the TFT. A liquid crystal panel comprising: a connected switch element; and control means for turning on the switch element for a predetermined time in synchronization with a fall of a TFT-on voltage waveform applied to the gate bus line. 2. The control means turns on a switch element connected to an i-th gate bus line for a predetermined time in synchronization with a fall of a TFT-on voltage waveform applied to the i-th gate bus line. The liquid crystal panel according to claim 1, wherein: