JPH10335614A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is enhanced in operating speed and lessened in area. SOLUTION: Gate wirings 22 and 23 which are divided in two and arranged in parallel with each other are provided to a transistor 21, and source contacts 28 and 29 and a drain contact 27 are arranged along the gate wirings 22 and 23 in order of contact numbers 28, 27, and 29. Source wirings 32 and 33 and a drain wiring 31 connected to the contacts 27 to 29 respectively are formed above the gate wirings 22 and 23 crossing them at right angles, and the source contacts 28 and 29 are arranged adjacent to the drain contact 27 in the direction which the wirings 31, 32, and 33 are formed. The gate wirings 22 and 23 are bent twice between the contacts 28 and 27 and between the contacts 27 and 29 formed on each side of the gate wirings 22 and 23 so as to be arranged surrounding the drain contact 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
More specifically, the present invention relates to a layout of a MOS transistor (MOS-FET) formed on a chip of a semiconductor device.

In recent semiconductor integrated circuit devices, higher integration and higher speed have been promoted, and the number of transistors formed on a chip of the semiconductor device has increased. Many transistors increase the cost by increasing the chip area of the semiconductor device.
T is required.

[0003]

2. Description of the Related Art FIG. 8 is a layout diagram of a transistor 11 formed on a chip of a conventional semiconductor integrated circuit device. The transistor 11 includes two gate wires 12. The region between the two gate lines 12 is the drain 13 of the transistor 11, and the region on the opposite side of the drain 13 with respect to the two gate lines 12 is the source 14. The drain 13 is connected via a contactor 15 to a drain wiring 16 formed in parallel with the gate wiring 12. In addition, both sources 14 are respectively contactor 1
7 are connected to source lines 18 which are also formed in parallel with the gate lines 12.

A transistor 11 shown in FIG. 8 has, for example, two gate wirings 12 and two source wirings 18.
A common signal is supplied and used. Then, the transistor 11 has the gate wiring 12 disposed with the contactor 15 connected to the drain 13 interposed therebetween,
This is effective in reducing the drain capacitance by reducing the junction area of the drain 13 and reducing the load capacitance. Also,
The two divided gate lines 12 of the transistor 11 are effective in increasing the gate line length to increase the effective gate width and reducing the on-resistance of the transistor 11.

[0005]

By the way, as for a semiconductor integrated circuit device, a higher integration and a higher speed are further advanced, and a transistor which operates at a high speed is required. for that reason,
For example, by increasing the size and increasing the effective gate width of the transistor 11, the on-resistance is reduced and the speed is increased. However, transistor 11
When the size of the transistor 1 is increased, the junction area of the drain 13 sandwiched between the two gate wires 12 is increased,
Since the capacitance component (drain capacitance) of 1 itself becomes large,
There is a problem that the effect of reducing the on-resistance cannot be fully utilized. In addition, when the semiconductor integrated circuit device is highly integrated, the number of transistors mounted on the chip increases and the chip area increases, which causes a problem that the cost of the device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a small-sized semiconductor device suitable for high-speed operation.

[0007]

According to the present invention, in order to achieve the above object, the invention according to claim 1 includes a gate wiring divided into two, and is sandwiched between gate wirings arranged in parallel. A semiconductor device comprising a region as a drain, a region opposite to the drain with respect to the gate line as a source, and a source contactor and a drain contactor for supplying a signal to the source and the drain, respectively. A source contactor, a drain contactor, and a source contactor are arranged in this order along the gate line, are formed in a layer above the gate line, and are connected to the contactors to supply signals to the source and drain, respectively. Wiring is formed along a direction orthogonal to the gate wiring, and the source is formed in the forming direction of the wiring. The scan contactor located close to the drain contactor and disposed so as to surround the drain contactor is bent twice between the formed gate lines to both sides of each said gate line contactor.

According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a gate wiring divided into two parts; a region sandwiched between the gate wirings arranged in parallel as a drain; In a semiconductor device having a region as a source and a source contactor and a drain contactor for supplying a signal to the source and the drain, respectively, the contactor is arranged along the gate wiring in the order of a source contactor, a drain contactor, and a source contactor. Forming a source line for supplying a signal to the source and a drain line for supplying a signal to the drain along the gate line, wherein the source line and the drain line are formed in a layer above the gate line. And a wiring connecting each of the contactors is formed orthogonal to the gate wiring, and the connection wiring is formed. The source contactor in the formation direction is arranged close to the drain contactor and disposed so as to surround the drain contactor is bent twice between the formed gate lines to both sides of each said gate line contactor.

The invention described in claim 3 is the first or second invention.
In the semiconductor device described in (1), a plurality of the respective contactors are provided, and the plurality of the source contactors and the drain contactors are alternately arranged along the gate wiring.

The invention described in claim 4 is the first or second invention.
In the semiconductor device described in (1), a plurality of the respective contactors are provided, and the plurality of source contactors and drain contactors are repeatedly arranged along the gate wiring in a set of a source contactor-drain contactor-source contactor.

[0011] The invention according to claim 5 provides the invention according to claims 1 to 4.
5. A plurality of transistors formed of the semiconductor device according to any one of the above items are formed in the same region along a direction in which a wiring connected to the contactor is formed.

According to a sixth aspect of the present invention, there is provided a gate wiring divided into two and arranged in parallel, one of the regions divided by each of the gates being a source, and the other being a drain, Forming a drain contactor and a source contactor for supplying a signal to the drain and the source, respectively, arranging the contactors alternately along the gate wiring, and forming the contactor in a layer above the gate wiring; Connected drain,
A wiring for supplying a signal to a source is formed along a direction orthogonal to the gate wiring, and the drain contactor is arranged closer to the source contactor in a direction in which the wiring is formed. A plurality of transistors, which are bent two times between the contactors formed to surround the source contactor, are formed adjacent to each other along the forming direction of the wiring connected to the contactor.

(Operation) Therefore, according to the first aspect of the present invention, the source contactor and the drain contactor are arranged along the gate wiring with respect to the gate wiring divided into two and arranged in parallel. They are arranged in the order of contactor and source contactor. The source wiring and the drain wiring connected to each contactor are formed above the gate wiring and along the orthogonal direction,
The source contactor is arranged closer to the drain contactor in the direction in which the wiring is formed. Then, each gate wiring is bent twice between contactors formed on both sides of the gate wiring, and is arranged so as to surround the drain contactor. Therefore, the drain capacitance is small, the effective gate width is large, the on-resistance is small, and a semiconductor device with a small area is formed.

According to the second aspect of the present invention, the source contactor and the drain contactor are arranged along the gate wiring with respect to the gate wiring divided into two and arranged in parallel. They are arranged in order. The source wiring and the drain wiring connected to each contactor are located above the gate wiring and are formed along the gate wiring, and the wiring connecting the source wiring, the gate wiring and the contact is formed perpendicular to the gate wiring. You. The source contactor is arranged closer to the drain contactor in the direction in which the connection wiring is formed. Then, each gate wiring is bent twice between contactors formed on both sides of the gate wiring, and is arranged so as to surround the drain contactor. Therefore, the drain capacitance is small, the effective gate width is large, the on-resistance is small, and a semiconductor device with a small area is formed.

According to the third aspect of the present invention, the effective channel width of the plurality of transistors formed by alternately arranging the plurality of source contactors and the drain contactors along the gate wiring is increased, and the on-counter resistance is reduced. .

According to the fourth aspect of the present invention, a plurality of source contactors and drain contactors are formed by repeatedly arranging a set of a source contactor-drain contactor-source contactor along a gate wiring. The channel width increases and the on-resistance decreases.

According to the invention described in claim 5, according to claim 1,
5. A plurality of transistors each including the semiconductor device according to any one of Items 4 to 4 are provided in the same region along the formation direction of the wiring connected to the contact, thereby forming a semiconductor device having an area.

According to the semiconductor device of claim 6, 2
One of the divided regions divided by the gate wiring arranged in parallel is a source, and the other region is a gate. A source contactor and a drain contactor for supplying a signal are formed on the source / gate, respectively. These contactors are alternately arranged along the gate wiring. On the layer above the gate wiring, a wiring connected to each contactor and supplying a signal is formed along a direction perpendicular to the gate wiring. Then, the drain contactor is arranged closer to the source contactor in the formation direction of the connection wiring. Further, the gate wiring is bent twice between the contacts formed on both sides of the gate wiring, and the transistor is formed so as to surround the source contact. A plurality of such transistors are formed adjacent to each other along the direction in which the wiring connected to the contactor is formed, and the drain and source are made common to form a semiconductor device having a small area.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, a MOS transistor (MOS-FET, hereinafter simply referred to as a transistor) 21 includes two divided gate wirings 22 and 23. The gate wirings 22 and 23 are
It is formed along the longitudinal direction (vertical direction in FIG. 1) for the substantially rectangular region.

The transistor 21 has two gate lines 22,
A region sandwiched between the gate wirings 2 and 3 is a drain 24 and a gate wiring 2
Regions 2 and 23 are opposite to the drain 24 and are the sources 25 and 26. Drain 24, source 25, 2
6, a drain contactor 27 and source contactors 28 and 29 are formed.

The transistor 21 has a drain wiring 31 and source wirings 32 and 33. The drain / source wires 31 to 33 are formed in parallel with each other.
It is formed so as to extend along a direction orthogonal to the gate wirings 22 and 23 (left and right direction in FIG. 1). Therefore, the drain / source wirings 31 to 33 are formed above the gate wirings 22 and 23.

The drain 24 is connected to a drain wiring 31 via a drain contactor 27. The sources 25 and 26 are source contactors 28 and 29, respectively.
Are connected to the source wirings 32 and 33 via the.

Each of the contactors 27 to 29 is arranged in the order of a source contactor 28, a drain contactor 27, and a source contactor 29 along the gate wirings 22 and 23. The drain contactor 27 is formed substantially at the center of the transistor 21, and the source contactors 28 and 29
Is the transistor 21 across the drain contactor 27.
Are formed on substantially diagonal lines.

The source contactors 28 and 29
Since the drain / source lines 31 to 33 are formed along the horizontal direction, the conventional transistor 11 shown in FIG.
From the center, that is, the drain-source wirings 31 to
In the forming direction of 33, it is arranged close to the drain contactor 27. Therefore, the width of the transistor 21 of the present embodiment in the left-right direction is smaller than that of the conventional transistor 11.

The gate wirings 22 and 23 are arranged with the drain contactor 27 interposed therebetween. Both gate wirings 22,
23 is a contactor 28 sandwiching each gate wiring,
27 is formed between the contactor 27 and the contactor 27, 29 in a crank shape bent twice, and is arranged so as to surround the drain contactor 27, and the area of the drain 24, which is a region sandwiched between both gate wirings, is minimized. Are arranged as follows.

One of the two gate lines 22 and 23 is formed to be bent at a right angle to the other gate line 23 above the drain contactor 27. Further, one gate wiring 22 is formed to be bent at a right angle along the other gate wiring 23 extending vertically above the drain contactor 27.

The other gate wiring 23 is formed to be bent at a right angle toward one gate wiring 22 below the drain contactor 27. Further, the other gate wiring 23 is formed to be bent at a right angle along one gate wiring 22 extending vertically below the drain contactor 27.

That is, the two gate wirings 22 and 23 formed by being bent at right angles twice each are arranged so as to surround the drain contactor 27. Then, the distance between the two gate wirings 22 and 23, the two gate wirings 22 and 23
The distance between the drain contactor 27 and the drain contactor 27 is set to a minimum distance that satisfies a preset design rule. Therefore, the junction area of the drain 24, which is a region sandwiched between the gate wirings 22 and 23, is minimized, and the drain capacitance is smaller than that of the conventional transistor 11.

Further, since both gate wirings 22 and 23 are formed by bending twice, respectively, both gate wirings 2 and 23 are formed.
The effective gate width of each of the transistors 2 and 23 is longer than the vertical length of the transistor 21 in FIG. Therefore, when the transistor 21 of the present embodiment is formed to have the same length in the vertical direction as the conventional transistor 11 shown in FIG. 6, the effective gate length due to both gate wirings 22 and 23 is longer than that of the conventional transistor 11. Conversely, when the effective gate length is the same, the transistor 2 of the present embodiment
1 is smaller vertically than the conventional transistor 11.

That is, in the transistor 21, the source contactors 28 and 29 are formed in the direction in which the wirings 31 to 33 are formed by forming the drain / source wirings 31 to 33 orthogonally to the gate wirings 22 and 23.
7 and the occupied area can be reduced. Also,
By arranging the gate wirings 22 and 23 bent twice to surround the drain contactor 27, the drain 2
The junction area of No. 4 is reduced, and the drain capacitance is reduced.
Further, by forming the gate wirings 22 and 23 by bending twice, the gate wirings 22 and 23 become longer, the effective channel width becomes larger, and the on-resistance of the transistor 21 becomes lower.

In the conventional transistor 11 shown in FIG. 6, the gate wiring 12 is bent four times to reduce the area of the drain by dividing the space between the divided gate wirings 12 above and below the drain contactor 15. The layout can be considered. Also in this case, the area occupied by the transistor and the area of the drain can be reduced, and the effective wiring width is increased due to the longer gate wiring 12.

However, since the corners of the bent gate wiring 12 do not act as gates (channels), the effective channel width is not so much larger than the length of the gate wirings 22 and 23 compared to this embodiment. .
Therefore, when the gate wiring 12 bent four times and the gate wirings 22 and 23 bent twice in the present embodiment are formed to have the same length, the effective channel width is larger and the on-resistance is lower in the present embodiment. It is suitable for speeding up.

For example, in the transistor 21 having the layout shown in FIG. 1, the sources 25, 26 and the drain 24 are formed as N-type diffusion regions (regions in which antimony or the like is diffused), so as to be as shown in FIG. N-channel MOS transistors TN1, T having drain D connected to
It is equivalent to N2. Therefore, both transistors TN1, T
By connecting the gate G and the source S of N2, that is, connecting the gate wirings 22 and 23 and connecting the source wirings 32 and 33 together in FIG. 1, the transistors TN1 and TN2 are connected in parallel to form a transistor. 21.

In the transistor 21 having the layout shown in FIG. 1, the sources 25 and 26 and the drain 24
By making it a type diffusion region (a region where boron or the like is diffused), it becomes equivalent to two P-channel MOS transistors TP1 and TP2 to which the drain D is connected as shown in FIG. Therefore, the gate G and the source S of both transistors TP1 and TP2 are connected to each other, that is, FIG.
By connecting the gate lines 22 and 23 to each other and connecting the source lines 32 and 33 to each other, the transistors TP1 and TP2 are connected in parallel to form the transistor 21.

The transistor configured as above is
For example, it is used as an output transistor. As shown in FIG. 3, the output circuit (transistor array) 41 of the semiconductor integrated circuit device includes a plurality of transistors 21 arranged and connected in a matrix. Vertical direction (row) in FIG.
Are arranged on the gate wirings 22, 23
The transistors 21 arranged in the horizontal direction (row) in FIG. 3 have common drain / source wirings 31 to 33. In addition, the drain wiring 31 of each row is connected to a wiring 42 and is common, and the source wirings 32 and 33 are connected to a wiring 43 and are common.

With the configuration shown in FIG. 3, it is possible to configure an output circuit having a small on-resistance, operating at high speed, and having a large current capacity. Further, by using the transistor 21 of the present embodiment, the entire area of the output circuit 41 can be reduced as compared with a case where an output circuit is configured by the conventional transistor 11.

In a semiconductor integrated circuit device, the number of output circuits 41 to be mounted increases as the degree of integration increases, and a transistor having a small on-resistance is required.
Since a conventional transistor having a small on-resistance has a large area, the larger the number of output circuits 41, the larger the chip area for forming a semiconductor integrated circuit device. However,
Since the transistor 21 of the present embodiment has a small on-resistance and a small area, the entire area of the output circuit 41 is small. Therefore, by mounting the output circuit 41 including the transistor 21 of the present embodiment, it is possible to suppress an increase in the chip area of the highly integrated semiconductor integrated circuit device, and to reduce an increase in the cost of the semiconductor integrated circuit device. Is done.

As described above, the present embodiment has the following advantages. -Two gate wirings 2 provided in the transistor 21
2 and 23, the drain wiring 31 and the source wiring 3
2 and 33 are formed along a direction orthogonal to the gate wirings 22 and 23. As a result, the source contactors 28 and 29 connecting the source wirings 32 and 33 and the sources 25 and 26 are connected to the drain contactor 2 in the formation direction of the wirings 32 and 33.
7, the width of the transistor 21 can be reduced, and the occupied area of the transistor 21 can be reduced.

The two gate wirings 22 and 23 provided in the transistor 21 are formed by bending twice so as to surround the drain contactor 27 and are arranged. Accordingly, the junction area of the drain 24 composed of the region surrounded by the gate wirings 22 and 23 is reduced, and the drain capacitance is reduced. Also, the gate wirings 22 and 23 are
The gate wirings 22 and 2 can be formed by bending the wirings twice.
3, the effective channel width increases, and the on-resistance of the transistor 21 decreases. As a result, when the characteristics of the transistor 21 are almost the same as those in the related art, the area of the transistor 21 can be reduced. In a semiconductor integrated circuit device having an output circuit composed of a plurality of transistors, the area of the output circuit 41 is reduced by reducing the area of each transistor 21, and the chip of the highly integrated semiconductor integrated circuit device is reduced. An increase in area can be suppressed, and an increase in cost can be reduced.

The present invention may be carried out in the following modes in addition to the above embodiment. In the above-described embodiment, a plurality of transistors (contactors) may be formed in the same region along the gate wiring, and may be implemented. That is, the diffusion region is shared by a plurality of transistors. For example, FIG.
As shown in (a), the transistor 51 has a source
Contactors 28, 27, 29 like drain / source
Are repeatedly arranged. Two gate wirings 22 and 2
Reference numeral 3 is arranged so as to surround the drain contactor 27 by bending twice between the source contactors 28 and 29 sandwiching the drain contactor 27. Then, the transistor 51 is constituted by four MOS transistors connected in parallel with the drain 24 being common. According to this configuration, as in the above embodiment, the area of the transistor 51 having a small drain junction area and a low drain capacitance, a large effective channel width, and a small on-resistance can be reduced.

As shown in FIG. 4B, the transistor 52 has a source / drain / source / drain /
Contactors 29, 27, 28, 27, 2 like sources
9 are repeatedly arranged. Two gate wirings 22,
The reference numeral 23 is arranged so as to surround the drain contactor 27 by being bent twice between the source contactors 28 and 29 sandwiching the drain contactor 27. Then, the transistor 52 is connected in parallel with the common drain 24.
It is composed of MOS transistors. With this configuration as well, the area of the transistor 52 having a small drain junction area and a low drain capacitance, a large effective channel width and a small on-resistance can be reduced similarly to the above embodiment. Further, by arranging the contactors 27 to 29 in this manner, the area can be reduced as compared with the transistor 51 of FIG.

Further, the transistors 51 and 52 may be formed in a plurality of rows along the drain wiring 31 and the source wirings 32 and 33 in the same region (the same diffusion layer).
For example, as shown in FIG. 5, a transistor array 53 is formed by arranging the transistors 51 shown in FIG. The transistor array 53 has a common source for the plurality of transistors 51 and a common drain region interposed between the gate wirings 22 and 23. That is, the plurality of transistors 51 connected in parallel are arranged without gaps, and the area of the entire transistor array 53 is smaller than that in the conventional case where the same number of transistors 11 are arranged. FIG.
As shown in FIG. 6, the transistor 52 shown in FIG.
The transistor array 54 is configured by arranging the transistor array 54 in the same manner as in the above embodiment. In this case, the transistors 52 are arranged by the same number as the transistors 51 forming the transistor array 53 shown in FIG. The area of each transistor 52 is smaller than that of the transistors 51 forming the transistor array 53 shown in FIG. 5, so that the area of the transistor array 54 is further reduced.

Although a plurality of transistors 51 (52) are shown in FIG. 5 (FIG. 6) in order to make the plurality of transistors 51 (52) clear, the transistors 51 (52) are actually partitioned by dotted lines.
The source of (52) is not distinguished. Therefore, by further narrowing the distance between the gate wirings 22 and 23 sandwiching the source, the width of the transistors 51 and 52 can be narrowed and the overall area can be reduced. And the gate wiring 2
The area of the source is reduced by reducing the widths of 2, 23. Therefore, the source and the drain may be switched, that is, the signal supplied via the wiring 31 and the signal supplied via the wirings 32 and 33 shown in FIGS. Similarly, a transistor having a small drain requirement can be formed.

In the above embodiment, the drain wiring 31 and the source wirings 32 and 33 are formed in a direction orthogonal to the gate wiring. However, as shown in FIG. , 23 in parallel with each other and connected to each of the contactors 27 to 29
55b and 56a may be formed in a direction orthogonal to the gate wirings 22 and 23. In this case, by connecting both source contactors 28 and 29 to one source wiring 55, the number of source wirings 55 is reduced, and an increase in area is suppressed. As a result, the source line 5
Although the area of the transistor 21 including the drain wiring 5 and the drain wiring 56 is increased, the wiring direction is the same as that of the conventional transistor, so that the conventional transistor 11 can be easily replaced.

In the above embodiment, the output circuit 41 is constituted by using the transistor 21 as an output transistor. However, the embodiment may be implemented by using the transistor 21 in another circuit, for example, a switch circuit.

In the above embodiment, the transistor 21 is formed by connecting the gate G and the source S shown in FIGS. 2A and 2B in common and connecting the transistors TN1 and TN2 (TP1, TP2) in parallel. Instead of being connected, separate signals may be supplied to the gate G and the source S for operation.

In the above embodiment, the gate wirings 22, 23, the drain wiring 31, and the source wirings 32, 33 of the plurality of transistors 21 shown in FIG. 3 are commonly connected, but at least one of them is commonly connected. May be.

[0048]

As described in detail above, according to the first to sixth aspects of the present invention, a semiconductor device having a small area suitable for high-speed operation can be provided.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a MOS transistor according to an embodiment.

FIGS. 2A and 2B are equivalent circuit diagrams of a MOS transistor.

FIG. 3 is a layout diagram of an output circuit using MOS transistors.

4A and 4B are layout diagrams of another MOS transistor.

FIG. 5 is a layout diagram in which a plurality of MOS transistors of FIG. 4A are arranged.

FIG. 6 is a layout diagram in which a plurality of MOS transistors of FIG. 4B are arranged.

FIG. 7 is a layout diagram of another MOS transistor.

FIG. 8 is a layout diagram of a conventional MOS transistor.

[Explanation of symbols]

 22, 23 Gate wiring 24 Drain 25, 26 Source 27 Drain contactor 28, 29 Source contactor 31 Drain wiring 32, 33 Source wiring

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78

Claims (6)

[Claims] 1. A semiconductor device comprising: a gate wiring divided into two parts; a region sandwiched between gate lines arranged in parallel as a drain; a region opposite to the drain with respect to the gate wiring as a source; , A source contactor for supplying a signal to the drain, and a drain contactor for forming a signal, wherein the contactor is arranged along the gate wiring in the order of a source contactor, a drain contactor, and a source contactor; A source line and a drain line connected to each of the contactors and supplying a signal to a source and a drain are formed in a direction perpendicular to the gate line, and the source line and the source line are formed in a direction perpendicular to the gate line. Place the contactor close to the drain contactor, A semiconductor device in which contactors formed on both sides of the gate wiring are bent twice to surround the drain contactor. 2. A semiconductor device comprising: a gate wiring divided into two parts; a region between the gate wirings arranged in parallel as a drain; a region opposite to the drain with respect to the gate wiring as a source; , A source contactor for supplying a signal to the drain, and a drain contactor for forming a signal, wherein the contactor is arranged along the gate wiring in the order of a source contactor, a drain contactor, and a source contactor; A source line for supplying a signal to the source and a drain line for supplying a signal to the drain are formed along the gate line, and the source and drain lines are connected to the contactors. The wiring is formed orthogonal to the gate wiring, and the wiring is formed in the formation direction of the connection wiring. Over a scan contactor located close to the drain contactor, the semiconductor device arranged twice bent so as to surround the drain contactor between the contactor formed the gate wiring on both sides of each said gate line. 3. The semiconductor device according to claim 1, wherein a plurality of said contactors are provided, and said plurality of source contactors and said drain contactors are alternately arranged along said gate wiring. 4. The semiconductor device according to claim 1, wherein a plurality of said contactors are provided, and said plurality of source contactors and drain contactors are arranged along said gate wiring. A semiconductor device in which pairs are repeatedly arranged. 5. A semiconductor device comprising a plurality of transistors each comprising the semiconductor device according to claim 1, formed in the same region along a direction in which a wiring connected to the contactor is formed. 6. A gate wiring divided into two and arranged in parallel, one of the regions divided by each of said gates as a source, the other as a drain, and a signal applied to said drain and source. A drain contactor and a source contactor for supplying are respectively formed, and the contactors are alternately arranged along the gate wiring. The contactor is formed in a layer above the gate wiring, and is connected to each of the contactors to form a drain and a source. A wiring for supplying a signal is formed along a direction orthogonal to the gate wiring, and the drain contactor is arranged closer to the source contactor in the wiring forming direction, and the gate wirings are formed on both sides of the gate wiring, respectively. A transformer arranged so as to surround the source contactor by being bent twice between the set contactors A semiconductor device in which a plurality of stars are formed adjacent to each other along a forming direction of a wiring connected to the contactor.