JPH10322904A - Power supply control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of latching-up so as to be capable of applying power supply voltage at the same timing as ICs. SOLUTION: A P-channel MOS transistor 4 is connected to a 5-V voltage supply connection terminal 1, and the P-channel MOS transistor 4 is kept OFF until the voltage of a 3.3-V voltage supply connection terminal 2 has risen, so that no 5-V voltage is applied to the power supply terminals of CMOS IC7 and CMOS IC8. When the voltage of the 3.3-V voltage supply connection terminal 2 rises, 3.3-V voltage is applied to the power supply terminals of CMOS IC9 and CMOS IC10. At the same time, 3.3-V is applied to the base of an N- channel bipolar transistor 6, so that the N-channel bipolar transistor 6 is turned on, and 5-V voltage is applied to the power supply terminals of the CMOS IC7 and CMOS IC8. Therefore, at the same time, a power supply voltage is applied to the power supply terminals of CMOS IC7, CMOS IC8, CMOS IC9, and CMOS IC10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a power supply control circuit for controlling a power-on sequence of electronic equipment having a plurality of power supply voltages.

[0002]

2. Description of the Related Art As disclosed in JP-A-7-284227, in a power supply circuit having two power supplies, a power supply A and a power supply B, a power supply B is used.
Is a power supply device that has a power-on sequence so that it always starts up after the power supply A.

[0003]

In recent devices, a large amount of CMOS ICs and LSIs are used to reduce power consumption. In CMOS ICs and LSIs, when a power supply voltage is applied after an input voltage is applied first, a parasitic thyristor is formed inside the IC and the LSI, and a large current flows, causing a phenomenon called latch-up that destroys the IC and the LSI itself. It is necessary to apply an input voltage from. The power supply voltage of ICs and LSIs is not only 5V, but also 3.3V to reduce power consumption. In this way, two power supplies are provided, and C
In devices using MOS ICs and LSIs, CMOS I
In order to prevent latch-up of C and LSI, the power-on sequence is controlled as shown in the prior art.

Normally, the output voltage of a 5V system IC or LSI is 5V.
Since the voltage is V and does not satisfy the input voltage standard of the 3.3 V element, a 3.3 V IC or LSI is driven through a voltage level conversion element such as LVTTL which does not cause latch-up. Therefore, even if a power supply voltage is applied to a 5V-system IC or LSI and an output signal is output, the signal is cut off at the level conversion element portion. Therefore, latch-up can be prevented by turning on the power supply in the order of 5V → 3.3V. . But recent 5V I
Some C and LSIs have a voltage drop circuit in the output circuit and can directly drive 3.3 V ICs and LSIs. Since an apparatus using such an IC or LSI does not have a level conversion element, if there is a time difference in the order of turning on the power of 5 V and 3.3 V, the input voltage applied to the CMOS IC and the power supply voltage will be as follows. The order of voltage application may be reversed and latch-up may occur.

A voltage is applied to a 5V CMOS IC.

[0006] → An output signal is output from the 5V CMOS IC and input to the 3.3V CMOS IC. (3.3
The power supply voltage of V has not been applied yet. → In this state, a power supply voltage of 3.3 V is applied.

[0007] → 3.3V CMOS IC latch-up occurs.

As a countermeasure, a power supply capable of simultaneously applying a power supply voltage of 5 V and 3.3 V may be used, but it is difficult to manufacture such a power supply for the following reasons.

Conventional example As described in JP-A-7-2842, the power supply A and the power supply B are generated from the primary coil, but the generation circuits are independent circuits. Therefore, in order to simultaneously raise the power supply voltages of the power supply A and the power supply B, it is necessary to monitor the voltages of the power supply A and the power supply B and supply power to the load when both the power supply A and the power supply B rise. Circuit must be provided, and the number of components is large and the cost is high.

[0010]

SUMMARY OF THE INVENTION A circuit for simultaneously applying a power supply voltage to an electronic device is provided so that 3.3V and 5V I
The power supply voltage is applied to C at the same timing to prevent latch-up.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. The 5V voltage source connection terminal 1 is connected to the resistor 3 and the source of the P-channel MOS transistor 4.
The gate of the P-channel MOS transistor 4 is connected to the resistor 3 and the N
It is connected to the collector of the channel bipolar transistor 6.

The drain of the P-channel MOS transistor 4 is connected to the power supply terminals of the CMOS IC 7 and the CMOS IC 8. The base of N-channel bipolar transistor 6 is connected to resistor 5. The emitter of the N-channel bipolar transistor 6 is connected to the ground.

The 3.3V voltage source connection terminal 2 is connected to the resistor 5 and the CM.
The power supply terminals of the OS IC 9 and the CMOS IC 10 are connected. The output terminal of the CMOS IC 7 is a CMOS I
It is connected to the input terminal of C10. CMOS IC9
Are connected to the input terminals of the CMOS IC8. Next, the operation of the present invention will be described.

When the power of the apparatus is turned on, the voltage of the 5V voltage source connection terminal 1 rises, and then the voltage of the 3.3V voltage source connection terminal 2 rises. Here, the P-channel MOS transistor 4 is connected to the 5V voltage source connection terminal 1 and the P-channel MOS transistor 4 is turned off until the voltage of the 3.3V voltage source connection terminal 2 rises.
The voltage 5 is applied to the power supply terminals of the OS IC 7 and the CMOS IC 8.
V is not applied.

Next, when the voltage of the 3.3V voltage source connection terminal 2 rises, the power supply terminal of the CMOS IC 9 and the CMOS IC 9
A voltage of 3.3 V is applied to the power supply terminal of the power supply 10. At the same time N
The base of the channel bipolar transistor 6 is also 3.3
Since V is applied, the N-channel bipolar transistor 6 is turned on and the P-channel MOS transistor 4 is turned on. When the P-channel MOS transistor 4 is turned on, C
A voltage of 5 V is applied to the power supply terminal of the MOS IC 7 and the power supply terminal of the CMOS IC 8.

Therefore, a CMOS to which a power supply of 5 V is applied
A power supply voltage is simultaneously applied to the power supply terminals of the IC 7, the CMOS IC 8, and the CMOS IC 9 and the CMOS IC 10 to which the 3.3 V power is applied. Therefore, the output signal of the CMOS IC 7 to which the power of 5 V is applied drives the input of the CMOS IC 10 to which the power of 3.3 V is applied, and the output signal of the CMOS IC 8 to which the power of 3.3 V is applied is 5 V. Even when the input of the CMOS IC 10 to which power is applied is driven, the order in which the input voltage and the power supply voltage are applied is reversed and latch-up does not occur.

FIG. 2 shows another embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 are denoted by the same reference numerals as those in FIG. 1 and will not be described. 5V voltage source connection terminal 1 is diode 1
1 and the power supply terminals of CMOS IC7 and CMOS IC8. The anode of the diode 11 is connected to the power supply terminals of the CMOS IC 9 and the CMOS IC 10.

Next, the operation of the present invention will be described.

When the power of the apparatus is turned on, the voltage of the 3.3V voltage source connection terminal 2 rises, and then the voltage of the 5V voltage source connection terminal 1 rises. 3.3V power supply rises 5
When the power supply of V is not turned on, 3.3 V is applied to the CMOS IC 9 and the CMOS IC 10 and at the same time, 3.3 V is applied to the power supply terminals of the CMOS IC 7 and the CMOS IC 8 through the diode 11 from the 3.3 V voltage source connection terminal 2.
3V is applied. Next, when the voltage of the 5V voltage source connection terminal 2 rises, the power supply terminal of the CMOS IC 7 and the CMOS
A voltage of 5 V is applied to a power supply terminal of the IC 8.

According to this embodiment, there is an effect that the power supply voltage can be simultaneously applied to the CMOS IC in the device by adding a simple circuit.

FIG. 3 shows another embodiment of the present invention.

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 and 2 have the same configuration functions as those in FIGS. 1 and 2 and will not be described.

Next, the operation of the present invention will be described.

A description will be given of a case where the power supply of 5 V is turned on first in the device having the power supply voltages of 5 V and 3.3 V. The voltage at the 5V voltage source connection terminal 1 rises, and then the voltage at the 3.3V voltage source connection terminal 2 rises. Here, the P-channel MOS transistor 4 is connected to the 5V voltage source connection terminal 1 and the P-channel MOS transistor 4 is turned off until the voltage of the 3.3V voltage source connection terminal 2 rises, so the CMOS IC 7 and the CMOS IC
No voltage of 5 V is applied to the power supply terminal 8. When the voltage of the 3.3V voltage source connection terminal 2 rises, the CMOS I
A voltage of 3.3 V is applied to the power supply terminal of C9 and the power supply terminal of CMOS IC 10. At the same time, 3.3 V is also applied to the base of N-channel bipolar transistor 6, so that N
The channel bipolar transistor 6 is turned on, and the P-channel MOS transistor 4 is turned on. P channel MO
When the S transistor 4 is turned on, a voltage of 5 V is applied to the power supply terminal of the CMOS IC 7 and the power supply terminal of the MOS IC 8.

Therefore, a CMOS to which a power supply of 5 V is applied
A voltage is simultaneously applied to the power supply terminals of the IC 7, the CMOS IC 8, and the CMOS IC 9 and the CMOS IC 10 to which the power of 3.3V is applied.

Next, a description will be given of a case where the power supply of 3.3 V is turned on first in the apparatus having the power supply voltages of 5 V and 3.3 V. When the power of the device is turned on, 3.3V voltage source connection terminal 2
Then, the voltage of the 5V voltage source connection terminal 1 rises. When the 3.3V power supply rises and the 5V power supply does not rise, CMOS IC9 and CMOS
At the same time that 3.3 V is applied to the IC 10, the 3.3 V voltage source connection terminal 2 connects the CMOS through the diode 11.
3.3V is applied to the power supply terminals of IC7 and CMOS IC8. Next, when the voltage of the 5 V voltage source connection terminal 2 rises, a voltage of 5 V is applied to the power supply terminal of the CMOS IC 7 and the power supply terminal of the CMOS IC 8.

According to the present embodiment, in a power supply circuit having two power supplies, a power supply A and a power supply B, a power supply voltage can be simultaneously applied to the CMOS IC in the device regardless of the power-on sequence. Further, the unit using this embodiment can be used regardless of the order in which the power of the main unit is turned on, so that the unit can be standardized.

[0029]

According to the present invention, in a device having a plurality of power supplies, the occurrence of latch-up can be prevented only by adding a simple circuit, so that the reliability of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a power supply control circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a power supply control circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a power supply control circuit according to a third embodiment of the present invention.

[Explanation of symbols]

1. 5 V voltage source connection terminal, 2 3.3 V voltage source connection terminal, 3 resistor, 4 P channel MOS transistor,
5: resistor, 6: N-channel bipolar transistor, 7: CMOS IC, 8: CMOS I
C, 9 ... CMOS IC, 10 ... CMOS IC,
11 ... Diode.

Claims (3)

[Claims] In a device having a plurality of power supply lines, a switching element is provided on a power supply line that rises first, and a power supply detection circuit that detects a rise of power supply of a power supply line that rises lastly is provided. A power supply control circuit characterized by detecting and turning on a switching element. 2. An apparatus having a plurality of power supply lines, wherein an anode of a diode is connected to a power supply line which rises first and has a low power supply voltage, and a power supply line which rises later and has a high power supply voltage is connected to a cathode of the diode. Power control circuit. 3. An apparatus having a plurality of power supply lines, comprising a switching element on a power supply line with a high voltage, a power supply detection circuit for detecting a rise of a power supply on a power supply line with a low voltage, and detecting a power supply voltage rising last. A power supply control circuit comprising: detecting and turning on a switching element; connecting an anode of a diode to a power supply line having a low power supply voltage; and connecting a power supply line having a high power supply voltage to a cathode of the diode.