JP2009105721A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid an occurrence of a latch-up phenomenon even in the case of VSS1>VSS2, when input voltages VDD1 and VSS1 under VDD2>VSS2>VSS1 and VDD1>VSS1 are input and the levels are shifted to VDD2 and VSS2. <P>SOLUTION: A level shift circuit has a latch circuit 3 composed of two inverters subjected to back-to-back connection between a node N1 and a node N2 which become a signal output terminal OUT and operating on voltages VDD2 and VSS2, a first inverter 1 connected between a signal input terminal IN and a node N3 and operating on voltages VDD1 and VSS1, a second inverter 2 connected between the node N3 and a node N4 and operating on the voltages VDD1 and VSS1, a first inverse driving circuit 4 connected to the nodes N1, N2, and N3, a second inverse driving circuit 5 connected to the nodes N1, N2, and N4, and a diode D1 using a terminal side of the voltage VSS1 for anode and a terminal side of the voltage VSS2 for cathode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a level shift circuit that converts a voltage level of an input signal and outputs the converted signal.

  FIG. 6 is a circuit diagram showing a configuration of a conventional level shift circuit (see, for example, Patent Document 1). In the following description, the PMOS transistor is represented by “MP *” and the NMOS transistor is represented by “MN *”. “*” Is a number.

  Reference numeral 1 denotes a first inverter composed of transistors MP9 and MN5, and reference numeral 2 denotes a second inverter composed of transistors MP10 and MN6. Reference numeral 3 denotes a first latch circuit. Between the nodes N1 and N2, an inverter composed of transistors MP7 and MN3 and an inverter composed of transistors MP8 and MN4 are reversed so that one input side is connected to the other output side. It is configured by connecting in parallel.

  4 is a first inversion drive for inverting the voltages of the nodes N1 and N2 (the node N1 is inverted from VDD2 to VSS2 and the node N2 is inverted from VSS2 to VDD2) when the voltage of the node N3 is inverted from VSS1 to VDD1. The circuit is composed of transistors MN1, MP1, MP3, and MP5. The conduction resistances of the transistors MN1 and MP1 are set smaller than the conduction resistances of the transistors MP3 and MP5.

  5 is a second inversion drive for inverting the voltages of the nodes N1 and N2 (the node N1 is inverted from VSS2 to VDD2 and the node N2 is inverted from VDD2 to VSS2) when the voltage of the node N4 is inverted from VSS1 to VDD1. This circuit is composed of transistors MN2, MP2, MP4, and MP6. Note that the conduction resistances of the transistors MN2 and MP2 are set smaller than the conduction resistances of the transistors MP4 and MP6. The signal input terminal IN is connected to the input side of the first inverter 1, and the signal output terminal OUT is connected to the node N1. Each power supply voltage has a relationship of VDD2> VSS2> VSS1 and VDD1> VSS1.

  Now, when the voltage of the signal input terminal IN is VDD1, the voltage of the node N3 is VSS1, and the voltage of the node N4 is VDD1. The voltage at the node N1 is VDD2, and the voltage at the node N2 is VSS2.

  In this state, when the voltage at the signal input terminal IN changes from VDD1 to VSS1, the operation is as follows. First, the transistor MN1 is turned on when the voltage at the node N3 changes from VSS1 to VDD1, and the transistor MN2 is cut off when the voltage at the node N4 changes from VDD1 to VSS1. When the transistor MN1 is turned on, the node N5 has a low impedance with respect to the terminal of the voltage VSS1, so that the source of the transistor MP1, that is, the voltage of the node N1 is changed from VDD2 to "VSS2 + Vth1" ) Voltage. As a result, the inverter composed of the transistors MP8 and MN4 of the latch circuit 3 is driven, and the voltage at the node N2 changes to VDD2 and the voltage at the node N1 changes to VSS2.

  At the time of this transition, for the transistors MP4 and MP6 on the second inverting drive circuit 5 side, the transistor MP4 shifts from the cut-off state to the conductive state, and the transistor MP6 shifts from the conductive state to the cut-off state. Since the timing of the transition from the state to the conductive state is slightly earlier, the impedance of the node N2 is temporarily lowered relative to the terminal of the voltage VDD2, and the time for the voltage of the node N2 to transition from VSS2 to VDD2 is shortened and inverted. Speed up the operation.

  At this time, for the transistors MP3 and MP5 on the first inverting drive circuit 4 side, the transistor MP5 first changes from the cutoff state to the conduction state, and then the transistor MP3 changes from the conduction state to the cutoff state. At this time, since the transistors MN1 and MP1 are turned on first, and the conduction resistance is set smaller than those of the transistors MP3 and MP5, the lift amount of the node N1 in the direction of the voltage VDD2 is small. The operation of inverting the node N1 to the voltage VSS2 is not affected.

  Next, when the voltage at the signal input terminal IN changes from VSS1 to VDD1, the voltage at the node N3 changes from VDD1 to VSS1, so that the transistor MN1 is cut off, and the voltage at the node N4 changes from VSS1 to VDD1. As a result, the transistor MN2 becomes conductive. When the transistor MN2 is turned on, the node N6 has a low impedance with respect to the terminal of the voltage VSS1, so that the source of the transistor MP2, that is, the voltage of the node N2, is changed from VDD2 to “VSS2 + Vth2” (Vth2 is the threshold voltage of the transistor MP2). ) Voltage. As a result, the inverter composed of the transistors MP7 and MN3 of the latch circuit 3 is driven, the voltage at the node N1 changes to VDD2 and the voltage at the node N2 changes to VSS2, and is inverted.

  At the time of this transition, for the transistors MP3 and MP5 on the first inversion driving circuit 4 side, the transistor MP3 shifts from the cut-off state to the conductive state, and the transistor MP5 shifts from the conductive state to the cut-off state. Since the timing of the transition from the state to the conductive state is slightly earlier, the impedance of the node N1 is temporarily lowered relative to the terminal of the voltage VDD2, the time for the voltage of the node N1 to transition from VSS2 to VDD2 is shortened, and inversion Speed up the operation.

  At this time, for the transistors MP4 and MP6 on the second inverting drive circuit 5 side, the transistor MP6 first changes from the cutoff state to the conduction state, and then the transistor MP4 changes from the conduction state to the cutoff state. At this time, the transistors MN2 and MP2 are turned on first, and the conduction resistance is set to be smaller than those of the transistors MP4 and MP6. Therefore, the lift amount of the node N2 in the direction of the voltage VDD2 is very small. The operation of inverting the node N2 to the voltage VSS2 is not affected.

As described above, according to the level shift circuit of FIG. 6, it is possible to obtain the output signal level-shifted to VDD2 and VSS2 by inputting the voltages VDD1 and VSS1. Further, at the time of transition, the impedance between the node N1 or N2 transitioning in the VDD2 direction and the terminal side of VDD2 is temporarily reduced, so that the switching speed can be increased. Furthermore, the entire circuit can be composed of only PMOS and NMOS transistors.
JP 2005-150989 A

  However, in this level shift circuit, as described above, VSS2> VSS1, but for some reason, when this is inverted and VSS1> VSS2, a parasitic PNP transistor formed in the CMOS circuit portion. As a result, a trigger current flows through a parasitic thyristor composed of an NPN transistor, and a latch-up phenomenon that causes the parasitic thyristor to conduct occurs, and an excessive current may flow to cause element destruction.

  FIG. 7 is a cross-sectional view of a main part for explaining this. FIG. 7A is an explanatory diagram when the transistor MN3 is conductive (node N1 = VSS2). The transistor MN5 is formed directly on the P-type impurity low-concentration substrate 11, and the transistor MP9 is an island in the N-type impurity low-concentration region. 12, the transistor MP1 is formed in the island 14 of the N-type impurity low concentration region in the island 13 of the N-type impurity high concentration region, and the transistor MN3 is P-type in the island 15 of the N-type impurity high concentration region. The impurity is formed in the island 16 in the low concentration region. The PNP transistor Q1 and the NPN transistor Q2 are parasitic transistors that constitute a parasitic thyristor, and R1, R2, and R3 are parasitic resistances.

  FIG. 7B is an explanatory diagram when the transistor MN4 is turned on (node N2 = VSS2). The transistor MN6 is formed directly on the P-type impurity low-concentration substrate 11, and the transistor MP10 is an island in the N-type impurity low-concentration region. 17 is formed in the island 19 of the N-type impurity low concentration region in the island 18 of the N-type impurity high concentration region, and the transistor MN4 is P-type in the island 20 of the N-type impurity high concentration region. The impurity is formed in the island 21 in the low concentration region. The PNP transistor Q3 and the NPN transistor Q4 are parasitic transistors that constitute a parasitic thyristor, and R4, R5, and R6 are parasitic resistors.

In FIG. 7A, when VSS1> (VSS2 + _VBEQ2 ) ( _VBEQ2 is the base-emitter voltage of the transistor Q2), the route is VSS1 → R2 → base / emitter of Q2 → N1 → MN3 → VSS2. A trigger current I_trigger flows, whereby the transistor Q2 is turned on and a base current flows through the transistor Q1. Therefore, a large current between VDD1 → VSS2 via the resistor R1 and the transistor Q2, a large current between VDD1 → VSS1, and a large current between the VDD1 → VSS1 via the transistor Q1 and the resistor R3 flow, respectively. Will occur.

Also in FIG. 7B, when VSS1> (VSS2 + _VBEQ4 ) ( _VBEQ4 is the voltage between the base and emitter of the transistor Q4), the route is VSS1 → R5 → base / emitter of Q4 → N2 → MN4 → VSS2. A trigger current I_trigger flows, whereby the transistor Q4 is turned on and a base current flows through the transistor Q3. Therefore, a large current between VDD1 and VSS2 passing through the resistor R4 and the transistor Q4, a large current between VDD1 and VSS1, and a large current between VDD1 and VSS1 passing through the transistor Q3 and the resistor R6 flow, respectively. Will occur.

  An object of the present invention is to provide a level shift circuit in which a latch-up phenomenon does not occur even when the relationship between the levels of the power supply voltage collapses from a predetermined relationship as described above.

In order to achieve the above object, a level shift circuit according to a first aspect of the present invention comprises two inverters connected in reverse parallel between a first node serving as a signal output terminal and a second node, and a voltage A latch circuit operating at VDD2 and VSS2, a first inverter connected at the input side to the signal input terminal and connected at the output side to the third node and operating at voltages VDD1 and VSS1, and an input side connected to the third node A second inverter whose output side is connected to the fourth node and operating at voltages VDD1 and VSS1, and a first inverter connected to the first, second and third nodes and operating at voltages VDD2, VSS2 and VSS1. And a second inverting drive circuit connected to the first, second and fourth nodes and operating at voltages VDD2, VSS2 and VSS1. In the level shift circuit, the first inversion driving circuit includes a first NMOS transistor having a source connected to the terminal of the voltage VSS1, a gate connected to the third node, and a drain connected to the fifth node. A first PMOS transistor having a gate connected to the terminal of the voltage VSS2, a drain connected to the fifth node and a source connected to the first node, and a gate and a drain connected to the first node. A fifth PMOS transistor having a source connected to the seventh node, a drain connected to the seventh node, a gate connected to the second node, and a source connected to the terminal of the voltage VDD2. The second inversion driving circuit has a source connected to the terminal of the voltage VSS1 and a gate connected to the front of the second inversion driving circuit. A second NMOS transistor connected to the fourth node and having a drain connected to the sixth node; a gate connected to a terminal of the voltage VSS2, a drain connected to the sixth node, and a source connected to the second node; A second PMOS transistor connected to the node; a sixth PMOS transistor having a gate and drain connected to the second node and a source connected to the eighth node; and a drain connected to the eighth node. And a fourth PMOS transistor having a gate connected to the first node and a source connected to the terminal of the voltage VDD2, and the voltage VSS2 between the terminal of the voltage VSS2 and the terminal of the voltage VSS1. The first diode is connected such that the first terminal is the cathode and the first VSS1 terminal is the anode. It is a sign.
A level shift circuit according to a second aspect of the present invention is a latch circuit comprising two inverters connected in antiparallel between an eleventh node and a twelfth node as signal output terminals and operating at voltages VDD1 and VSS1. A third inverter whose input side is connected to the signal input terminal and whose output side is connected to the thirteenth node and operates at voltages VDD2 and VSS2, and whose input side is connected to the thirteenth node and whose output side is the fourteenth node. A fourth inverter connected and operating at voltages VDD2 and VSS2, a third inversion driving circuit connected to the eleventh, twelfth and thirteenth nodes and operating at voltages VDD2, VDD1 and VSS1, and And a fourth inversion drive circuit connected to the eleventh, twelfth and fourteenth nodes and operating at voltages VDD2, VDD1 and VSS1. In the bell shift circuit, the third inversion driving circuit includes an eleventh PMOS transistor having a source connected to the terminal of the voltage VDD2, a gate connected to the thirteenth node, and a drain connected to the fifteenth node; An eleventh NMOS transistor having a gate connected to the terminal of the voltage VDD1, a drain connected to the fifteenth node and a source connected to the eleventh node, and a gate and a drain connected to the eleventh node. A fifteenth NMOS transistor having a source connected to the seventeenth node; a thirteenth drain having a drain connected to the seventeenth node; a gate connected to the twelfth node; and a source connected to the terminal of the voltage VSS1. The fourth inversion driving circuit has a source whose end is the voltage VDD2 A twelfth PMOS transistor having a gate connected to the fourteenth node and a drain connected to the sixteenth node, a gate connected to the terminal of the voltage VDD1, and a drain connected to the sixteenth node. A twelfth NMOS transistor having a source connected to the twelfth node; a sixteenth NMOS transistor having a gate and drain connected to the twelfth node and a source connected to the eighteenth node; A fourteenth NMOS transistor having a gate connected to the eleventh node, a gate connected to the eleventh node, and a source connected to the terminal of the voltage VSS1, and a terminal of the voltage VDD2 and a terminal of the voltage VDD1; In between, the terminal of the voltage VDD2 becomes the cathode and the terminal of the VDD1 becomes the anode. And a second diode is connected.

According to the level shift circuit of the first aspect of the present invention, when the voltages are VDD2>VSS2> VSS1 and VDD1> VSS1, the voltages VDD1 and VSS1 are input and the voltages VDD2 and VSS2 are output. In addition, even when the voltages VSS1 and VSS2 are inverted from the normal voltage relationship VSS2> VSS1 and VSS1> VSS2 is satisfied, the bypass path is formed by the first diode. Supply of a trigger current to a parasitic thyristor formed of a parasitic NPN transistor is avoided, and occurrence of latch-up can be avoided.
According to the level shift circuit of the second aspect of the invention, when the voltages are in the relationship of VDD2>VDD1> VSS1 and VDD2> VSS2, the voltages VDD1 and VDD2 are inverted from the normal voltage relationship VDD2> VDD1, and VDD1 Even if> VDD2, the bypass path is formed by the second diode, so that a trigger current is prevented from being supplied to the parasitic thyristor formed by the parasitic PNP transistor and the parasitic NPN transistor. Up occurrence can be avoided. Contrary to the first aspect of the invention, the voltages VDD2 and VSS2 can be inputted and the voltages VDD1 and VSS1 can be outputted.

<Example 1>
FIG. 1 is a circuit diagram showing the configuration of the level shift circuit according to the first embodiment. In the conventional level shift circuit shown in FIG. 6, the first diode D1 is placed between the voltage VSS1 terminal and the voltage VSS2 terminal so that the terminal side of the voltage VSS1 is an anode and the terminal side of the voltage VSS2 is a cathode. The connection is different.

  FIG. 2A is a diagram showing a cross section of the first diode D1. The diode D1 is directly formed on the substrate 11 having a low concentration of P-type impurities. When VSS1> VSS2, the diode D1 is turned on to form a bypass path between the voltage VSS1 terminal and the voltage VSS2 terminal, so that a trigger current is supplied to the parasitic PNP transistor Q1 and the NPN transistor Q2. The parasitic thyristor composed of the transistors Q1 and Q2 is prevented from turning on.

  FIG. 2B is a cross-sectional view of another example of the first diode D1. In the diode D1, an island 22 of a high N-type impurity concentration region is formed in a substrate 11 having a low P-type impurity concentration, and an island 23 of a P-type impurity low concentration region is formed in the region 22, and the island 23 The NPN transistor Q5 is formed in this, and this transistor Q5 is diode-connected.

  As described above, in the level shift circuit according to the first embodiment, when the original power supply voltage should be used in the relationship of VDD2> VSS2> VSS1 and VDD1> VSS1, VSS1> VSS2 for some reason. Even if a situation occurs, a bypass path is formed in advance between the voltage VSS1 terminal and the voltage VSS2 terminal by the diode D1, so that a trigger current is supplied to the parasitic PNP transistor and NPN transistor. However, it is avoided that the parasitic thyristor including these parasitic transistors is turned on, and the occurrence of the latch-up phenomenon is avoided.

<Example 2>
FIG. 3 is a circuit diagram showing the configuration of the level shift circuit of the second embodiment. In this level shift circuit, the power supply voltages are VDD2>VDD1> VSS1 and VDD2> VSS2, and are the same as the level shift circuit described in FIG. 1, but the input voltage is VDD2, VSS2, the output voltage is VDD1, It is VSS1, and the circuit configuration is a configuration in which the element polarity is reversed from that of the circuit of FIG. In this embodiment, the second diode D2 is connected between the voltage VDD1 terminal and the voltage VDD2 terminal so that the terminal side of the voltage VDD1 is an anode and the terminal side of the voltage VDD2 is a cathode.

  31 is a third inverter made up of transistors MP15 and MN19, and 32 is a fourth inverter made up of transistors MP16 and MN20. Reference numeral 33 denotes a second latch circuit, which reverses an inverter composed of transistors MP13 and MN17 and an inverter composed of transistors MP14 and MN18 between nodes N11 and N12 so that one input side is connected to the other output side. It is configured by connecting in parallel.

  34 is a third inversion drive for inverting the voltages of the nodes N11 and N12 (the node N11 is inverted from VSS1 to VDD1 and the node N12 is inverted from VDD1 to VSS1) when the voltage of the node N13 is inverted from VDD2 to VSS2. This circuit is composed of transistors MN13, MN15, MN11, and NP11. The conduction resistances of the transistors MN11 and MP11 are set smaller than the conduction resistances of the transistors MN13 and MN15.

  35 is a fourth inversion drive for inverting the voltages of the nodes N11 and N12 (the node N11 is inverted from VDD1 to VSS1 and the node N12 is inverted from VSS1 to VDD1) when the voltage of the node N14 is inverted from VDD2 to VSS2. This circuit is composed of transistors MN14, MN16, MN12, and MP12. The conduction resistances of the transistors MN12 and MP12 are set smaller than the conduction resistances of the transistors MN14 and MN16. The signal input terminal IN is connected to the input side of the third inverter 31, and the signal output terminal OUT is connected to the node N11.

  Now, when the voltage of the signal input terminal IN is VSS2, the voltage of the node N13 is VDD2, and the voltage of the node N14 is VSS2. The voltage at the node N11 is VSS1 and the voltage at the node N12 is VDD1.

  In this state, when the voltage at the signal input terminal IN changes from VSS2 to VDD2, the operation is as follows. First, the transistor MP11 is turned on when the voltage at the node N13 changes from VDD2 to VSS2, and the transistor MP12 is cut off when the voltage at the node N14 changes from VSS2 to VDD2. Since the transistor MP11 becomes conductive, the node N15 has a low impedance with respect to the terminal of the voltage VDD2, so that the source of the transistor MN11, that is, the voltage of the node N11 is changed from VSS1 to “VDD1−Vth11” (Vth11 is the threshold of the transistor MN11). Value voltage). As a result, the inverter comprising the transistors MN18 and MP14 of the latch circuit 13 is driven, and the voltage at the node N12 changes to VSS1 and the voltage at the node N11 changes to VDD1 and is inverted.

  At the time of this transition, for the transistors MN14 and MN16 on the fourth inversion driving circuit 35 side, the transistor MN14 shifts from the cut-off state to the conductive state, and the transistor MN16 shifts from the conductive state to the cut-off state. Since the timing of the transition from the state to the conductive state is slightly earlier, the impedance of the node N12 is temporarily lowered with respect to the terminal of the voltage VSS1, the time for the voltage of the node N12 to transition from VDD1 to VSS1 is shortened, and inversion Speed up the operation.

  At this time, regarding the transistors MN13 and MN15 on the third inverting drive circuit 34 side, the transistor MN15 first changes from the cutoff state to the conduction state, and then the transistor MN13 changes from the conduction state to the cutoff state. At this time, the transistors MP11 and MN11 are turned on first, and the conduction resistance is set to be smaller than that of the transistors MN13 and MN15. Therefore, the amount of the node N11 to be lowered in the voltage VSS1 direction is small. The operation of inverting the node N11 to the voltage VDD1 is not affected.

  Next, when the voltage at the signal input terminal IN changes from VDD2 to VSS2, the voltage at the node N13 changes from VSS2 to VDD2, whereby the transistor MP11 is cut off, and the voltage at the node N4 changes from VDD2 to VSS2. As a result, the transistor MP12 becomes conductive. When the transistor MP12 is turned on, the node N16 has a low impedance with respect to the terminal of the voltage VDD2, so that the source of the transistor MN12, that is, the voltage of the node N12 is changed from VSS1 to “VDD1-Vth12” (Vth12 is the threshold of the transistor MN12). Value voltage). As a result, the inverter comprising the transistors MN17 and MP13 of the latch circuit 33 is driven, and the voltage at the node N11 changes to VSS1 and the voltage at the node N12 changes to VDD1 and is inverted.

  At the time of this transition, for the transistors MN13 and MN15 on the third inverting drive circuit 34 side, the transistor MN13 shifts from the cutoff state to the conduction state, and the transistor MN15 shifts from the conduction state to the cutoff state. Since the timing of the transition from the state to the conductive state is slightly earlier, the impedance of the node N11 is temporarily lowered with respect to the terminal of the voltage VSS1, the time for the voltage of the node N11 to transition from VDD1 to VSS1 is shortened, and inversion Speed up the operation.

  At this time, regarding the transistors MN14 and MN16 on the fourth inversion drive circuit 35 side, the transistor MN16 first changes from the cutoff state to the conduction state, and then the transistor MN14 changes from the conduction state to the cutoff state. At this time, the transistors MP12 and MN12 are turned on first, and the conduction resistance is set to be smaller than that of the transistors MN14 and MN16. Therefore, the amount of voltage VSS1 at the node N12 to be pulled down is small. There is no effect on the operation of inverting the node N12 to the voltage VDD1.

  As described above, according to the level shift circuit of FIG. 3, it is possible to input the voltages VDD2 and VSS2 and obtain an output signal level-shifted to VDD1 and VSS1. Further, at the time of transition, the impedance between the node N11 or N12 transitioning in the VSS1 direction and the VSS1 side is temporarily reduced, so that the switching speed can be increased. Furthermore, the entire circuit can be composed of only PMOS and NMOS transistors.

  However, in the level shift circuit of FIG. 3, when the second diode D2 is not connected and the power supply relationship becomes VDD1> VDD2 for some reason, the parasitic PNP transistor formed in the CMOS circuit portion A trigger current flows through a parasitic thyristor composed of an NPN transistor, causing a latch-up phenomenon that causes the parasitic thyristor to conduct, and an excessive current may flow to cause element destruction.

  FIG. 4 is a cross-sectional view of a main part for explaining this. FIG. 4A is an explanatory diagram when the transistor MP13 is conductive (node N11 = VDD1). The transistor MN17 is formed directly on the P-type impurity low concentration substrate 41, and the transistor MP13 is an island of the N-type impurity low concentration region. The transistor MN11 is formed in the island 44 of the N-type impurity low concentration region in the island 43 of the N-type impurity high concentration region, and the transistor MP11 is formed in the island 45 of the N-type impurity low concentration region. ing. PNP transistors Q11 and Q12 and NPN transistor Q13 are parasitic transistors constituting a parasitic thyristor, R11 and R12 are parasitic resistors, and D21 is a parasitic diode.

  FIG. 4B is an explanatory diagram when the transistor MP14 is turned on (node N12 = VDD1). The transistor MN18 is formed directly on the P-type impurity low-concentration substrate 41, and the transistor MP14 is an island in the N-type impurity low-concentration region. The transistor MN12 is formed in the island 48 of the N-type impurity low concentration region in the island 47 of the N-type impurity high concentration region, and the transistor MP12 is formed in the island 49 of the N-type impurity low concentration region. ing. The PNP transistors Q14 and Q15 and the NPN transistor Q16 are parasitic transistors constituting a parasitic thyristor, R13 and R14 are parasitic resistors, and D22 is a parasitic diode.

In FIG. 4A, when VDD1> (VDD2 + V _D21 + V _BEQ11 ) (V _D21 is the forward voltage of the diode D21, V _BEQ11 is the base-emitter voltage of the transistor Q11), VDD1 → MP13 → D21 → The trigger current I_trigger flows through the route of N15 → Q11 base / emitter → R11 → VDD2, whereby the transistor Q11 becomes conductive and the base current flows through the transistor Q13. Therefore, a large current between VDD2 and VSS1 passing through the resistor R11 and the transistor Q13 and a large current between VDD2 and VSS1 passing through the transistor Q12 and the resistor R12 flow, and a latch-up phenomenon occurs.

Also in FIG. 4B, when VDD1> (VDD2 + V _D22 + V _BEQ14 ) (V _D22 is the forward voltage of the diode D22, V _BEQ14 is the base-emitter voltage of the transistor Q14), VDD1 → MP14 → D22 → The trigger current I_trigger flows in the route of N16 → Q14 base / emitter → R13 → VDD2, whereby the transistor Q14 is turned on and the base current flows in the transistor Q16. Therefore, a large current between VDD2 and VSS1 passing through the resistor R13 and the transistor Q16 and a large current between VDD2 and VSS1 passing through the transistor Q15 and the resistor R14 flow, and a latch-up phenomenon occurs.

  However, in this embodiment, as described above, the second diode D2 is connected between the voltage VDD1 terminal and the voltage VDD2 terminal so that the terminal side of the voltage VDD1 is an anode and the terminal side of the voltage VDD2 is a cathode. Therefore, the occurrence of the latch-up phenomenon can be avoided.

  FIG. 5 is a cross-sectional view of the second diode D2. This diode D2 is formed by forming an island 49 of an N-type impurity high concentration region in a substrate 41 of a low concentration of P-type impurity, and forming an island 50 of an N-type impurity low concentration region in the region 49. Is formed. The diode D2 may be formed directly on the substrate like the diode D1 shown in FIG. 2 (a), or may be formed of a diode-connected transistor like the transistor Q5 shown in FIG. 2 (b). Good.

  As described above, in the level shift circuit according to the second embodiment, when the original power supply voltage should be used in the relationship of VDD2> VDD1> VSS1 and VDD2> VSS2, VDD1> VDD2 for some reason. Even if the situation occurs, a bypass path is formed in advance between the voltage VDD1 terminal and the voltage VDD2 terminal by the diode D2, so that a trigger current is supplied to the parasitic PNP transistor and NPN transistor. However, it is avoided that the parasitic thyristor including these parasitic transistors is turned on, and the occurrence of the latch-up phenomenon is avoided. In the first embodiment, VDD1 and VSS1 cannot be input and level shifted to VDD2 and VSS2. However, in the second embodiment, the level shift can be performed.

It is a circuit diagram of the level shift circuit of Example 1 of the present invention. (a) is sectional drawing of an example of the principal part of the level shift circuit of Example 1, (b) is sectional drawing of another example of the principal part. It is a circuit diagram of the level shift circuit of Example 2 of the present invention. (a), (b) is sectional drawing for description of the latch-up which generate | occur | produces when the diode D2 is removed from the level shift circuit of FIG. FIG. 6 is a cross-sectional view of an example of a main part of a level shift circuit according to a second embodiment. It is a circuit diagram of a conventional level shift circuit. FIG. 7A is a cross-sectional view for explaining the occurrence of latch-up in the level shift circuit of FIG. 6, and FIG. 7B is another cross-sectional view for explaining the occurrence of the latch-up.

Explanation of symbols

1: first inverter, 2: second inverter, 3: first latch circuit, 4: first inversion drive circuit, 5: second inversion drive circuit, 31: third inverter, 32: fourth 33: second latch circuit, 34: third inversion drive circuit, 35: fourth inversion drive circuit

Claims (2)

A latch circuit comprising two inverters connected in antiparallel between a first node and a second node serving as signal output terminals and operating at voltages VDD2 and VSS2;
A first inverter having an input side connected to a signal input terminal and an output side connected to a third node and operating at voltages VDD1 and VSS1,
A second inverter having an input side connected to the third node and an output side connected to a fourth node and operating at voltages VDD1 and VSS1,
A first inverting drive circuit connected to the first, second and third nodes and operating at voltages VDD2, VSS2 and VSS1;
In a level shift circuit comprising a second inverting drive circuit connected to the first, second and fourth nodes and operating at voltages VDD2, VSS2 and VSS1,
The first inversion driving circuit includes a first NMOS transistor having a source connected to the terminal of the voltage VSS1, a gate connected to the third node, and a drain connected to a fifth node, and a gate connected to the voltage VSS. A first PMOS transistor having a drain connected to the VSS2 terminal, a drain connected to the fifth node, and a source connected to the first node, a gate and a drain connected to the first node, and a source connected to the seventh node. A fifth PMOS transistor connected to the second node, a third PMOS transistor having a drain connected to the seventh node, a gate connected to the second node, and a source connected to the terminal of the voltage VDD2. Consists of
The second inversion driving circuit includes a second NMOS transistor having a source connected to the terminal of the voltage VSS1, a gate connected to the fourth node, and a drain connected to a sixth node, and a gate connected to the voltage VSS. A second PMOS transistor having a drain connected to the terminal of VSS2, a drain connected to the sixth node and a source connected to the second node, a gate and a drain connected to the second node, and a source connected to the eighth node. A sixth PMOS transistor connected to the first node, a fourth PMOS transistor having a drain connected to the eighth node, a gate connected to the first node, and a source connected to the terminal of the voltage VDD2. Consists of
A first diode is connected between the terminal of the voltage VSS2 and the terminal of the voltage VSS1 so that the terminal of the voltage VSS2 becomes a cathode and the terminal of the VSS1 becomes an anode.
A level shift circuit characterized by that. A latch circuit composed of two inverters connected in antiparallel between an eleventh node and a twelfth node as signal output terminals and operating at voltages VDD1 and VSS1,
A third inverter whose input side is connected to the signal input terminal and whose output side is connected to the thirteenth node and which operates at voltages VDD2 and VSS2,
A fourth inverter having an input side connected to the thirteenth node and an output side connected to the fourteenth node and operating at voltages VDD2 and VSS2,
A third inverting drive circuit connected to the eleventh, twelfth and thirteenth nodes and operating at voltages VDD2, VDD1 and VSS1,
A level shift circuit including a fourth inversion driving circuit connected to the eleventh, twelfth and fourteenth nodes and operating at voltages VDD2, VDD1 and VSS1,
The third inversion driving circuit includes an eleventh PMOS transistor having a source connected to the terminal of the voltage VDD2, a gate connected to the thirteenth node, and a drain connected to the fifteenth node, and a gate connected to the voltage An eleventh NMOS transistor connected to the terminal of VDD1, a drain connected to the fifteenth node, and a source connected to the eleventh node; a gate and a drain connected to the eleventh node; A fifteenth NMOS transistor connected to the node of the second node, a thirteenth NMOS transistor having a drain connected to the seventeenth node, a gate connected to the twelfth node, and a source connected to the terminal of the voltage VSS1. Consists of
The fourth inversion driving circuit includes a twelfth PMOS transistor having a source connected to the terminal of the voltage VDD2, a gate connected to the fourteenth node, and a drain connected to the sixteenth node, and a gate connected to the voltage A twelfth NMOS transistor having a drain connected to the VDD1, a drain connected to the sixteenth node and a source connected to the twelfth node, a gate and a drain connected to the twelfth node, and a source eighteenth. A sixteenth NMOS transistor connected to the node of the first node, a fourteenth NMOS transistor having a drain connected to the eighteenth node, a gate connected to the eleventh node, and a source connected to the terminal of the voltage VSS1. Consists of
A second diode is connected between the voltage VDD2 terminal and the voltage VDD1 terminal such that the voltage VDD2 terminal is a cathode and the VDD1 terminal is an anode.
A level shift circuit characterized by that.

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