JPH10321742A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a both-face mounting semiconductor integrated circuit device which reduces chip area and prevents increase in signal propagation delay. SOLUTION: This device is constituted so that integrated circuit chips 11, 12 are respectively mounted on both faces of a chip mount part of a lead frame and respective electrodes 15, 16 corresponding to the integrated circuit chips 11, 12 are connected to a common lead terminal 17. In this case, an electrostatic protection circuit provided for the common lead terminal 17 comprises a first portion (an electrostatic protection circuit 13) provided in the one integrated circuit chip 11 and a second portion (an electrostatic protection circuit 14) provided in the other integrated circuit chip 12, and a combined set of the both portions satisfies the necessary functions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an integrated circuit chip mounted on both sides of a chip mounting portion of a lead frame, and corresponding electrodes of each integrated circuit chip are connected to common lead terminals. The present invention relates to a resin-sealed semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A resin-sealed semiconductor integrated circuit device has a configuration in which an integrated circuit chip is mounted on a chip mounting portion of a lead frame, and each electrode of the integrated circuit chip and a lead terminal are connected by a bonding wire. ing. With respect to such a normal resin-encapsulated semiconductor integrated circuit device, in order to improve the function or the mounting density, both sides of the chip mounting portion of the lead frame are configured to mount integrated circuit chips on both surfaces. A mounted semiconductor integrated circuit device has been proposed.

FIG. 2 shows a configuration diagram of a conventional double-sided semiconductor integrated circuit device. In the figure, reference numeral 31 denotes a chip mounting portion of a lead frame, and integrated circuit chips 32 and 33 are mounted on both surfaces thereof, respectively. The corresponding electrodes (not shown) of the integrated circuit chips 32 and 33 are connected to the common lead terminals 34 by bonding wires 35, respectively. 36 is a sealing resin. For example, each of the integrated circuit chips 32 and 33 is a memory chip having the same capacity.
In the case of doubling, only the decoder circuit portion that outputs the selection signal to the internal circuit based on the chip selection signal input differs,
The other parts are two memory chips of the same configuration (however, one chip is left / right (or up / down) with respect to the other chip)
(Inverted structure) is mounted on both sides of the chip mounting portion, and the corresponding electrodes of each memory chip are connected to the same lead terminal, so that the function (capacity) is the same, while the area is the same. Can be obtained twice. Such a semiconductor integrated circuit device is disclosed, for example, in Japanese Patent Laid-Open No. 2-87661.

[0004]

However, the conventional double-sided semiconductor integrated circuit device has the following problems.

Generally, an electrostatic protection circuit is provided for each electrode of an integrated circuit chip in preparation for the intrusion of static electricity from the outside. That is, the electrostatic protection circuit allows the static charge that has entered from the outside to escape to the power supply line or the like, thereby preventing a high voltage from being applied to the internal circuit and preventing its destruction. In a double-sided semiconductor integrated circuit device, such an electrostatic protection circuit is
The two integrated circuit chips contained therein are mounted on both sides of the chip mounting portion of the lead frame, and the corresponding electrodes of each integrated circuit chip are connected to the common lead terminals by bonding wires. Therefore, when viewed from each lead terminal, an electrostatic protection circuit having a required double function is connected. This means that an unnecessary circuit is provided more than necessary. In addition, the electrostatic protection circuit generally includes a transistor, a diode, and the like, as shown in FIG. 3, to which a capacitance such as a PN junction or a wiring capacitance is added. Therefore, in a double-sided semiconductor integrated circuit device, the capacity is about twice as large as that of a normal semiconductor integrated circuit device, and the delay of signal propagation increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and eliminates the above waste, reduces the chip area, and prevents an increase in signal propagation delay. A circuit device is provided.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device in which integrated circuit chips are mounted on both sides of a chip mounting portion of a lead frame. In a resin-sealed semiconductor integrated circuit device in which electrodes are respectively connected to a common lead terminal, an electrostatic protection circuit provided for the common lead terminal is provided only on one of the integrated circuit chips. It is characterized by becoming.

Further, in the semiconductor integrated circuit device of the present invention (claim 2), integrated circuit chips are mounted on both sides of the chip mounting portion of the lead frame, and the corresponding electrodes of the integrated circuit chips are respectively provided. In a resin-sealed semiconductor integrated circuit device connected to a common lead terminal, an electrostatic protection circuit provided for the common lead terminal
It is characterized by comprising a first portion provided on one integrated circuit chip and a second portion provided on the other integrated circuit chip, and configured to satisfy a required function by a set of both portions. Things.

According to the semiconductor integrated circuit device of the present invention, in the double-sided semiconductor integrated circuit device, the electrostatic protection circuit is provided on only one of the integrated circuit chips, or the electrostatic protection circuit of a predetermined scale is provided. Since it is configured to be provided separately on two integrated circuit chips, useless circuits can be eliminated, the chip area can be reduced, and an increase in parasitic capacitance added to each electrode can be prevented. This can prevent an increase in signal delay.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device according to one embodiment of the present invention.

The present embodiment is structurally the same as the structure of the conventional semiconductor integrated circuit device shown in FIG. 2, and FIG. 1 shows only the characteristic portions. In the figure, 11
And 12 are integrated circuit chips, for example, memory chips (DRAM, ROM, etc.) having the same capacity. In the present embodiment, a configuration is adopted in which electrostatic protection circuits of a required scale are provided separately on the two integrated circuit chips 11 and 12 (for example, each is provided with a half scale). In the figure, 13 and 14 are respectively
An electrostatic protection circuit provided on the integrated circuit chips 11 and 12;
And 14 are configured so as to obtain a necessary electrostatic protection function. 15 and 16 are respectively
The electrodes 17 to which the electrostatic protection circuits 13 and 14 are connected are:
The common lead terminals 18 and 19 for the electrodes 15 and 16 are the common lead terminal 17 and each electrode 1
It is a bonding wire connecting between 5 and 16.

FIG. 4 shows an integrated circuit chip 11 and an integrated circuit chip 1 according to a chip selection signal input from the outside.
2 shows a configuration of a control circuit portion that makes one of the two effective.

An external chip select signal is applied to the electrodes shown in FIG. Connect the wiring correction unit to the integrated circuit chip 1.
1 and 12, the internal control signal of one of the integrated circuit chips is H and the internal control signal of the other integrated circuit chip is L in accordance with the H and L of the chip selection signal.
And the chip selection is performed.

In the above embodiment, an electrostatic protection circuit for one lead terminal is provided separately on two integrated circuit chips, and a predetermined set of the electrostatic protection circuits provided on each integrated circuit chip is used. However, the configuration may be such that an electrostatic protection circuit of a necessary scale for one lead terminal is provided only on one of the integrated circuit chips. In this case, all the electrostatic protection circuits for all the lead terminals may be provided only on one of the integrated circuit chips (for example, the integrated circuit chip 11), or may be appropriately dispersed. For example, the electrostatic protection circuit for the input terminal may be provided on the integrated circuit chip 11 side, and the electrostatic protection circuit for the output terminal may be provided on the integrated circuit chip 12 side.

Since the substrates of the two integrated circuit chips can be bonded together to the chip mounting portion of the conductive lead frame, the substrate resistance between the chips can be reduced.
Therefore, even if the electrostatic protection circuit of the common lead terminal is provided only on one of the integrated circuit chips, or the size of the electrostatic protection circuit of the two integrated circuit chips is reduced by about half, a normal single integrated circuit chip can be used. The same electrostatic breakdown resistance as that of the semiconductor integrated circuit device can be obtained.

[0017]

As described above in detail, according to the semiconductor integrated circuit device of the present invention, in the double-sided semiconductor integrated circuit device, the electrostatic protection circuit is provided only on one of the integrated circuit chips, or , An electrostatic protection circuit of a predetermined scale
Since it is configured to be provided separately on one integrated circuit chip, unnecessary circuits can be eliminated, chip area can be reduced, and increase in parasitic capacitance added to each electrode can be prevented. , It is possible to prevent an increase in signal delay.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional double-sided mounted semiconductor integrated circuit device.

FIG. 3 is a diagram illustrating a configuration example of an electrostatic protection circuit.

FIG. 4 is a configuration diagram of a chip selection control circuit portion provided in each integrated circuit chip shown in FIG. 1;

[Explanation of symbols]

 11, 12 Integrated circuit chip 13, 14 Electrostatic protection circuit 15, 16 Electrode 17 Common lead terminal 18, 19 Bonding wire

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 25/18

Claims (2)

[Claims] An integrated circuit chip is mounted on both sides of a chip mounting portion of a lead frame, and respective electrodes of each integrated circuit chip are connected to common lead terminals, respectively. In the integrated circuit device, the electrostatic protection circuit provided for the common lead terminal is provided only on one of the integrated circuit chips. 2. A resin-sealed semiconductor in which integrated circuit chips are mounted on both surfaces of a chip mounting portion of a lead frame, and respective electrodes of the integrated circuit chips are connected to common lead terminals, respectively. In the integrated circuit device, the electrostatic protection circuit provided for the common lead terminal includes a first portion provided on one integrated circuit chip and a second portion provided on the other integrated circuit chip,
A semiconductor integrated circuit device configured to satisfy a required function by a set of the two parts.