JP3342645B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit chip mounted on both sides of a chip mounting portion of a lead frame, and each electrode of each integrated circuit chip and each lead terminal are connected by bonding wires. The present invention relates to a resin-sealed semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A resin-sealed semiconductor integrated circuit device has a configuration in which an integrated circuit chip is mounted on a chip mounting portion of a lead frame, and each electrode of the integrated circuit chip and a lead terminal are connected by a bonding wire. ing. With respect to such a normal resin-encapsulated semiconductor integrated circuit device, in order to improve the function or the mounting density, both sides of the chip mounting portion of the lead frame are configured to mount integrated circuit chips on both surfaces. A mounted semiconductor integrated circuit device has been proposed.

FIG. 2 shows a configuration diagram of a conventional double-sided semiconductor integrated circuit device. In the figure, reference numeral 31 denotes a chip mounting portion of a lead frame, and integrated circuit chips 32 and 33 are mounted on both surfaces thereof, respectively. The electrodes (not shown) of each of the integrated circuit chips 32 and 33 and the lead terminals 34 are connected by bonding wires 35, respectively. 36 is a sealing resin. For example, when the integrated circuit chips 32 and 33 are each a memory chip having the same capacity, and the capacity is doubled by mounting on both sides, a decoder circuit portion that outputs a selection signal to an internal circuit based on a chip selection signal input Only the difference, the other part is the same configuration of two memory chips (however, one chip is
By mounting the left and right (or upside down) structure on the other chip on both sides of the chip mounting portion, the corresponding electrodes of each memory chip are connected to the same lead terminal. A semiconductor integrated circuit device having twice the function (capacitance) with the same area can be obtained. Such a semiconductor integrated circuit device is disclosed, for example, in Japanese Patent Laid-Open No. 2-87661.

[0004]

However, the conventional double-sided semiconductor integrated circuit device has the following problems.

That is, in the above-mentioned conventional double-sided semiconductor integrated circuit device, there is a problem that circuits may be redundantly used between two integrated circuit chips.
In other words, a circuit that realizes a common function between both chips is
Each of them may be individually provided, and in that case, there is a problem that waste occurs in terms of chip area or power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. A double-sided semiconductor integrated circuit device which eliminates the above waste, reduces the chip area, and reduces the power consumption is provided. To provide.

[0007]

Means for Solving the Problems To solve the above problems,
Therefore, in the semiconductor integrated circuit device of the present invention , integrated circuit chips are mounted on both sides of the chip mounting portion of the lead frame, and each electrode of each integrated circuit chip and each lead terminal are connected by a bonding wire. In a resin-sealed semiconductor integrated circuit device, a common device for each of the above integrated circuit chips is used.
The common circuit that realizes the function is one of the integrated circuit chips
And only on one of the integrated circuit chips.
The received output signal of the common circuit receives the output signal.
Electrode and sealing resin
No lead and no bonding wire through the other
The configuration is such that the signal is transmitted to the integrated circuit chip .

[0008] In addition, the semiconductor integrated circuit device of the present onset Ming, Li
On both sides of the chip mounting part of the card frame.
Circuit chip is mounted, each electrode of each integrated circuit chip and each electrode
Resin with lead wires connected by bonding wires
In sealed semiconductor integrated circuit device, the common circuit for realizing the functions common to each of the integrated circuit chip is provided only in one of the integrated circuit chip, the common provided on only one of the integrated circuit chip described above the output signal of the circuit is the one
To the integrated circuit chip substrate
Electrodes that receive force signals, chip mounting parts of the lead frame,
And through the bonding wires, it you wherein where the structure is transmitted to the other integrated circuit chip.

In one embodiment, the semiconductor integrated circuit device is
Each integrated circuit chip is a memory chip.
The common circuit is an address transition detection circuit.
I do.

In one embodiment, the semiconductor integrated circuit device is
The common circuit is a substrate bias generation circuit.
I do.

In one embodiment, the semiconductor integrated circuit device is
The first common circuit common to each integrated circuit chip is:
Provided on only one of the integrated circuit chips,
Output of the first common circuit provided only on the circuit chip
The signal is applied to the electrode receiving this output signal,
Leads and bonds that are provided and are not led out
To the other integrated circuit chip via
And the second common circuit chip
A common circuit is provided only on the other integrated circuit chip.
And the second integrated circuit chip provided only on the other integrated circuit chip.
The output signal of the common circuit 2 receives the output signal.
The poles are provided inside the sealing resin and are not led out
One of the above via a lead and a bonding wire
Characterized in that it is configured to be transmitted to an integrated circuit chip.
You.

According to the semiconductor integrated circuit device of the present invention , the chip area and power consumption can be reduced.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a semiconductor integrated circuit device according to one embodiment of the present invention.

The present embodiment is structurally the same as the structure of the conventional semiconductor integrated circuit device shown in FIG. 2, and FIG. 1 shows only the characteristic portions. In the figure, 11
And 12 are integrated circuit chips, for example, memory chips (DRAM, ROM, etc.) having the same capacity. In the present embodiment, a common circuit 13 that realizes a function common to both integrated circuit chips is provided by an integrated circuit chip 11.
Is provided only on the side of. Therefore, it is necessary to transmit the output signal of the common circuit 13 to the other integrated circuit chip 12. The signal transmission is performed by the electrode 14 receiving the output signal of the common circuit 13, the bonding wire 15, and the internal lead 16.
(Leads that are not led out of the sealing resin, that is, are provided by being buried inside the sealing resin), bonding wires 17, and electrodes 18 of the other integrated circuit chip 12. In the drawing, the output signal line of the common circuit 13 is shown as a single line.
Needless to say, there may be more than one. In the figure, reference numeral 19 denotes an internal circuit of the integrated circuit chip 11 which receives an output of the common circuit 13;
In the integrated circuit chip 12, the internal circuit receives the output of the common circuit 13. Further, 21 and 22 are ordinary electrodes provided on the integrated circuit chips 11 and 12, respectively, 23 is a common lead terminal (one end thereof is led out of the sealing resin), and 24 and 25 are respectively This is a bonding wire that connects between the common lead terminal 23 and the electrodes 21 and 22. Also, 26 and 27 are
These are electrostatic protection circuits connected to the electrodes 21 and 22, respectively. Note that the leads 1 and
Since 6 is not led out of the sealing resin, it is not particularly necessary to provide an electrostatic protection circuit.

FIG. 3 shows an integrated circuit chip 11 and an integrated circuit chip 1 according to a chip selection signal input from the outside.
2 shows a configuration of a control circuit portion that makes one of the two effective.

An external chip select signal is applied to the electrodes shown in FIG. Connect the wiring correction unit to the integrated circuit chip 1.
1 and 12, the internal control signal of one of the integrated circuit chips is H and the internal control signal of the other integrated circuit chip is L in accordance with the H and L of the chip selection signal.
And the chip selection is performed.

In the above embodiment, the output signal of the common circuit 13 provided on one integrated circuit chip 11 is transmitted to the other integrated circuit chip 12 via bonding wires and internal leads. The common circuit may be a substrate bias generation circuit, and the output of the circuit may be transmitted to the substrate of the other integrated circuit chip via the chip mounting portion of the conductive lead frame.

FIG. 7 shows a schematic configuration diagram of an embodiment having such a configuration.

The present embodiment is structurally the same as the structure of the conventional semiconductor integrated circuit device shown in FIG. 2, and FIG. 7 shows only the characteristic portions. In the figure, 71
And 72 are DRAM chips having the same capacity. In the present embodiment, the substrate bias generation circuit 73
Are provided only on the DRAM chip 71 side. The negative voltage V _BB output from the substrate bias generation circuit 73 is equal to DR
The other DRAM chip 7 is provided to the substrate 74 of the AM chip 71 and is also connected to the other DRAM chip 7 through the conductive chip mounting portion 75.
The second substrate 76 is also provided.

Reference numeral 77 denotes a substrate bias generating circuit 73.
And GND for applying a GND potential to other parts
Reference numeral 78 denotes a GND terminal connected to the GND electrode 77 via a bonding wire 79. GND
The terminal 78 is also connected to a GND electrode (not shown) of the DRAM chip 72 via a bonding wire 80.

FIG. 8 shows a schematic configuration diagram of the DRAM chip 71. In the figure, 81 is a P substrate, and 82 is an N substrate.
Well. Reference numeral 83 denotes an N-channel MOS transistor formed on a P substrate 81 and constituting a peripheral circuit, and reference numeral 84 denotes a P-channel MOS transistor formed on an N well. Further, 85 is a select transistor of the memory cell, and 86 is the same capacitor. Reference numeral 87 denotes a substrate bias generation circuit,
A predetermined negative voltage V _BB is applied to P substrate 81.
As described above, by generating and applying the substrate bias voltage V _BB to the substrate, the threshold value of the selection transistor (N-channel MOS transistor) 85 of the memory cell increases, the leak current of the memory cell capacitor 86 decreases, and the data The holding time can be increased.

In the above embodiment, the common circuit 13
Although the (substrate bias generation circuit 73) is provided only on one integrated circuit chip 11 (DRAM chip 71), for example, the first common circuit is provided only on one integrated circuit chip 11 and its output signal is The second common circuit is provided only to the other integrated circuit chip 12 via the bonding wire and the internal lead or the chip mounting portion, and the second common circuit is provided only to the other integrated circuit chip 12, and the output signal is transmitted to another integrated circuit chip 12. The configuration may be such that the signal is transmitted to one integrated circuit chip 11 via a bonding wire and an internal lead or a chip mounting portion.

FIG. 4 shows an example in which the above-mentioned common circuit is replaced with an address transition detection circuit (ATD circuit) provided in a memory chip.
FIG. 2 is a schematic configuration diagram of an embodiment according to the present invention.

In the figure, 41 and 42 are respectively
Memory chips (DRAM, ROM, etc.) of the same capacity. In the present embodiment, the address transition detection circuit (A
The TD circuit 43 is provided only on the memory chip 41 side. Therefore, the output signal of the ATD circuit 43 (AT
D signal) to the other memory chip 42. The signal transmission is performed by the electrode 44 receiving the output signal of the ATD circuit 43, the bonding wire 45, and the internal lead 46.
(Leads that are not led out of the sealing resin, that is, are provided by being buried inside the sealing resin), bonding wires 47, and electrodes 4 of the other memory chip 42
8 is performed. In the figure, reference numeral 49 denotes an internal circuit that receives the output of the ATD circuit 43 in the memory chip 41, for example, a circuit that outputs a bit line precharge signal PRC1. An internal circuit receiving the output of the ATD circuit 43, for example, the bit line precharge signal PR
This is a circuit that outputs C2. Further, 51 and 52 are address input electrodes provided on the memory chips 41 and 42, respectively, 53 is a common lead terminal (address input terminal, one end of which is led out of the sealing resin),
54 and 55 are bonding wires connecting between the common lead terminal 53 and the electrodes 51 and 52, respectively. 56 and 57 are address buffer circuits connected to the electrodes 51 and 52, respectively.

FIG. 5 shows a configuration example of the ATD circuit, and FIG. 6 shows a timing chart including a precharge signal.

[0027]

As described above in detail, according to the semiconductor integrated circuit device of the present invention , the chip area can be reduced and
The power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional double-sided mounted semiconductor integrated circuit device.

FIG. 3 is a configuration diagram of a chip selection control circuit portion provided in each integrated circuit chip shown in FIG. 1;

FIG. 4 is a schematic configuration diagram of another embodiment of the present invention.

FIG. 5 is a configuration diagram of an ATD circuit.

FIG. 6 is an operation timing chart of the ATD circuit.

FIG. 7 is a schematic configuration diagram of another embodiment of the present invention.

FIG. 8 is a schematic configuration diagram of a DRAM chip.

[Explanation of symbols]

 11, 12 integrated circuit chip 13 common circuit 14, 18 electrode 15, 17 bonding wire 16 internal lead 41, 42 memory chip 43 ATD circuit 44, 48 electrode 45, 47 bonding wire 46 internal lead 71, 72 DRAM chip 73 substrate bias generation Circuit 74, 76 Substrate 75 Chip mounting section

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-130949 (JP, A) JP-A-8-18003 (JP, A) JP-A 8-139204 (JP, A) JP-A 8- 167703 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 25/00-25/18

Claims (5)

(57) [Claims] 1. A resin-sealed semiconductor integrated circuit in which integrated circuit chips are mounted on both sides of a chip mounting portion of a lead frame, and each electrode of each integrated circuit chip and each lead terminal are connected by bonding wires. In a circuit device, a common circuit that realizes a function common to each of the integrated circuit chips
Is provided only on one of the integrated circuit chips, and the common circuit provided only on the one integrated circuit chip.
The output signal of the path is an electrode receiving this output signal, the sealing resin
And the lead which is provided inside and is not led out
Via bonding wires to the other integrated circuit chip
A semiconductor integrated circuit device having a configuration in which transmission is performed . 2. Both sides of a chip mounting portion of a lead frame.
Integrated circuit chips are mounted on the respective integrated circuits.
Bonding wire between each chip electrode and each lead terminal
In a resin-sealed semiconductor integrated circuit device connected by
Te, common circuit for realizing the functions common to each of the integrated circuit chip is provided only in one of the integrated circuit chip, the output signal of the common circuit provided only on one of the integrated circuit chip described above one above Given to the substrate of the integrated circuit chip
Electrodes and the lead frame
Via the chip mounting part and bonding wire
Te, other integrated circuit semi-conductor integrated circuit device you characterized by being configured to be transmitted to the chip. 3. The semiconductor integrated circuit device according to claim 1,
Oite, each integrated circuit chip, a memory chip der respectively
That is, the common circuit is an address transition detection circuit.
A semiconductor integrated circuit device characterized by the above-mentioned. 4. The semiconductor integrated circuit device according to claim 2,
Oite, the common circuit, that the substrate bias generating circuit Laid
Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1,
Oite first common circuit common to each of the integrated circuit chip, what
Provided only on one of the integrated circuit chips,
Of the first common circuit provided only on the integrated circuit chip.
The output signal is applied to the electrode receiving the output signal and the sealing resin.
Leads and Bones that are provided in the
To the other integrated circuit chip via
Transmitted and a second common circuit common to the integrated circuit chips is
The other integrated circuit chip is provided only on the other integrated circuit chip.
The output of the second common circuit provided only in the integrated circuit chip
The force signal is applied to the electrode receiving this output signal and the inside of the sealing resin.
Leads and bonds that are
Via the connecting wire to one of the integrated circuit chips.
Semiconductor integrated circuit device characterized in that
Place.