JPH10313006A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of wiring with a less number of steps while preventing shift of overlayed mask. SOLUTION: A resist film 3 is first formed on an insulating film provided on a lower conductive layer 1. A groove pattern 4 is then formed in the resist film 3 by a lithographic process, so that the resist film 3 remains at a bottom of the pattern 4 for formation of a wiring groove 6. A hole pattern 5 is formed on the resist film 3 at the bottom of the groove pattern 4 so as to make a contact hole 7 reach the insulating film 2 from the bottom. Thereafter, the resist and insulating films 3 and 2 are etched to form the wiring groove 6 at a position corresponding to the groove pattern 4 of the film 2 and to form the contact hole 7 communicating with the groove 6 and reaching the lower conductive layer 1 at a position corresponding to the hole pattern 5 of the film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device applied to a wiring forming process.

[0002]

2. Description of the Related Art In recent years, in the field of manufacturing semiconductor devices, multi-layer wirings have been adopted as semiconductor devices become more highly integrated. In the conventional method of forming a wiring up to the 0.25 μm generation, when forming an aluminum (Al) multilayer wiring, for example, the following method is used. First, a contact hole is formed in an insulating film on a lower Al wiring layer, and then tungsten (W) is buried in the contact hole to form a W plug and a W film is formed on the insulating film. After the W film is etched back to flatten the surface of the W plug, an upper layer of Al is formed on the W plug.
Form wiring. According to this method, conduction of the Al wirings in the upper and lower layers can be ensured even if a slight misalignment occurs between the contact portion formed of the W plug and the mask for forming the Al wiring. However, in the future, when the wiring is further miniaturized, the misalignment of the mask will be a major bottleneck.

[0005] Usually, wiring processing is performed by reactive ion etching (RIE), but deviation occurs because no self-alignment technique is used. At this time, if over-etching is caused, a problem occurs in that the contact portion is cut deep according to the size of the shift width. Therefore,
As a method for solving this problem, a dual damascene method has recently been devised.

[0004] There are various methods for the dual damascene method. In general, as shown in FIG.
(Chemical vapor deposition) method, the first
An insulating film 52, a first etching stopper layer 53, a second insulating film 54, and a second etching stopper layer 55 are sequentially laminated. For example, the first insulating film 52 and the second insulating film are made of a silicon oxide (SiO ₂ ) film, and the first etching stopper layer 53 and the second etching stopper layer 55 are made of a silicon nitride (SiN) film.

Next, as shown in FIG. 7B, after forming a resist film 56 on the second etching stopper layer 55, a wiring groove pattern 56a is formed in the resist film 56 by lithography. Subsequently, as shown in FIG. 7C, a trench 57 for wiring is formed in the second etching stopper layer 55, the second insulating film 54, and the first etching stopper layer 53 by RIE using the resist film 56 as a mask. Then, the resist film 56 is removed.

Next, as shown in FIG. 7D, a resist film 58 is formed on the second etching stopper layer 55, and thereafter, a hole pattern 58a communicating with the wiring groove 57 is formed in the resist film 58 by lithography. To form Then, by RIE using the resist film 58 as a mask,
As shown in FIG. 7E, the lower wiring 51 is formed on the first insulating film 52.
Is formed and a contact hole 59 communicating with the groove 57 is formed.

After that, Al is buried in the groove 57 and the contact hole 59 by sputtering, and an Al film is formed on the second etching stopper layer 55. Alternatively, Cu is buried in the trench 57 and the contact hole 59 by the CVD method and the second
A Cu film is formed on the etching stopper layer 55. Then, the Al film or the Cu film is removed by a CMP (chemical mechanical polishing) method until the upper surface of the second etching stopper layer 55 is exposed, and the upper wiring formed of the Al film or the Cu film and the upper wiring and the lower wiring 51 are formed. Is formed.

[0008]

In the above-described method for forming a wiring using the dual damascene method, the above-described 0.25
The step of embedding the W plug in the contact hole can be omitted as compared with the method of forming the wiring of the μm generation.
However, since the self-alignment technique is introduced, as described above, four CVD steps and two lithography steps for individually forming a groove pattern for wiring and a hole pattern for contact holes, and Times RI
The step E is required, and the number of steps is greatly increased. As a result, there are disadvantages that the manufacturing yield is reduced, the manufacturing cost is increased, and the reliability of the semiconductor device is reduced.
Therefore, there is a need to establish a semiconductor device manufacturing technique capable of forming a wiring in a small number of steps without causing a mask overlay displacement.

[0009]

In the method of manufacturing a semiconductor device according to the present invention, first, a resist film is formed on an insulating film formed on a conductive layer. Next, a groove pattern for forming a wiring groove is formed on the resist film by lithography with the resist film remaining at the bottom of the groove pattern, and the resist film at the bottom of the groove pattern is formed from the bottom to the insulating film. A hole pattern for forming a contact hole is formed in the reached state. Thereafter, by etching under conditions that etch the insulating film together with the resist film, a groove for wiring is formed at a position corresponding to the groove pattern of the insulating film, and the groove communicates with the groove at a position corresponding to the hole pattern of the insulating film; A contact hole reaching the conductive layer is formed.

According to the present invention, since a hole pattern and a groove pattern are formed in a resist film by one lithography, the mask is overlapped by performing the wiring groove pattern and the contact hole pattern by separate lithography. No deviation occurs. Further, since only one lithography process is required, there is no need to use a self-alignment technique. Therefore, since the step of forming the etching stopper layer is not required, the film forming step is performed only once for forming the insulating film on the conductive layer. Further, etching is performed under the condition of etching the insulating film together with the resist film,
A single etching step is required to form a wiring groove and a contact hole in the insulating film.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. Prior to this, first, an example of a mask used in the embodiment will be described with reference to FIG. The effect of this mask on resist patterning will be described with reference to FIGS. 4, 5 and 6. FIG. FIG. 3A is a plan view of an example of a mask, and FIG. 3B is a partially enlarged view of FIG. 3A. For ease of explanation, one groove pattern for wiring and the groove pattern for contact holes are used. Only the parts necessary to form one hole pattern communicating with the pattern are shown. Therefore,
It is different from the actual circuit wiring. A mask using a reduction projection exposure apparatus is generally called a reticle.
In this specification, this is also referred to as a mask.

The mask 20 is used for patterning, for example, a positive resist film in a lithography process of an embodiment described later. Although a mask using a reduction projection exposure apparatus is generally called a reticle, it is also called a mask in this specification. As shown in FIG. 3, the mask 20 includes a mask body 21.
A first mask pattern 22 for forming the groove pattern and a second mask pattern 23 for forming the hole pattern are provided corresponding to the positional relationship between the groove pattern and the hole pattern described later. Have been. The first mask pattern 22 is formed of a material having a lower transmittance of exposure light (hereinafter simply referred to as light) than the second mask pattern 23.

Further, a portion 2 of the mask body 21 different from the first mask pattern 22 and the second mask pattern 23
4, that is, a portion (hereinafter, referred to as other portion) 24 for forming a resist mask other than the first mask pattern 22 and the second mask pattern 23 is made of a material having a lower light transmittance than the first mask pattern 22. It is formed with. Therefore, the mask 20 is formed of three types of materials having different transmittances. Here, the first mask pattern 22 is made of translucent half-tone chrome (Cr), the second mask pattern 23 is made of transparent quartz glass, and the other portions 24 of the mask main body 21 are used as the complete light shield. Cr (shown by hatching in the figure)
It is formed with.

Specifically, a Cr thin film is formed on a glass substrate, and is etched in a groove shape from the upper surface of the Cr thin film to a position approximately half the thickness of the Cr thin film to form a first mask pattern 22. . Also, the first mask pattern 22
A hole-shaped second mask pattern 23 is formed in the Cr thin film in a state of reaching the glass substrate from the bottom of the groove. Therefore, when the mask 20 is viewed in plan, the second mask pattern 2
A glass substrate is provided at the formation position of No. 3, and the first mask pattern 22 is provided with a half-tone Cr that is translucent, and the other portions 24 are provided with a Cr that is a complete light shield.

FIG. 4 is a plan view showing, with contour lines, the light intensity transferred to the upper surface of the resist film applied on the semiconductor wafer when exposure is performed using such a mask 20. The AB direction in (b) is the A-B direction in FIG.
It corresponds to the B direction. FIG. 5 is a diagram showing a light intensity distribution in a cross section taken along a line AB in FIG. 4, and FIG.
FIG. 4 is a cross-sectional view of a resist pattern shape obtained by developing the resist film of FIG.

As shown in FIGS. 4 and 5, the portion corresponding to the second mask pattern 23 made of glass having the highest light transmittance has the highest light intensity and the first mask pattern 22 made of halftone Cr. The corresponding part has about half the light intensity of the part with the highest light intensity. Therefore, as shown in FIG. 6, if the height of the portion corresponding to the other portion 24 that is shielded from light is set to 1, the positive resist after development is the first resist.
The height of the portion corresponding to the mask pattern 22 becomes about 0.5, and the portion corresponding to the second mask pattern 23 is completely removed.

In the above example, the mask used for exposing the positive resist is described. However, the mask used for exposing the negative resist includes the first mask pattern 22, the second mask pattern 23, Of which the transmittance is inverted from that of the mask 20 of the above example. For example, the second mask pattern 23 is formed of Cr, the first mask pattern 22 is formed of halftone Cr having a light transmittance higher than that of the second mask pattern 23, and the other portions 24 are formed of a material other than the first mask pattern 23. Use is made of glass having high light transmittance. By exposing and developing the negative resist using this mask, a resist pattern having a cross-sectional shape similar to that of FIG. 6 can be formed.

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Here, a case where a positive resist is used as the resist and the mask 20 shown in FIG. 3 is used will be described as an example. FIGS. 2A to 2F are cross-sectional views of the semiconductor device corresponding to a section between A and B of the mask 20 in each step of the manufacturing method according to the present embodiment.

In this method of manufacturing a semiconductor device, first, FIG.
As shown in FIG. 1A, a structure in which an insulating film 2 is formed on a lower conductive layer 1 made of, for example, a lower wiring is prepared. Insulating film 2
Is formed of, for example, a material film containing oxygen atoms, and here is formed of, for example, a SiO ₂ film formed by a CVD method. Next, as shown in FIGS. 1B and 2A, a positive resist film 3 is formed on the insulating film 2 by a spin coating method.

Thereafter, as shown in FIGS. 1B and 2B, a wiring groove is formed in the resist film 3 by lithography (exposure, development, baking, etc.) using the mask 20. And a hole pattern 5 for forming a contact hole. At this time, the groove pattern 4 is formed with the resist film 3 left at the bottom of the groove pattern 4. Further, the insulating film 2 is formed on the resist film 3 at the bottom of the groove pattern 4 from the bottom of the groove pattern 4.
The hole pattern 5 is formed in a state of reaching.

As described above, in the mask 20, the first mask pattern 22 for forming the groove pattern 4 is made of half-tone Cr, and the second mask pattern 22 for forming the hole pattern 5 is formed.
Since the mask pattern 23 is made of glass (see FIG. 3), the groove pattern 4 can be formed with the resist film 3 left at the bottom by using the mask 20, and the insulating film 2 reaches from the bottom of the groove pattern 4. Hole pattern 5
Can be formed.

Next, anisotropic etching such as RIE under the condition of etching the insulating film 2 together with the resist film 3 having the groove pattern 4 and the hole pattern 5 is performed as shown in FIG.
2C, a wiring groove 6 is formed at a position corresponding to the groove pattern 4 of the insulating film 2 and a contact hole 7 is formed at a position corresponding to the hole pattern 5 of the insulating film 2. Form. At this time, a contact hole 7 communicating with the groove 6 and reaching the lower conductive layer 1 is formed.

The above-described etching is performed, for example, as follows. First, the etching rate of the insulating film 2 (Etching Ra)
te) and the etching rate of the resist film 3 are almost the same, that is, the etching is advanced under the condition that the etching selectivity between the insulating film 2 and the resist film 3 is almost 1 (hereinafter, referred to as a first condition). As a result, as shown in FIG. 2C, the insulating film 2 immediately below the hole pattern 5 is etched and the entire resist film 3 is etched back.

By performing etching under the first condition until the resist film 3 remaining at the bottom of the groove pattern 4 is removed, the surface of the portion 2a of the insulating film 2 corresponding to the groove pattern 4 is exposed to the outside. In the portion corresponding to the hole pattern 5 of the insulating film 2, a concave portion 2b not reaching the lower conductive layer 1 is formed. That is, the shape of the resist film 3 having the groove pattern 4 and the hole pattern 5 is transferred to the insulating film 2.

The resist film 3 left at the bottom of the groove pattern 4
Is removed, the condition that the etching selectivity of the resist film 3 with respect to the insulating film 2 becomes larger than 1, that is, the condition that the etching rate of the insulating film 2 becomes faster than the etching rate of the resist film 3 (hereinafter, the second condition) And the etching proceeds. Thereby, the resist film 3
Is removed and the portion of the insulating film 2 where the surface is exposed is etched while maintaining the surface shape. Therefore, FIG.
As shown in (d), the portion 2 where the groove pattern 4 has been transferred
is etched to form a trench 6 for wiring, and a contact hole 7 reaching the lower conductive layer 1 by removing the insulating film 2 remaining at the bottom of the concave portion 2 b formed by transferring the hole pattern 5. Is formed.

Here, the timing of switching between the first condition and the second condition is such that, for example, etching under each condition is performed using a gas containing carbon atoms, and the carbon atoms and the oxygen forming the insulating film 2 are formed. This is performed by monitoring the emission intensity of carbon monoxide obtained by reacting with atoms. That is, the resist film 3 is etched back to expose the surface of the insulating film 2 at a position corresponding to the groove pattern 4, and when the etching of this portion starts, the etching area of the insulating film 2 changes, so that carbon monoxide is removed. The incidence increases and the emission intensity of carbon monoxide changes. When this change is detected by monitoring the emission intensity, the first condition is switched to the second condition. Examples of the etching gas containing a carbon atom include a fluorocarbon-based (C _x F _y ) gas.

According to this detection method, even when the surface of the groove pattern 4 is not formed flat, the time point at which the resist film 3 remaining at the bottom of the groove pattern 4 is removed can always be detected with high accuracy. It is very suitable as a detection method used for switching etching conditions. In addition, if the surface of the groove pattern 4 is formed flat, it is needless to say that the etching conditions can be switched depending on the etching time or the like.

The insulating film 2 from the first condition to the second condition
The switching of the etching selection ratio of the resist film 3 to the etching is performed by, for example, changing the kind of etching gas or the flow ratio of the etching gas. An example of the type and flow rate of the etching gas under the first condition and the second condition is shown below.

First condition: etching gas and flow rate; C ₄ F ₈ / CO / Ar / O
₂ : 4 sccm / 150 sccm / 150 sccm / 1
5 sccm Second condition: etching gas and flow rate; C ₄ F ₈ / CO / Ar: 4
sccm / 150 sccm / 150 sccm Here, sccm is a volume flow rate (cm ³ in a standard state).
/ Min).

After the wiring groove 6 and the contact hole 7 are formed in the insulating film 2, the resist film 3 remaining on the insulating film 2 is removed as shown in FIG. Then, for example, Al, Cu, Al-C
A film made of a wiring material such as u is formed, and the wiring material is embedded in the wiring groove 6 and the contact hole 7. Then, the wiring material film is removed to a position where the upper surface of the insulating film 2 is exposed by, for example, a CMP method to planarize the surface. Thus, the upper layer wiring 8 in which the wiring material is buried in the wiring groove 6 and the upper layer wiring 8 in which the wiring material is buried in the contact hole 7 and are formed continuously with the upper layer wiring 8, A contact portion 9 for conduction with the lower conductive layer 1 is formed.

As described above, in this embodiment, since the groove pattern 4 and the hole pattern 5 are formed in the resist film 3 by one lithography, the groove pattern for wiring and the hole pattern for contact hole are formed as in the conventional method. And lithography are performed by different lithography, thereby preventing the mask from being misaligned. For this reason, even if the miniaturization of the wiring progresses, it is possible to reliably prevent a decrease in the electrical reliability of the semiconductor device due to the occurrence of the misalignment of the mask.

Further, since only one lithography step is required, no self-alignment technique is required. Therefore, unlike the conventional method using the dual damascene method, a CVD process for forming an etching stopper layer is not required, and
One-time CVD for forming insulating film 2 on lower conductive layer 1
Since the number of steps is enough, the number of film forming steps can be significantly reduced. Further, the etching is performed under the condition of etching the insulating film 2 together with the resist film 3 to form the wiring groove 6 and the contact hole 7, so that only one etching step is required.

Therefore, one lithography step, 1
Since only one film forming step and one etching step are required and the number of steps can be significantly reduced, the manufacturing yield can be improved and the manufacturing cost can be reduced. In addition, since the semiconductor device can be manufactured with a small number of steps, the reliability of the semiconductor device can be improved. Therefore, by using the method of manufacturing a semiconductor device according to the present embodiment, it is possible to form a multi-layer wiring that is fine and has high electrical reliability in a small number of steps. Furthermore, the cost advantage is obtained, and the dual damascene method can be adopted. As a result, the wiring resistance, the device speed, and the flatness required for the next generation can be improved.

[0034]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, since a groove pattern and a hole pattern are formed in a resist film by one lithography, the mask is overlapped as in the prior art. There is no gap,
This can reliably prevent a decrease in the electrical reliability of the semiconductor device due to this. In addition, since a single lithography process is required, a self-alignment technique is not required, so that the number of film formation steps on a conductive layer can be significantly reduced as compared with a conventional method using a dual damascene method. Further, since a wiring groove is formed and a contact hole is formed in one etching step, the number of etching steps can be reduced. Therefore, the number of steps can be significantly reduced, so that the manufacturing yield can be improved and the miniaturization can be advanced while improving the reliability of the semiconductor device.

[Brief description of the drawings]

1A to 1C are perspective views showing an embodiment of the present invention in the order of steps.

FIGS. 2A to 2F are cross-sectional views showing an embodiment of the present invention in the order of steps.

3A and 3B are diagrams illustrating an example of a mask used in the embodiment. FIG. 3A is a plan view, and FIG. 3B is a partially enlarged plan view of FIG.

FIG. 4 is a plan view showing the light intensity transferred to the upper surface of the resist film by contour lines.

FIG. 5 is a diagram showing a light intensity distribution in a cross section taken along a line AB in FIG. 4;

FIG. 6 is a sectional view of a resist pattern shape obtained by developing the resist film of FIG. 5;

7A to 7E are cross-sectional views showing an example of a conventional method in the order of steps.

[Explanation of symbols]

Reference Signs List 1 lower conductive layer 2 insulating film 3 resist film
Reference Signs List 4 groove pattern 5 hole pattern 6 wiring groove 7 contact hole 20 mask 21 mask body 22 first mask pattern 23 second mask pattern 24 other places

Claims (9)

[Claims] After a resist film is formed on an insulating film formed on a conductive layer, a groove pattern for forming a wiring groove is formed on the resist film by lithography at a bottom of the groove pattern. And forming a hole pattern for forming a contact hole in the resist film at the bottom of the groove pattern so as to reach the insulating film from the bottom, and the resist film together with the resist film. By etching under the condition of etching the insulating film, a groove for wiring is formed at a position of the insulating film corresponding to the groove pattern, and the conductive film communicates with the groove at a position of the insulating film corresponding to the hole pattern. Forming a contact hole reaching the layer. 2. A positive resist film is used as the resist film, and a mask used in lithography in the first step is:
A first mask pattern for forming the groove pattern and a second mask pattern for forming the hole pattern are formed on the mask body in a state corresponding to a positional relationship between the groove pattern and the hole pattern. With the first
The mask pattern is formed of a material having a lower light transmittance than the two mask patterns, and a portion of the mask body different from the first mask pattern and the second mask pattern transmits light more than the first mask pattern. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a material formed of a material having a low rate is used. 3. A negative resist film is used as the resist film, and a mask used in lithography in the first step is:
A first mask pattern for forming the groove pattern and a second mask pattern for forming the hole pattern are formed on the mask body in a state corresponding to a positional relationship between the groove pattern and the hole pattern. With the first
The mask pattern is formed of a material having a higher light transmittance than the two mask patterns, and a portion of the mask body different from the first mask pattern and the second mask pattern transmits light more than the first mask pattern. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a material formed of a material having a high rate is used. 4. In the second step, etching is performed under the condition that an etching selectivity between the resist film and the insulating film becomes substantially 1, whereby the resist film left at the bottom of the groove pattern is removed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is advanced by switching to a condition in which an etching selectivity of the resist film with respect to the insulating film is larger than 1 at a time of the removal. 5. In the second step, etching is performed under a condition that an etching selectivity between the resist film and the insulating film becomes substantially 1, whereby a resist film left at the bottom of the groove pattern is formed. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching is switched to a condition where an etching selectivity of the resist film with respect to the insulating film is larger than 1 at a time of the removal. 6. In the second step, etching is performed under a condition that an etching selectivity between the resist film and the insulating film becomes substantially 1, whereby a resist film remaining at the bottom of the groove pattern is formed. 4. The method of manufacturing a semiconductor device according to claim 3, wherein, at the time of the removal, the condition is changed to a condition where an etching selectivity of the resist film with respect to the insulating film is larger than 1. 7. The insulating film is made of a material film containing oxygen atoms. In the second step, etching is performed using a gas containing carbon atoms, and the carbon atoms react with the oxygen atoms. 5. The method according to claim 4, wherein the emission intensity of carbon monoxide obtained as a result is monitored, and the etching condition is switched when a change in the emission intensity is detected. 6. 8. The insulating film is made of a material film containing oxygen atoms. In the second step, etching is performed using a gas containing carbon atoms, and the carbon atoms react with the oxygen atoms. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the emission intensity of the carbon monoxide obtained by the monitoring is monitored, and the etching condition is switched when a change in the emission intensity is detected. 9. The insulating film is made of a material film containing oxygen atoms. In the second step, etching is performed using a gas containing carbon atoms, and the carbon atoms react with the oxygen atoms. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the emission intensity of the carbon monoxide obtained by the monitoring is monitored, and the etching condition is switched when the change in the emission intensity is detected.