JPH10283056A - Clock signal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a larger power saving effect by deciding and supplying the combination of an operation frequency and a drive current capable of operating system logic. SOLUTION: A frequency control circuit 1 decides a frequency to be supplied to the system logic and reports it to a frequency variable oscillation circuit 2 by using control signals (a). For the decision method of the frequency, an operation is performed by a maximum frequency capable of operating the system logic at the time of a normal operation, and at the time of wanting to reduce power consumption, at the time of using a battery for instance, the system logic is operated at a low frequency. Simultaneously, a drive current decision circuit 3 decides a minimum drive current capable of operating the system logic at the frequency decided in the frequency control circuit 1 based on the control signals (a). The drive current decided by the drive current decision circuit 3 is reported to a drive circuit 4 by the control signals (c), and by turning parallelly connected transistors on and off, only a required current is driven.

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a power consumption reducing circuit, and more particularly to a power consumption reducing circuit for a personal computer.

[0001]

2. Description of the Related Art In personal computers, particularly notebook-type personal computers, power consumption of devices has become important for the purpose of realizing long-time operation of batteries and facilitating thermal design.

Conventionally, various measures have been taken to reduce the power consumption of personal computers. One of the methods for reducing power consumption is to lower the input frequency to system logic including a CPU. Most of the system logic used in current personal computers is composed of CMOS LSI.
Since the power consumption is almost proportional to the operating frequency, this method is effective in reducing the power consumption. Hereinafter, a conventional power consumption reduction method will be described with reference to the drawings.

FIG. 2 is a block diagram of an operating frequency reducing circuit in a conventional personal computer. In FIG. 2, 1 is a frequency control circuit, 2 is a variable frequency oscillation circuit,
Reference numeral 5 denotes a system logic including a CPU. A indicates a control signal, and b indicates an input clock to the system logic. The variable frequency oscillation circuit 3 has a feature that the frequency of the input clock to the system logic b can be changed by the control signal a.

The frequency control circuit 1 determines a frequency to be supplied to the system logic and transmits it to the variable frequency oscillation circuit 2 using the control signal a. There are various methods for determining the frequency to be supplied to the system logic.However, here, simply during normal operation, the system logic is operated at the maximum operable frequency, and when it is desired to reduce the power consumption, it is low. It shall be operated at the frequency.

The variable frequency oscillator 2 supplies a clock b determined by the control signal a to the system logic 5.

[0006]

However, the above-described conventional configuration has a problem that the effect of reducing power consumption is small. The reason is that, since the drive current in the system logic is fixed, an unnecessarily large current flows in the system logic even when the input frequency is reduced to reduce power consumption.

An object of the present invention is to realize a more effective low power consumption circuit by making a drive current in a system logic variable.

[0008]

A power consumption reduction circuit according to the present invention comprises an oscillation circuit whose frequency can be changed, and a drive current determination circuit that determines a drive current at which system logic can operate.

According to the configuration of the present invention, the drive current in the system logic is determined by the drive current determination circuit. This circuit has a function of determining a drive current for operating at a desired frequency. To reduce power consumption, not only lower the frequency, but also allow the lowest current operable at that frequency to flow through the system logic, resulting in lower power consumption compared to the conventional frequency-only method. Is big.

[0010]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a power consumption reduction circuit according to a first embodiment of the present invention. 1 is a frequency control circuit, 2 is a variable frequency oscillation circuit, 3 is a drive current determination circuit, 4 is a drive circuit in system logic,
5 indicates system logic.

The drive circuit 4 includes a plurality of transistors whose drive currents are I1 to In. In addition, a is a control signal determined by the frequency control circuit 1, b is an input clock to the system logic generated by the frequency variable oscillation circuit 3, c is a control signal determined by the drive current determination circuit 3, and d is a drive signal. It shows the current that the circuit 4 drives.

The difference from the prior art is that a drive current determination circuit is provided and the drive circuit is divided into a plurality of transistors that can be turned on and off. The operation of the power consumption reducing circuit configured as described above will be described below.

The frequency control circuit 1 determines a frequency to be supplied to the system logic and transmits it to the variable frequency oscillation circuit 2 using the control signal a. As in the conventional method, the frequency is determined at the maximum frequency at which the system logic can operate during normal operation, and when the power consumption is to be reduced, for example, when the battery is used, the system logic is operated at a low frequency. . At the same time, the drive current determination circuit 3 determines the minimum drive current at which the system logic can operate at the frequency determined by the frequency control circuit 1 based on the control signal a.

The combination of the operating frequency and the drive current is determined by the characteristics of the CMOS LSI constituting the system logic, and can be set in advance before designing the power consumption reducing circuit of the present invention. It is. The drive current determined by the second drive current determination circuit 2 is transmitted to the drive circuit 4 by the control signal c, and drives the necessary current by turning on / off the transistors connected in parallel.

[0015]

The power consumption reduction circuit according to the present invention determines and supplies a combination of an operating frequency and a drive current at which the system logic can operate, thereby providing a larger power consumption reduction circuit than a power consumption reduction circuit that controls only the frequency. Power saving effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a low power consumption circuit of the present invention.

FIG. 2 is a block diagram of a conventional low power consumption circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Frequency control circuit 2 Frequency variable circuit 3 Drive current determination circuit 4 Drive circuit 5 System logic

Claims (2)

[Claims] A means for determining a drive frequency of a clock signal; a means for determining a drive current in accordance with the determined drive frequency; and a control signal for generating a control signal indicating the drive current value; A clock signal driving circuit, comprising: means for generating a signal; and driving means for outputting the clock signal with the determined driving current value of the generated signal. 2. The driving unit includes a plurality of transistors connected in parallel, and a plurality of switches provided at output stages of the plurality of transistors, the plurality of switches being opened and closed by the control signal. The clock signal driving circuit according to claim 1, wherein