JPH10233636A - Amplifier and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the amplifier in which an offset voltage and a temperature drift are cancelled. SOLUTION: An amplifier 1 is provided with 1st and 2nd operational amplifier circuits 2, 3. The 1st operational amplifier circuit 2 configures a voltage follower circuit where its output terminal connects to an inverting, input terminal, and the output terminal is connected to an inverting input terminal of the 2nd operational amplifier circuit 3. The circuit configuration and the circuit components of the 1st and 2nd operational amplifier circuits 2, 3 are identical to each other, and then they have the same characteristic and the same offset voltage. Then the output terminal of the 1st operational amplifier circuit 2 is connected to the inverting input terminal of the 2nd operational amplifier circuit 3 to allow the offset voltages of the 1st and 2nd operational amplifier circuits 2, 3 to be cancelled with each other and then the offset voltage of the amplifier 1 is cancelled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier such as an operational amplifier, which is one of the most important circuits in the field of analog electronic circuits.

In recent years, electronic circuits have been required to have higher precision. In order to increase the precision of the circuit operation, an amplifier such as an ideal operational amplifier having no offset voltage or the like is required.

[0003]

2. Description of the Related Art FIG. 13 shows a conventional operational amplifier (operational amplifier) 50. The operational amplifier 50 constitutes a voltage follower having an output terminal connected to an inverting input terminal (−side input terminal), and operates as a buffer for a signal In input to a non-inverting input terminal (+ side input terminal). .

In the operational amplifier 50, the characteristics of the transistors constituting the operational amplifier 50 vary due to process variations and the like. Therefore, an offset voltage of an output signal due to variations in transistor characteristics is inevitable.

Therefore, an adjustment circuit 51 such as an external resistor is connected to the outside of the chip of the operational amplifier 50, and the adjustment circuit 51 cancels an offset.
Some operational amplifiers have an adjustment circuit formed on the semiconductor chip and cancel the offset voltage by trimming or the like before shipping.

[0006]

However, FIG.
The adjustment circuit 51 shown in FIG. 11 only adjusts the offset voltage shown in FIG. 11A so that the offset voltage becomes almost zero near a desired point as shown in FIG. 11B. Therefore, the offset cannot be canceled for the entire operation range.

The addition of the external adjustment circuit 51 requires adjustment when the operational amplifier 50 is integrated into an IC, which is troublesome. Further, if an adjustment circuit is connected to the outside or a pattern for trimming is formed on an IC, the circuit scale of the entire electronic circuit increases and the cost increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide an amplifier capable of canceling offset voltage and temperature drift, and a semiconductor integrated circuit device having the amplifier. It is in.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a first input terminal having an inverting input terminal and a non-inverting input terminal, the output terminal being connected to the inverting input terminal. And a second amplifying unit having the same circuit configuration and circuit elements as the first amplifying unit, and having a signal from an output terminal of the first amplifying unit input to an inverting input terminal. The gist is to have prepared.

[0010] The invention described in claim 2 is the same as the claim 1.
The output terminal of the second amplifying unit is connected to a non-inverting input terminal of the first amplifying unit,
The gist is that a non-inverting amplifier is constituted by the second amplifier.

[0011] The invention according to claim 3 is based on claim 1.
3. The amplifier according to claim 2, wherein the first and second amplification units are formed adjacently on the same chip.

Further, the invention described in claim 4 is the first invention.
The present invention provides an amplifier described in any one of (1) to (3) and an internal circuit connected to an input terminal of the amplifier and outputting a signal to the amplifier.

(Operation) Therefore, according to the first aspect of the present invention, the first amplifier and the second amplifier have the same characteristics because the circuit configuration and the circuit elements are formed identically.
The same offset voltage results. Then, by connecting the output terminal of the first amplifier to the inverting input terminal of the second amplifier, the first and second offset voltages cancel each other, and the offset voltage of the amplifier is cancelled.

According to the second aspect of the present invention, the output terminal of the second amplifier is connected to the non-inverting input terminal of the first amplifier, and the first and second amplifiers perform non-inversion. An amplifier is configured, and offset voltages of the first and second amplifying units are canceled.

According to the third aspect of the present invention, the first and second amplifying units are formed adjacently on the same chip, have the same characteristics, and have the same offset voltage. The offset voltages of both amplifiers cancel each other, and the offset voltage of the amplifier is cancelled.

According to a fourth aspect of the present invention, there is provided the amplifier according to any one of the first to third aspects, and an internal circuit connected to an input terminal of the amplifier and outputting a signal to the amplifier. The output signal of the internal circuit is accurately output via the amplifier.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, an amplifier 1 includes first and second operational amplifier circuits 2,
3 are provided. The amplifier 1 has an external non-inverting input terminal 4, an external inverting input terminal 5, and an external output terminal 6.
Are provided, and signals IN1 and IN2 are input from both input terminals 4 and 5.
Is entered.

Each of the first and second operational amplifier circuits 2 and 3 has a non-inverting input terminal (+ side input terminal), an inverting input terminal (− side input terminal), and an output terminal. The first and second operational amplifier circuits 2 and 3 are connected in series.

That is, the output terminal of the first operational amplifier circuit 2 is connected to the non-inverting input terminal of the second operational amplifier circuit 3. In the first operational amplifier circuit 2, the output terminal is connected to the inverting input terminal, and the output signal is fed back to the inverting input terminal at the same magnification to form a voltage follower circuit (voltage follower circuit). First operational amplifier circuit 2
Is connected to the external inverting input terminal 5, and the first operational amplifier circuit 2 receives the signal IN1. The second operational amplifier circuit 3 has a non-inverting input terminal connected to the external non-inverting input terminal 4 and an output terminal connected to the external output terminal 6.

The operational amplifier circuits 2 and 3 have the same circuit configuration. For example, as shown in FIG. 3, each of the operational amplifier circuits 2 and 3 includes a bias voltage generation circuit 1
1, an input circuit 12, and an output circuit 13.

In the bias voltage generation circuit 11, the gate and the drain of the N-channel MOS transistor Tr1 have a resistance R
The transistor Tr1 is connected to a power supply Vcc via a ground 1 and a ground GND. Therefore, a bias voltage VB which becomes a constant voltage is output to the input circuit 12 and the output circuit 13 based on the ratio of the resistance value of the resistor R1 to the on-resistance of the transistor Tr1.

The input circuit 12 includes P-channel MOS transistors Tr2 and Tr3 and an N-channel MOS transistor Tr4.
To Tr6. The sources of the P-channel MOS transistors Tr2 and Tr3 are connected to the power supply Vcc. The drain of the transistor Tr1 is connected to the transistors Tr2 and Tr3.
And the drain of the N-channel MOS transistor Tr4. Further, the drain of the transistor Tr3 is connected to the drain of the N-channel MOS transistor Tr5. A signal is output to the output circuit 13 from the drains of the transistors Tr3 and Tr5.

The gates of the transistors Tr4 and Tr5 serve as a non-inverting input terminal and an inverting input terminal, respectively, to which a signal is input. A connection point between the sources of the transistors Tr4 and Tr5 is connected to the ground GND via the transistor Trs6. The bias voltage VB output from the bias voltage generation circuit 2 is input to the gate of the transistor Tr6, and the transistor Tr6 operates as a current source.

The output circuit 13 comprises a P-channel MOS transistor Tr7 and an N-channel MOS transistor Tr8. The source of the P-channel MOS transistor Tr7 is connected to the voltage Vcc, and the drain is connected to the ground GND via the transistor Tr8. A signal is input from the input circuit 12 to the gate of the transistor Tr7. The bias voltage VB output from the bias voltage generation circuit 11 is input to the gate of the transistor Tr8, and the transistor Tr8 operates as a current source. Then, the output signals of the operational amplifier circuits 2 and 3 are output from the drains of the transistors Tr7 and Tr8.

The operation of the amplifier 1 configured as described above will be described. For simplicity of explanation, the output terminal of the second operational amplifier circuit 3 is connected to the output terminal of the second operational amplifier circuit 3 inside the amplifier 1 as shown in FIG. Connect to inverting input terminal. A voltage follower circuit in which all output signals of the second operational amplifier circuit 3 are fed back to the first operational amplifier circuit 2 will be described.

The amplifier 1 configured as described above has the structure shown in FIG.
As shown in FIG. On the chip 7, first and second operational amplifier circuits 2 and 3 constituting the amplifier 1 are formed adjacent to each other. The two operational amplifier circuits 2 and 3 have the same configuration as described above, and the circuit elements constituting the circuit are formed in the same shape (area).

Therefore, the operational amplifier circuits 2 and 3 have the same electrical characteristics and the same variation. Therefore, the offset voltages generated in the operational amplifier circuits 2 and 3 are the same. Therefore, both operational amplifier circuits 2 and 3
As shown in (a) and (b), a power supply V1 that outputs an offset voltage ΔV is connected to an output terminal or an inverting input terminal for an ideal operational amplifier circuit (offset voltage is zero volt (0 V)) OP. It is equivalent to the circuit performed.

When the offset voltage ΔV is, for example, a positive voltage, the negative terminal of the power supply V1 is connected to the output terminal of an ideal operational amplifier OP as shown in FIG. The output signal of the operational amplifier circuit is boosted by the offset voltage ΔV by the power supply V1 and output as an output signal.

As shown in FIG. 7B, the power supply V1 has a negative terminal connected to the inverting input terminal of the ideal operational amplifier circuit OP and a positive terminal connected to the output terminal of the operational amplifier circuit. . Then, the output signal of the operational amplifier circuit is stepped down by the offset voltage ΔV by the power supply V1, and is fed back to the inverting input terminal.

FIGS. 7A and 7B show equivalent circuits when the offset voltage ΔV is positive. Therefore, when the offset voltage ΔV is negative, the connection of the power supply V1 that outputs the offset voltage ΔV is reversed. Then, FIG.
In, the output signal of the operational amplifier circuit is stepped down by the offset voltage ΔV by the power supply V1 and output.
In FIG. 7B, the output signal of the operational amplifier circuit is boosted by the offset voltage ΔV by the power supply V1 and is fed back to the inverting input terminal.

Therefore, the amplifier 1 shown in FIG.
As shown in FIG. 7, an ideal operational amplifier circuit OP having an output terminal connected to a power supply V1 (see FIG. 7A), and an ideal operational amplifier circuit O having an inverted input terminal connected to a power supply V1.
This is equivalent to a circuit in which P (see FIG. 7B) is connected in series.

Then, the output signal of the ideal operational amplifier OP constituting the first operational amplifier circuit 2 is the power supply V1
After the voltage is raised by the offset voltage ΔV, the voltage is lowered by the offset voltage ΔV
Is input to an inverting input terminal of an ideal operational amplifier circuit OP constituting the operational amplifier circuit 3 of FIG. That is, as shown in FIG. 6, the output signals of the operational amplifier circuits 2 and 3
As a result, the positive offset voltage ΔV and the negative offset voltage ΔV are superimposed and input to the inverting input terminal of the operational amplifier circuit. Since the offset voltages .DELTA.V of the two operational amplifier circuits 2 and 3 are the same, the offset voltages .DELTA.V cancel each other, so that the offset voltage of the amplifier 1 becomes zero volt (0 V) as shown in FIG.

Generally, when an operational amplifier having a small offset voltage is to be manufactured, the transistors constituting the operational amplifier become large and the chip area increases. In general, if the operational amplifier is made twice as large, the offset voltage becomes a half of the root (1 / √2). Therefore, if the offset voltage is set to almost zero (0), the chip area of the operational amplifier becomes enormous. And
Although the offset voltage becomes almost zero, temperature drift and the like cannot be avoided.

However, in this embodiment, the area is 2
Although it is doubled, the offset voltage becomes almost zero. Further, since the operational amplifier circuits 2 and 3 are formed on the same chip, they have the same temperature. Therefore, the temperature drift occurs in the two operational amplifier circuits 2 and 3 in the same manner, and is canceled in the same manner as the offset voltage. Therefore, according to the amplifier 1 of the present embodiment, the offset voltage and the temperature drift can be canceled, and the increase in the chip area and the cost can be suppressed.

In the above embodiment, the external output terminal 6 and the external inverting input terminal 5 in the amplifier 1 shown in FIG.
A similar effect can be obtained by configuring a voltage follower circuit by connecting That is, the amplifier 1 of FIG.
According to the equivalent circuits of the operational amplifier circuits 2 and 3 shown in FIGS. Then, the offset voltage ΔV is canceled by the power supply V1 of the operational amplifier circuits 2 and 3, and the offset and the temperature drift of the amplifier 1 are canceled.

Further, in the above embodiment, the amplifier 1 may have an amplification factor. That is, as shown in FIG. 9, a resistor R2 is connected between the external output terminal 6 and the external inverting input terminal 5 of the amplifier 1, and the external inverting input terminal 5 is connected to the ground GND via the resistor R3. Non-inverting amplifier 1
Is configured. When the ratio between the resistors R2 and R3 is appropriately set, for example, when the resistors R2 = 2KΩ and R3 = 1KΩ, the amplifier 1 can obtain an output signal that is in-phase with the input signal and tripled. Further, the resistors R2 and R3 are variable resistors so that the amplification factor can be adjusted. Also in this case, since the offset voltage of the amplifier 1 is zero volt, there is no need to connect an adjustment circuit for adjusting the offset voltage, and it is only necessary to add a resistor for setting the amplification factor. The amplifier 1 having the amplification factor can be obtained by the configuration.

The amplifier 1 constructed as described above
Can be applied to various circuits such as a semiconductor integrated circuit device having an internal circuit for outputting to the amplifier 1. For example, the amplifier 1 is used for a low-pass filter 21 as shown in FIG. Low-pass filter 21
Represents an amplifier 1, resistors R4 to R6 and a capacitor C1,
And an internal circuit 22 composed of C2. Amplifier 1
External non-inverting input terminal 4 is connected to ground GND,
A signal is input to the external inversion input terminal 5 via the resistors R4 and R5. The output signal of the amplifier 1 is fed back to the external inversion input terminal 5 via the capacitor C1. Ground GND between the resistors R4 and R5 via the capacitor C2.
And the output signal of the amplifier 1 is fed back via the resistor R6. And the low-pass filter 21
The signal passes only a predetermined low frequency band and is output as a signal. In this case, since the offset voltage in the amplifier 1 has been canceled, a signal in a low frequency band is output with high accuracy.

The amplifier 1 is used for a D / A converter 23 as shown in FIG. The D / A converter 23 includes the amplifier 1 and the internal circuit 24 including the resistors R11 to R18, the switches SW1 to SW4, and the reference power supply V2. The external output terminal 6 of the amplifier 1 is connected to the external inverting input terminal 5 to form a voltage follower circuit. The external non-inverting input terminal 4 of the amplifier 1
The resistors R11 to R13 having the same resistance connected in series and a resistor R18 having a resistance twice the resistance of the resistors R11 to R13 are connected to the ground GND. Each resistor R11 to R13, R
18, one end of each of resistors R14 to R17 having the same resistance value as the resistor R18 is connected between the resistor R11 and the amplifier 1, and the other end of each of the resistors R14 to R17 is connected to the switches SW1 to SW4. Have been. Switch SW1
The switching terminals of SW4 are connected to the ground GND and the reference power supply V2. And the D / A converter 2
3 divides the voltage of the reference power supply V2 supplied via switches SW1 to SW4 which are turned on / off in response to the input digital signal by resistors R11 to R18, and divides the divided voltage via the amplifier 1 Output as an analog signal. In this case, since the offset voltage in the amplifier 1 has been canceled, the divided voltage is accurately output as an analog signal.

Further, the amplifier 1 described above has the configuration shown in FIG.
It is used for the A / D converter shown in FIG. FIG.
As shown in FIG. 1A, the A / D converter includes a plurality of amplifiers 1 and internal circuits including resistors R21 to R24, flip-flop circuits (FF) 26 to 28, and logic circuits 29 and 30. You. The resistors R21 to R24 are
It is connected in series between the high potential side reference power supply VRH and the low potential side reference power supply VRL. Each of the resistors R21 to R24 is connected to an external inverting input terminal 5 (see FIG. 12B) of each amplifier 1, and an analog signal AIN is input to an external non-inverting input terminal 4 of each amplifier 1. Accordingly, the amplifier 1 includes an analog signal AIN and a plurality of resistors R21 to R21 connected between the high-potential-side reference power supply VRH and the low-potential-side reference power supply VRL.
It operates as a comparator for comparing the divided voltage of the voltage dividing circuit consisting of R24 with each other. Then, based on the comparison result of each amplifier 1, the FFs 26 to 28 and the logic circuit 2
A digital signal is output via 9, 30. In this case, since the offset voltage in each comparator (each amplifier 1) has been canceled, the analog signal AIN
And the divided voltage are compared with high accuracy, and an accurate digital signal is output.

As described above, the present embodiment has the following advantages. (1) The amplifier 1 has first and second operational amplifier circuits 2,
3 are provided. The first operational amplifier circuit 2 forms a voltage follower circuit having an output terminal connected to the inverting input terminal, and has an output terminal connected to the inverting input terminal of the second operational amplifier circuit 3. The first and second operational amplifier circuits 2 and 3 have the same circuit configuration and circuit elements,
It has the same characteristics and the same offset voltage. as a result,
By connecting the output terminal of the first operational amplifier circuit 2 to the inverting input terminal of the second operational amplifier circuit 3, the offset voltages of the first and second operational amplifier circuits 2 and 3 cancel each other. The voltage is canceled.

The present invention may be carried out in the following modes in addition to the above embodiment. In the above embodiment,
Although the second operational amplifier circuits 2 and 3 are configured by CMOS circuits, they may be implemented by appropriately changing the circuit configuration to a bipolar integrated circuit, a Bi-CMOS circuit, or the like.

In addition to the voltage follower circuit (buffer) and the non-inverting amplifier, the amplifier 1 is used to configure an amplifier such as an inverting amplifier and a differential amplifier, and an arithmetic unit such as an adder circuit and an integrator using the amplifier 1. I do. Also in this case, since the offset voltage of the amplifier is canceled, a highly accurate amplifier, arithmetic unit, and the like can be configured.

[0043]

As described above, according to the first to third aspects of the present invention, it is possible to provide an amplifier capable of canceling an offset voltage and a temperature drift.

According to the fourth aspect of the present invention, it is possible to provide a semiconductor integrated circuit device including an amplifier whose offset voltage is canceled and capable of outputting an output signal of an internal circuit with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of an amplifier according to an embodiment.

FIG. 2 is an equivalent circuit diagram of the amplifier in FIG. 1;

FIG. 3 is a circuit diagram of first and second operational amplifier circuits.

FIG. 4 is an operation waveform diagram of first and second operational amplifier circuits.

FIG. 5 is a circuit diagram for explaining the operation of the amplifier.

6 is an equivalent circuit diagram of FIG.

FIGS. 7A and 7B are equivalent circuit diagrams of an operational amplifier circuit.

FIG. 8 is a schematic plan view showing an amplifier chip.

FIG. 9 is a block circuit diagram of another amplifier.

FIG. 10 is a circuit diagram showing an example applied to a low-pass filter.

FIG. 11 is a circuit diagram showing an example applied to a D / A converter.

FIGS. 12A and 12B are circuit diagrams showing examples applied to an A / D converter.

FIG. 13 is a circuit diagram of a conventional operational amplifier circuit.

14A and 14B are waveform diagrams showing offsets of a conventional operational amplifier circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 amplifier 2 first operational amplifier circuit as first amplifier 3 second operational amplifier circuit as second amplifier

Claims (4)

[Claims] A first amplifier having an inverting input terminal and a non-inverting input terminal and having an output terminal and an inverting input terminal connected thereto; and a circuit configuration and a circuit element identical to the first amplifier. And a second amplifying unit, wherein a signal from an output terminal of the first amplifying unit is input to an inverting input terminal. 2. An output terminal of the second amplifying unit is connected to the first amplifying unit.
2. The amplifier according to claim 1, wherein said amplifier is connected to a non-inverting input terminal of said amplifying section, and said first and second amplifying sections constitute a non-inverting amplifier. 3. The amplifier according to claim 1, wherein the first and second amplifiers are formed adjacently on the same chip. 4. A semiconductor integrated circuit device comprising: the amplifier according to claim 1; and an internal circuit connected to an input terminal of the amplifier and outputting a signal to the amplifier.