JP2884896B2 - Differential operational amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fully differential operational amplifier formed on a MOS integrated circuit, and more particularly to an operational amplifier having a common-mode feedback circuit effective for a Holded Cascode type operational amplifier having a high output impedance. .

[0002]

2. Description of the Related Art A fully differential operational amplifier requires a common-mode feedback circuit to stabilize a DC operating point of a differential output. FIG. 3 shows an example of a fully differential operational amplifier including a common-mode feedback circuit. 3, reference numerals 71 to 75 denote n-channel transistors, 76 to 79 denote p-channel transistors, and CC1 and CC2.
Is a phase compensation capacitance, R3 and R4 are resistors, IP and IM are positive and negative input terminals for amplification, Vb10 is a bias input terminal, OP is a positive output terminal, and OM is a negative output terminal. This circuit is a general two-stage operational amplifier that obtains a differential output by amplifying the output of a differential pair by a common-source amplifier circuit.

Assuming that the resistors R3 and R4 are not provided and a constant bias is applied to the gates of the transistors 74 and 75, the gain of the operational amplifier with respect to the in-phase input becomes a very high value. As a result, the input terminal I
Even if a small common-mode input is applied to P and IM, the output greatly fluctuates, and the DC operating point of the output is not stable.

The gain for the common mode input is suppressed,
A circuit for stabilizing the output DC operating point is a common-mode feedback circuit. In the case of the circuit of FIG. 3, the differential output O is obtained by the resistors R3 and R4.
A common-mode feedback circuit is realized by detecting the midpoint voltage of P and OM and feeding back the midpoint voltage to the gates of the output stage current source transistors 74 and 75.

A method of directly dividing a differential output by an impedance such as a resistor as shown in FIG. 3 and feeding it back has an advantage that a common-mode feedback circuit can be realized with a simple circuit configuration.
Since a load is directly applied between the differential outputs, a negative feedback circuit is formed for the differential signal, which causes a decrease in open loop gain and a deterioration in frequency characteristics. In order to prevent such deterioration, it is necessary to make the resistance value of the resistance voltage dividing circuit sufficiently larger than the output impedance of the operational amplifier.

However, the above-mentioned common-mode feedback circuit has been used in recent years for a high-speed switched capacitor circuit or the like.
code-type operational amplifier (R.GREGORIAN and G.TEMES, JOHN
Published by WILEY & SONS, ANALOG MOS INTEGRATED CIRCUITS F
OR SIGNAL PROCESSING See page 255. ) Cannot be used for an operational amplifier having a high output impedance.

[0007] FIG. 4 is a diagram showing the Holded method disclosed in the above-mentioned reference example.
3 shows a Cascode-type operational amplifier. The output impedance of a Holded Cascode type operational amplifier is about several MΩ,
Compared to an OS operational amplifier (such as a two-stage operational amplifier with a grounded source output as shown in FIG. 3), the output impedance is higher by about three digits. Therefore, a common-mode feedback circuit as shown in FIG. 3 cannot be used.

As an example using the circuit of FIG.
R.NORSWORTHY et al. "A 14bit 80kHz Sigma-Delta A / D Con
verter: Modeling, Design, and Performance Evaluatio
n ", IEEE Jour. of Solid-State Circuits, Vol.24, No.
2, 1989, pp256-266, D.SALLAERT et al. "A single-Chip
U-Interface Transceiver for ISDN ", IEEE Jour.of So
lid-State Circuits, vol.22, No.6, 1987, pp1011-102
There is 1 mag.

Next, the Holded Cascode type operational amplifier shown in FIG. 4 will be described.

In the figure, 81 to 87 are n-channel transistors,
88 to 93 are p-channel transistors, Vb9 to Vb12 are bias voltage input terminals, IP and IM are the positive and negative input terminals of the operational amplifier, respectively, and OP and OM are the positive output terminal and the negative output terminal of the operational amplifier, respectively. . As aforementioned,
Since the output impedance of the held cascode operational amplifier is very high, it is difficult to directly connect a load between the differential outputs. Therefore, in FIG. 4, a common-mode feedback circuit is configured by directly feeding back the differential output to the gates of the two current source transistors 92 and 93 whose drains are commonly connected. In this case, the differential output appearing between the terminals OP and OM is subjected to voltage-current conversion by the transistors 92 and 93, and current addition is performed at the drains of the transistors 92 and 93.
As a result, the differential output voltages are equivalently added and fed back to the current source, and the DC operating point is stabilized.

[0011]

In a conventional Holded Cascode type operational amplifier using a common-mode feedback circuit, the output voltage is directly fed back to the gate of the current source transistor. There is a disadvantage that the output dynamic range is narrow because there is a cutoff region. There is also a problem that large common-mode noise is generated due to the influence of the non-linearity of the current source.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an operational operational amplifier using a common-mode feedback circuit having a wide output dynamic range and a small common-mode noise.

[0013]

A differential operational amplifier according to the present invention comprises a differential amplifier, two buffer circuits for inputting differential outputs of the differential operational amplifier, and the two buffers. A voltage dividing circuit that divides an output of the circuit to output a midpoint potential; and a circuit that amplifies a difference between an output of the voltage dividing circuit and a reference voltage and feeds back to a gate of a current source transistor of the differential amplifier circuit. , The buffer circuit has a gain of 1 or less.
The two buffer circuits each have a source connected to a first power supply, a gate connected to a corresponding differential output terminal of the differential amplifier circuit, and a drain connected to the voltage dividing circuit. A first connected p-channel transistor;
A first n-channel transistor having a source connected to the second power supply, a gate connected to the corresponding differential output terminal, a drain connected to the voltage dividing circuit, and a gate and a drain connected to the voltage dividing circuit A second p-channel transistor having a source connected to the first power supply; and a second n-channel transistor having a gate and drain connected to the voltage dividing circuit and a source connected to the second power supply. Is done.

In the above configuration, for example, the first power supply is set to the power supply voltage Vdd, the second power supply is set to the ground voltage GND, and the first p-channel transistor and the first n-channel transistor forming one buffer circuit Is connected to the positive output terminal, and the gates of the first p-channel transistor and the first n-channel transistor forming the other buffer circuit are connected to the negative output terminal. The second p-channel transistor and the second n-channel transistor are each diode-connected.

[0015]

According to the present invention, each buffer circuit has a CMO
This is an inversion buffer combining an S inverter and a diode-connected MOS transistor, and can realize a common-mode feedback circuit operable in the entire power supply voltage range. Further, since the midpoint potential of the differential output is fed back to the current source transistor, the influence of the nonlinearity of the buffer circuit is small. Further, since the reference voltage is used, a change in the DC operating point due to a process change can be suppressed.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, a first embodiment of the present invention will be described with reference to FIG. In FIG. 1, reference numerals 1 to 7 and 1
2 to 20 are n-channel transistors, 8 to 11 and 29
28 to 28 are p-channel transistors, R1 and R2 are resistors, CL1 and CL2 are load capacitors, Vb1 to Vb4 are bias voltage input terminals, VR is a reference voltage input terminal, IP and I
M indicates a positive input terminal and a negative input terminal of the operational amplifier, respectively, and OP and OM indicate a positive output terminal and a negative output terminal of the operational amplifier, respectively.

In the circuit shown in FIG. 1, transistors 1 to 11 constitute an ordinary Holded Cascode type operational amplifier shown in FIG. 4, and transistors 12 to 28 and resistors R1 and R2 constitute an in-phase feedback circuit.

This common mode feedback circuit includes a transistor 12,
A first inversion buffer circuit composed of transistors 21, 13, 22; a second inversion buffer circuit composed of transistors 17, 25, 18, 26;
A third inverting buffer circuit constituted by 19 and 27, a differential pair constituted by transistors 14-16, 23 and 24, and a resistor voltage dividing circuit constituted by resistors R1 and R2.

The first inverting buffer circuit includes CMOS inverters 12 and 21 connected between a power supply voltage Vdd and a ground voltage GND, and diode-connected n-channel transistors 13 and p-channel transistors 22 which load the CMOS inverters. It is composed of CMOS
The reference voltage VR is supplied to the gates of the transistors 12 and 21 constituting the inverter.

The second inversion buffer circuit has a power supply voltage Vd
CMOS inverters 17 and 25 connected between d and the ground voltage GND, and diode-connected n-channel transistors 18 and p-channel transistors 26 serving as loads on the CMOS inverters. The gates of the transistors 17 and 25 constituting the CMOS inverter are connected to the positive output terminal OP.

The third inversion buffer circuit has a power supply voltage Vd
CMOS inverters 20 and 28 connected between d and ground voltage GND, and diode-connected n-channel transistors 19 and p-channel transistors 27 serving as loads on the CMOS inverters. The negative output terminal OM is connected to the gates of the transistors 20 and 28 constituting the CMOS inverter.

The resistance voltage dividing circuits R1 and R2 are connected between the output points of the second and third inverting buffer circuits.

The output of the first inverting buffer circuit is connected to the gates of transistors 15 forming a differential pair by resistors R1 and R2.
Are respectively connected to the gates of the transistors 16 forming a differential pair. The voltage Vb4 is applied to the gate of the transistor 14. The output of the differential pair is
Current source transistor 1 of Holded Cascode type operational amplifier
0, 11 are applied to the gates.

Next, the operation of the operational amplifier configured as described above will be described.

In the configuration shown in FIG. 1, the gain and threshold voltage of each inversion buffer are determined by the size of four transistors constituting the inversion buffer. In this embodiment, the gain is 1 or less, and the threshold voltage is substantially Vdd /
The size of the transistor is selected to be 2. By setting the gain of the inverting buffer to 1 or less, it is possible to configure a buffer whose output is not saturated with respect to the input in the entire power supply voltage range.

The second inversion buffer circuit inverts and amplifies the positive output of the operational amplifier and outputs the result. The third inversion buffer circuit inverts and amplifies the negative output of the operational amplifier and outputs the result. By connecting the resistance voltage dividing circuits R1 and R2 between the output terminals OP and OM via the second and third inversion buffers, the midpoint potential can be detected without deteriorating the characteristics of the operational amplifier.

The reference voltage VR is a reference voltage that gives a DC operating point of the operational amplifier, and this reference voltage is input to the differential pair via the first inversion buffer. With this differential pair,
The outputs of the resistive voltage dividing circuits R1 and R2 (the potential at the connection point of R1 and R2) are compared with the reference voltage VR via the first inverting buffer, and a voltage obtained by inverting and amplifying the difference is output. The output of this differential pair is the current source transistor 10, 1 of the operational amplifier.
1 and the DC operating point is stabilized.

The reason why the reference voltage VR is used is to suppress the fluctuation of the DC operating point due to the process fluctuation. The reason why the first inversion buffers 12, 13, 21, and 22 are arranged between the reference voltage VR and the differential pairs 14-16, 23, and 24 is that the second and third inversion buffers 17-20, 25
This is for removing the offset generated at -28.

Next, a second embodiment of the present invention will be described. FIG. 2 shows an example in which the resistance voltage dividing resistance of FIG. 1 is realized by using the ON resistance of a MOS transistor. In the figure, 49,
50 is an n-channel transistor, 59 and 60 are p-channel transistors, and these four transistors constitute a voltage dividing circuit. The reason why the n-channel transistor and the p-channel transistor are connected in parallel is to cancel the voltage dependence of the on-resistance. By using a MOS transistor instead of a resistor as described above, a high resistance can be realized with a small area, and the common-mode feedback circuit can be downsized.

In the first and second embodiments, Holded Casc
Although the example in which the present invention is applied to the ode type operational amplifier is shown, the present invention may be applied to other fully differential operational amplifiers. For example, the low-power-consumption type two-stage operational amplifier shown in FIG. 3 has a high output impedance. By using the common-mode feedback circuit according to the present invention, it is possible to prevent characteristic deterioration due to connection of the common-mode feedback circuit.

Next, the operation of the present invention will be described using simulation results. FIG. 5 shows a circuit configuration of the fully differential inverting amplifier. In the figure, 100 is a fully differential operational amplifier, R5 to R8.
Indicates a resistance. As described above, since the output impedance of the Holded Cascode type operational amplifier is very high, it is hardly used for such a resistance feedback type circuit. Therefore, using the circuit of FIG. 5 to confirm the characteristics,
The simulation was performed with all the resistance values being 100 MΩ so as not to be affected by the output impedance.

FIGS. 6 and 7 show the DC input / output characteristics of the operational amplifier of the conventional example (FIG. 4) and the operational amplifier of the present application (FIG. 1), respectively. In the figure, OP and OM indicate a positive output and a negative output of the operational amplifier, respectively, and OP-OM indicates a differential output.

As is apparent from FIGS. 6 and 7, the characteristic shown in FIG. 7 has a wider output operation range than the characteristic of the conventional example shown in FIG. Also, comparing the linearity of OP and OM, it is understood that the present invention is superior. The effect of this non-linearity manifests itself in the form of common mode noise.

FIGS. 8 and 9 show the results of simulation of common-mode noise by adding a differential sine wave input to the circuit of FIG. FIG. 8 shows a simulation result when the conventional (FIG. 4) operational amplifier is used, and FIG. 9 shows a simulation result when the operational amplifier of the present application (FIG. 1) is used. O in the figure
P and OM indicate the positive output and the negative output of the operational amplifier, respectively, and COM indicates the common-mode noise (the midpoint waveform of OP and OM).

As is clear from FIGS. 8 and 9, the common mode noise COM of the present invention shown in FIG. 9 is smaller than the common mode noise COM of the conventional example shown in FIG. In the case of a fully differential circuit, this common mode noise is ideally not a problem. However, considering the signal path due to the parasitic capacitance or the like, the symmetry of the fully differential circuit is not completely maintained, and the common-mode noise becomes the opposite-phase noise due to the wraparound or the like, thereby deteriorating the S / N of the circuit. Since such effects depend on the circuit configuration, layout, etc.,
Although it cannot be expressed quantitatively, it is better to reduce even in-phase noise as much as possible. In this respect, the present invention is superior to the conventional example.

FIG. 10 shows the results of simulating the DC input / output characteristics of the operational amplifier of the second embodiment shown in FIG. 2 of the present invention, and shows that the same characteristics as those of the first embodiment can be obtained. I have.

[0038]

As described above, the present invention relates to a CMOS.
By using an inversion buffer combining an inverter and a MOS transistor diode-connected, a common-mode feedback circuit operable in the entire power supply voltage range can be realized. As a result, there is an effect that the differential output range of the operational amplifier is increased as compared with the related art. In the related art, a large common-mode noise is generated due to the non-linearity of the current source transistor. However, in the present invention, since the midpoint potential of the differential output is fed back to the current source transistor, the influence of the non-linearity is small. In the case of the present invention, common-mode noise is generated due to the influence of the nonlinearity of the inverting buffer, but the value is sufficiently smaller than the conventional common-mode noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a held cascode type operational amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a held cascode operational amplifier according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a conventional two-stage operational amplifier.

FIG. 4 is a circuit diagram showing a configuration of a conventional Holded Cascode type operational amplifier.

FIG. 5 is a circuit diagram of a conventional fully differential inverting amplifier circuit.

FIG. 6 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG. 4;

FIG. 7 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG. 1;

FIG. 8 is a graph showing a simulation result of common mode noise of the operational amplifier of FIG. 4;

FIG. 9 is a graph showing a simulation result of common mode noise of the operational amplifier of FIG. 1;

FIG. 10 is a graph showing a simulation result of DC input / output characteristics of the operational amplifier of FIG. 2;

[Explanation of symbols]

IP; Positive input terminal IM; Negative input terminal OP; Positive output terminal OM; Negative output terminal VR; Reference voltage input terminal Vb1 to Vb12; Bias voltage input terminal CL1 to CL6; Load capacitance R1 to R8; Resistance INP; Positive input INM Negative inputs 1 to 7, 12 to 20, 31 to 37, 42 to 52, 71 to
75, 81-87; n-channel transistors 8-11, 21-28, 38-41, 53-62, 76
-79, 88-93; p-channel transistor 100; fully differential operational amplifier

Claims (1)

(57) [Claims] 1. A differential amplifier circuit, two buffer circuits for inputting differential outputs of the differential amplifier circuit, and a voltage divider for dividing an output of the two buffer circuits to output a midpoint potential. And a circuit for amplifying a difference between an output of the voltage dividing circuit and a reference voltage and feeding back to a gate of a current source transistor of the differential amplifier circuit, wherein the buffer circuit is an inverting buffer having a gain of 1 or less.
The two buffer circuits each have a source connected to a first power supply, a gate connected to a corresponding differential output terminal of the differential amplifier circuit, and a drain connected to the voltage dividing circuit. 1
A first n-channel transistor having a source connected to the second power supply, a gate connected to the corresponding differential output terminal, and a drain connected to the voltage dividing circuit; Connected to the voltage divider circuit,
A second p-channel transistor having a source connected to the first power supply, and a second n-channel transistor having a gate and a drain connected to the voltage dividing circuit and a source connected to the second power supply A differential operational amplifier, characterized in that: