JPH1012736A - Planarizatioh for manufacturing integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high quality O3 /TEOS film and grow a uniform film by forming a silicon borophosphate glass layer, an oxide layer and a metal layer on a semiconductor substrate and forming the O3 /TEOS film on the metal layer. SOLUTION: A silicon borophosphate glass layer 4 is formed on a semiconductor substrate 2. Using a reactive gas of SiH4 , an oxide layer 6 is formed to cover the glass layer 4 by the plasma CVD. A metal layer 8 is formed to cover the oxide film 6. A lithography step is run to dislocate a metal wiring pattern on a photo mask to a photo resist, the metal layer not covered with the photo mask is removed by dry etching and photo resist is removed. An O3 /TEOS film 10 is formed on the layers 6 and 8, thereby obtaining a high quality O3 / TEOS film and uniformly grown film. This eliminates the need for chemical- mechanical polishing of following oxide layer and enhance the production ability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for planarizing an integrated circuit, and more particularly, to a method for planarizing a dielectric layer applied to the production of a very large integrated circuit.

[0002]

2. Description of the Related Art After a planarized dielectric layer does not have a drastic height drop, the subsequent fabrication of wiring in metal can be performed relatively easily and the pattern of the transition is also relatively accurate. Becomes Silicon borate glass (BPSG)
Is a type of pre-metallized isolating dielectric material commonly used today. General planarization methods include O ₃ / TEOS, SO
G method (spin on glass), chemical mechanical polishing method (CMP, chemical mechanical)
polishing).

[0003] A conventional method of planarizing a metal wiring dielectric layer in O ₃ / TEOS is to form a BPSG layer 3 on a semiconductor substrate 1, cover the BPSG layer 3 with a metal layer 5, and further use a lithography technique. The wiring pattern in the metal on the photomask is transferred onto the photoresist by using, and the photoresist is removed by removing the metal layer which is not yet covered by the dry etching method.
One oxide layer 7 is deposited on the metal layer 5 and the BPSG layer 3 by the E-SiH ₄ method (see FIG. 1). Then O ₃ /
A TEOS layer 9 is formed on the oxide layer 7 (see FIG. 2).

Generally, O formed by plasma CVD is used.
O ₃ / TEO on ₃ / TEOS oxide layer (oxide)
The deposition rate of the S layer is very low and the thermal oxide layer (therma
The deposition rate of the O ₃ / TEOS layer on the oxide is also very slow (see FIG. 3). In addition, T by plasma CVD
An O ₃ / TEOS layer formed on the EOS oxide layer, and
The wet etching rate for the O ₃ / TEOS layer formed on the thermal oxide layer is very high (see FIG. 4). Therefore, when the O ₃ / TEOS layer is formed on both, the quality of the thin film layer is very poor. As shown in FIGS. 1 and 2, an oxide layer (PESi) formed by plasma CVD using SiH ₄ as a reaction gas.
O ₃ / TEOS on H ₄ , oxide) provides a relatively good growth rate, and the rate of wet etching is much higher than the TEOS oxide layer (PET) by plasma CVD.
EOS oxide or thermal oxide layer (therm)
Aloxide) was better than O ₃ / TEOS formed on it. However, when an oxide layer formed by plasma CVD using SiH ₄ as a reaction gas is formed on a metal layer, the rate at which an O ₃ / TEOS layer is further deposited on the oxide layer becomes non-uniform, The difference between the center and the periphery of the wafer became larger. And if, evenly O ₃
In order to form the / TEOS layer, the ratio of the reaction gas at the time of forming the O ₃ / TEOS layer had to be reduced, and the quality of the O ₃ / TEOS layer was sacrificed.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide an
The favorable growth rate of the O ₃ / TEOS layer on the oxide layer (PESiH ₄ oxide) formed by plasma CVD using H ₄ as a reaction gas, and the wet etching rate of the O ₃ / TEOS layer by TEOS oxidation by plasma CVD Utilizing the fact that it is faster than that for the O ₃ / TEOS layer formed on the layer or thermal oxide layer, a good deposition rate and a high quality O ₃ / TEOS thin film can be obtained by using silicon borophosphate glass (BPSG). It is to form on.

In the present invention, after forming a semiconductor device, a silicon borophosphate glass layer (BPSG) is formed on a substrate, and then an oxide layer is formed by plasma CVD using SiH ₄ as a reaction gas. Overlying, followed by forming a metal layer over the oxide layer and overlying O ₃ over the metal layer
/ TEOS layer is formed.

[0007]

According to the first aspect of the present invention, a silicon borophosphate glass layer (BPSG) is formed on a semiconductor substrate, and then an oxide layer is formed on the silicon borophosphate glass layer. Subsequently, a metal layer is formed on the oxide layer, and an O ₃ / TEOS layer is formed on the metal layer.

According to a second aspect of the present invention, there is provided a planarization method for manufacturing an integrated circuit according to the first aspect, wherein the oxide layer is formed of S
formed by plasma CVD to iH ₄ as a reaction gas, and a planarization method in integrated circuit fabrication.

According to a third aspect of the present invention, there is provided the planarization method for manufacturing an integrated circuit according to the first aspect, wherein the thickness of the oxide layer is set to be 500 to 5,000 angstroms. .

According to a fourth aspect of the present invention, there is provided the planarization method for manufacturing an integrated circuit according to the first aspect, wherein the etching is further performed by a lithography technique before forming the metal layer. And how to do it.

According to a fifth aspect of the present invention, there is provided a planarization method for manufacturing an integrated circuit according to the fourth aspect, wherein the photoresist is further removed after forming the metal layer. I have.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Please refer to FIG. 3 and FIG. O
₃ / TEOS and plasma C using SiH ₄ as a reaction gas
When formed on an oxide layer (PESiH ₄ oxide) formed by VD, a good growth rate can be obtained, and the O
₃ / The wet etching rate for the TEOS layer is determined by the TEOS oxide layer (PE TEOS oxi
de) or thermal oxide layer
Faster than for the O ₃ / TEOS layer formed above.

In the method for planarizing a metal wiring dielectric layer in O ₃ / TEOS according to the present invention, first, a silicon borophosphate glass layer 4 (BPSG) is formed on a semiconductor substrate 2,
The H ₄ to form an oxide layer 6 in Burazuma CVD該硼phosphorus coated with acid silicon glass layer 4 as a reaction gas, the thickness is set to 500 to 5000 angstroms (see Fig. 5). Subsequently, a metal layer 8 is formed to cover the oxide layer 6, a lithography process is performed, a wiring pattern in the metal on the photomask is transferred onto the photoresist, and the metal not covered by the photomask is dry-etched. The layer is removed, and the photoresist is removed (see FIG. 5).
Subsequently, an O ₃ / TEOS layer 10 is formed on the oxide layer 6 and the metal layer 8 to obtain a state shown in FIG.

[0014]

According to the present invention, an oxide layer (PESiH ₄ oxi) formed by plasma CVD using SiH ₄ as a reaction gas.
de) and good growth rate of _O 3 / TEOS layer on the above by utilizing the wet etching speed to the _O 3 / TEOS layer is good, high quality _O 3 / TEOS layer and a uniform thin film The growth is obtained, so that the subsequent chemical mechanical polishing of the oxide layer is not required, and the production capacity can be increased.

[Brief description of the drawings]

FIG. 1 shows a conventional method for planarizing a dielectric layer of an integrated circuit.
The metal layer and the oxide layer are formed by a silicon borate glass layer (BPS).
It is an explanatory view of a step formed on G).

FIG. 2 shows a method of FIG.
FIG. 3 is an explanatory view showing steps for forming ₃ / TEOS.

FIG. 3 is a comparison diagram of formation rates of O ₃ / TEOS on different thin films.

FIG. 4 is a comparison diagram of wet etching rates for O ₃ / TEOS formed on different thin films.

FIG. 5 is an explanatory view showing a step of forming a metal layer and an oxide layer on a silicon borophosphate glass layer (BPSG) in the method of the present invention.

FIG. 6 is an explanatory view of a step of forming O ₃ / TEOS on a metal layer and an oxide layer in the method of the present invention.

[Explanation of symbols]

1 ... semiconductor substrate 3 ... the boron phosphate silicon glass layer (BPSG layer) 5 ... metal layer 7: Oxidized layer 9 ... _O 3 / TE
OS layer 2 ... Semiconductor substrate 4 ... Silicon borophosphate glass layer 6 ... Oxide layer 8 ... Metal layer 10 ... O ₃ / T
EOS layer

Claims (5)

[Claims] Forming a silicon borate glass layer (BPSG) on a semiconductor substrate, forming an oxide layer on the silicon borate glass layer, and forming a metal layer on the oxide layer; Forming and forming an O ₃ / TEOS layer on the metal layer. 2. The method according to claim 1, wherein the oxide layer is formed by plasma CVD using SiH ₄ as a reaction gas. 3. The method of claim 1, wherein said oxide layer has a thickness of 500-500.
A flattening method in integrated circuit manufacturing, which has a thickness of 0 Å. 4. The method according to claim 1, wherein, prior to forming the metal layer, etching is further performed by a lithography technique. 5. The method according to claim 4, wherein, after forming the metal layer, the photoresist is further removed.