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JPH07153840A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH07153840A
JPH07153840A JP32333693A JP32333693A JPH07153840A JP H07153840 A JPH07153840 A JP H07153840A JP 32333693 A JP32333693 A JP 32333693A JP 32333693 A JP32333693 A JP 32333693A JP H07153840 A JPH07153840 A JP H07153840A
Authority
JP
Japan
Prior art keywords
film
insulating film
ozone
plasma
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32333693A
Other languages
Japanese (ja)
Inventor
Toru Kubo
亨 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32333693A priority Critical patent/JPH07153840A/en
Publication of JPH07153840A publication Critical patent/JPH07153840A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To simplify the foaming process of an ozone TEOS film as an interlayer insulating film, and obtain a semiconductor device whose film quality is improved and its manufacturing method. CONSTITUTION:On a silicon substrate 1, a BPSG film 2 as a first base insulating film is formed, and thereon a plasma silicon film 3 as a second base insulating film is formed by a silane plasma CVD method. After an aluminum wiring 4 having a necessary pattern is formed on the base insulating film 3, a silicon oxide film (ozone TEOS film) 5 is formed by a high ozone concentration organic silane.ozone based normal pressure CVD method. An organic silica film is stuck to the silicon oxide film 5, and the surface is flattened by etch back. A silicon oxide film (plasma TEOS film) 7 is formed on the flattened ozone TEOS film 5 by an organic silane CVD method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は下値絶縁膜上に形成され
た配線上に層間絶縁膜が形成されている半導体装置に関
し、特にその下値絶縁膜と層間絶縁膜の構造およびその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an interlayer insulating film is formed on a wiring formed on a lower insulating film, and more particularly to a structure of the lower insulating film and the interlayer insulating film and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来の高集積化を図った半導体装置で
は、下値絶縁膜上に配線が形成され、この配線上に層間
絶縁膜が形成されて更に上層の配線が形成される多層配
線構造が採用されている。この層間絶縁膜としては、ケ
イ酸エチル(Si(OC2 5 4 :以下、TEOSと
称する)とオゾンを原料とする常圧化学気相成長(CV
D)法を用いて形成した酸化シリコン膜(以下、オゾン
テオス膜と称する)が用いられている。このオゾンテオ
ス膜は、下地絶縁膜がポリシリコン(多結晶シリコン)
膜の場合は表面の平坦性に優れているが、下地絶縁膜が
熱酸化膜の場合は表面に凹凸が生じる場合がある。ま
た、このオゾンテオス膜は形成時のオゾン濃度が高い
程、下地の配線を構成するアルミニウムの影響を受けて
表面の凹凸の差は大きくなる傾向にある。このため、オ
ゾンテオス膜の凹凸表面上に形成した配線にストレスが
かかり、断線等が生じ易くなって信頼性が劣化すること
がある。
2. Description of the Related Art In a conventional semiconductor device having high integration, a wiring is formed on a lower insulating film, and an interlayer insulating film is formed on the lower insulating film to form an upper wiring. Has been adopted. As this interlayer insulating film, there is used atmospheric pressure chemical vapor deposition (CV) using ethyl silicate (Si (OC 2 H 5 ) 4 : hereinafter referred to as TEOS) and ozone.
A silicon oxide film (hereinafter referred to as an ozone TEOS film) formed by using the method D) is used. In this ozone TEOS film, the underlying insulating film is polysilicon (polycrystalline silicon).
The film is excellent in flatness of the surface, but when the underlying insulating film is a thermal oxide film, unevenness may occur on the surface. Further, the higher the ozone concentration at the time of forming the ozone TEOS film, the larger the difference in the unevenness of the surface tends to be due to the influence of aluminum forming the underlying wiring. Therefore, stress is applied to the wiring formed on the uneven surface of the ozone TEOS film, and disconnection or the like is likely to occur, which may deteriorate reliability.

【0003】このため、特開平3−198340号公報
では、オゾンテオス膜の表面の平坦化を図った層間絶縁
膜の製造方法が提案されている。この方法を図4に示
す。まず、図4(a)に示すようにシリコン基板11を
熱処理してその表面にゲート酸化膜12を0.02μm
形成し、その上にCVD法によりポリシリコンを堆積し
た後、パターニングしてゲート電極等を構成するポリシ
リコン膜13を形成する。次に、図4(b)のように、
オゾン濃度を1%程度に設定して、オゾンテオス膜(1
%)14を0.1μm堆積する。この膜厚は前記ゲート
酸化膜12を被覆する程度でよい。次に、オゾン濃度を
5%程度に上げ、図4(c)に示すようにオゾンテオス
膜(5%)15を0.6μm堆積する。この膜厚は層間
絶縁膜として必要な厚さとする。
For this reason, Japanese Patent Laid-Open No. 3-198340 proposes a method of manufacturing an interlayer insulating film in which the surface of the ozone TEOS film is flattened. This method is shown in FIG. First, as shown in FIG. 4A, the silicon substrate 11 is heat-treated to form a gate oxide film 12 of 0.02 μm on its surface.
After being formed and polysilicon is deposited thereon by the CVD method, patterning is performed to form a polysilicon film 13 constituting a gate electrode and the like. Next, as shown in FIG.
Set the ozone concentration to about 1% and set the ozone TEOS film (1
%) 14 is deposited to a thickness of 0.1 μm. This film thickness may be such that it covers the gate oxide film 12. Next, the ozone concentration is increased to about 5%, and an ozone TEOS film (5%) 15 is deposited to 0.6 μm as shown in FIG. This film thickness is a thickness necessary for the interlayer insulating film.

【0004】このように形成される層間絶縁膜では、オ
ゾンテオス膜のオゾン濃度を高くしても下地のゲート酸
化膜12はオゾンテオス膜(1%)14によって、完全
に被覆されているので、ゲート酸化膜12の影響は殆ど
なく、オゾンテオス膜(5%)15の表面には凹凸は殆
ど現れない。また、オゾンテオス膜(5%)15は、ポ
リシリコン膜13の段差の角部の堆積形状がフロー形状
であって、カバレッジが極めて良好で、かつ吸湿性が少
ない良好な膜質をもっている。
In the interlayer insulating film thus formed, even if the ozone concentration of the ozone TEOS film is increased, the underlying gate oxide film 12 is completely covered with the ozone TEOS film (1%) 14. There is almost no influence of the film 12, and unevenness hardly appears on the surface of the ozone TEOS film (5%) 15. Further, the ozone TEOS film (5%) 15 has a good film quality with extremely good coverage and low hygroscopicity, because the deposition shape at the corners of the steps of the polysilicon film 13 is a flow shape.

【0005】[0005]

【発明が解決しようとする課題】このように従来の半導
体装置では、下地絶縁膜に熱酸化膜を用いているため、
層間絶縁膜としてオゾン濃度の高いオゾンテオス膜(5
%)を直接形成するとそのパターン依存性によって表面
に荒れが生じるおそれがあり、これを防止するためにオ
ゾン濃度の低いオゾンテオス膜(1%)を被着し、その
上にオゾンテオス膜(5%)を形成している。このた
め、異なるオゾン濃度でのオゾンテオス膜を連続して形
成する工程が必要となり、工程作業が繁雑化するという
問題がある。また、配線にアルミニウム配線を用いた場
合には、オゾン濃度の高いオゾンテオス膜のパターン依
存性によってオゾンテオス膜の表面凹凸が顕著になり、
微細配線に適用したときには、そのカバレッジ性により
層間絶縁膜にボイドが発生するという問題もある。更
に、オゾン濃度の低いオゾンテオス膜を形成している
が、この種のオゾンテオス膜は一般に膜中水分量が多い
ため、吸湿性が高く、配線層間の絶縁性を確保するため
の膜質としては問題がある。
As described above, in the conventional semiconductor device, since the thermal oxide film is used as the base insulating film,
Ozone TEOS film with high ozone concentration (5
%) May cause surface roughness due to its pattern dependence. To prevent this, an ozone TEOS film with a low ozone concentration (1%) is applied, and an ozone TEOS film (5%) is deposited on it. Is formed. Therefore, a step of continuously forming an ozone TEOS film with different ozone concentrations is required, and there is a problem that the process work becomes complicated. When aluminum wiring is used for the wiring, the surface irregularity of the ozone TEOS film becomes remarkable due to the pattern dependence of the ozone TEOS film with high ozone concentration,
When applied to fine wiring, there is also a problem that voids are generated in the interlayer insulating film due to its coverage property. Furthermore, although an ozone TEOS film having a low ozone concentration is formed, since this kind of ozone TEOS film generally has a large amount of moisture in the film, it has a high hygroscopic property, and there is a problem as a film quality for securing insulation between wiring layers. is there.

【0006】このため、図5に示すように、オゾンテオ
ス膜(1%)14の更に下層にプラズマテオス膜16を
形成して層間絶縁膜を3層構造にし、オゾンテオス膜
(1%)の膜中水分量による層間絶縁膜としての膜質の
低下を防止する試みも成されているが、これでは層間絶
縁膜が更に多層化され、その製造が一層繁雑化するとい
う問題が生じる。特に、図5ではオゾンテオス膜(5
%)の表面の平坦化を図るために、有機シリカ等を用い
たエッチングバック法による平坦化を行っており、その
上にプラズマテオス膜17を形成した構成となっている
ため、層間絶縁膜が更に多層化されることになり、製造
工程が更に繁雑化される。本発明の目的は、オゾンテオ
ス膜の形成工程を簡略化するとともに、層間絶縁膜とし
ての膜質を改善した層間絶縁膜を有する半導体装置とそ
の製造方法を提供することにある。
Therefore, as shown in FIG. 5, a plasma theos film 16 is formed further under the ozone theos film (1%) 14 to form an interlayer insulating film having a three-layer structure. Attempts have also been made to prevent the deterioration of the film quality of the interlayer insulating film due to the amount of water, but this causes a problem that the interlayer insulating film is further multi-layered and the production thereof is further complicated. In particular, in FIG. 5, the ozone TEOS film (5
%), The surface is flattened by an etching back method using organic silica or the like, and the plasma theos film 17 is formed on the flattened surface. The number of layers is further increased, and the manufacturing process is further complicated. An object of the present invention is to provide a semiconductor device having an interlayer insulating film having an improved film quality as an interlayer insulating film and a manufacturing method thereof, while simplifying the formation process of the ozone TEOS film.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は、
配線の下地絶縁膜をシラン系プラズマCVD法によるプ
ラズマ酸化膜で、この配線を覆う層間絶縁膜をオゾン濃
度の高い有機シラン・オゾン系常圧CVD法によるオゾ
ンテオス膜でそれぞれ形成する。この場合、下地絶縁膜
をBPSG膜とプラズマ酸化膜との2層構造として構成
する。或いは、層間絶縁膜をオゾンテオス膜と、有機シ
ラン系プラズマCVD法からなるプラズマテオス膜との
2層構造として構成する。また、本発明の半導体装置の
製造方法は、シリコン基板上に下地絶縁膜としてシラン
系プラズマCVD法によるプラズマ酸化膜を形成する工
程と、この下地絶縁膜上に所要パターンのアルミニウム
配線を形成する工程と、このアルミニウム配線を含む全
面に層間絶縁膜としてオゾン濃度の高い有機シラン・オ
ゾン系常圧CVD法によるオゾンテオス膜を形成する工
程とを含んでいる。この場合、シリコン基板上に第1下
地絶縁膜としてBPSG膜を形成する工程を備え、更に
オゾンテオス膜を形成した後に、その上に有機シリカ膜
を塗布し、かつこの有機シリカ膜と酸化シリコン膜とを
エッチングバックして表面を平坦化する工程と、平坦化
されたオゾンテオス膜の上にプラズマテオス膜を形成す
る工程とを含んでもよい。
The semiconductor device of the present invention comprises:
The underlying insulating film of the wiring is formed of a plasma oxide film by the silane plasma CVD method, and the interlayer insulating film covering the wiring is formed of an organic silane / ozone-based atmospheric pressure CVD method having a high ozone concentration. In this case, the base insulating film has a two-layer structure including a BPSG film and a plasma oxide film. Alternatively, the interlayer insulating film has a two-layer structure including an ozone TEOS film and a plasma TEOS film formed by an organic silane plasma CVD method. Further, the method of manufacturing a semiconductor device of the present invention comprises a step of forming a plasma oxide film by a silane plasma CVD method as a base insulating film on a silicon substrate, and a step of forming aluminum wiring of a required pattern on the base insulating film. And a step of forming an ozone TEOS film having a high ozone concentration by an organic silane / ozone-based atmospheric pressure CVD method as an interlayer insulating film on the entire surface including the aluminum wiring. In this case, a step of forming a BPSG film as a first base insulating film on the silicon substrate is provided, and after forming an ozone TEOS film, an organic silica film is applied thereon, and the organic silica film and the silicon oxide film are formed. The method may include a step of etching back to flatten the surface and a step of forming a plasma theos film on the flattened ozone theos film.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の断面図である。シリコン
基板1上に第1下地絶縁膜として0.5μm程度のBP
SG膜2を有し、かつその上に第2下地絶縁膜として
0.2μm程度のプラズマ酸化シリコン膜3を有する。
そして、この第2下地絶縁膜3の上に1μm程度の厚さ
のアルミニウム膜で形成された所要パターンの配線4を
有する。そして、層間絶縁膜として、厚さ0.8μmの
オゾンテオス膜5を被着しており、更にその平坦化され
た上面に0.5μmの厚さのプラズマテオス膜7を有し
ている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention. A BP having a thickness of about 0.5 μm is formed as a first base insulating film on the silicon substrate 1.
The SG film 2 is provided, and the plasma silicon oxide film 3 having a thickness of about 0.2 μm is provided thereon as a second base insulating film.
Then, on the second base insulating film 3, the wiring 4 having a required pattern formed of an aluminum film having a thickness of about 1 μm is provided. Then, an ozone TEOS film 5 having a thickness of 0.8 μm is deposited as an interlayer insulating film, and a plasma TEOS film 7 having a thickness of 0.5 μm is further provided on the flattened upper surface thereof.

【0009】図2は図1の構造を製造工程順に示す断面
図である。先ず、図2(a)に示すように、シリコン基
板上1の上に常圧気相成長法により、BPSGを0.5
μmの厚さに堆積した後、900℃の窒素ガス雰囲気中
で30分間の熱処理を行い、第1下地絶縁膜(BPSG
膜)2を形成する。次に、第1下地絶縁膜2の上に平行
平板型枚葉式プラズマ化学気相成長装置を用いて、第2
下地絶縁膜としてシラン系プラズマ酸化シリコン膜3
(以下、プラズマ酸化膜という)を0.2μm形成す
る。そして、このプラズマ酸化膜3の上に銅及びシリコ
ンを含有するアルミニウム膜をスパッタリング法により
1μmの厚さで堆積して、パターニングし、配線4を形
成する。次に、配線4を含む表面に平行平板型枚葉式常
圧気相成長装置を用い、基板温度400℃,オゾン濃度
5%の条件で、厚さ0.8μmのオゾンテオス膜5を堆
積する。
FIG. 2 is a sectional view showing the structure of FIG. 1 in the order of manufacturing steps. First, as shown in FIG. 2A, BPSG of 0.5 is formed on the silicon substrate 1 by atmospheric pressure vapor deposition.
After depositing to a thickness of μm, heat treatment is performed in a nitrogen gas atmosphere at 900 ° C. for 30 minutes to form a first base insulating film (BPSG).
Film 2) is formed. Next, using a parallel plate type single wafer type plasma chemical vapor deposition apparatus on the first base insulating film 2,
Silane-based plasma silicon oxide film 3 as a base insulating film
(Hereinafter referred to as plasma oxide film) is formed to a thickness of 0.2 μm. Then, an aluminum film containing copper and silicon is deposited to a thickness of 1 μm on the plasma oxide film 3 by a sputtering method and patterned to form the wiring 4. Next, an ozone TEOS film 5 having a thickness of 0.8 μm is deposited on the surface including the wiring 4 using a parallel plate type single wafer type atmospheric pressure vapor deposition apparatus under the conditions of a substrate temperature of 400 ° C. and an ozone concentration of 5%.

【0010】次に、図2(b)に示すように、スピン塗
布法により、有機シリカ膜6を約1μmの厚さで形成す
る。次いで、図2(c)に示すように、平行平板型バッ
チ式反応性イオンエッチング装置を用い、CF4ガス流
量100SCCM,O2ガス流量15SCCM,圧力
0.1torr,周波数13.56MHZ,並びに高周
波電力0.3W/cm2 の条件で、有機シリカ膜6の全
部及び前記オゾンテオス膜5の表面の一部をエッチング
バックして、オゾンテオス膜5の表面を平坦化する。こ
こで、オゾンテオス膜5のエッチングレートを有機シリ
カ膜6のエッチングレートとほぼ同じにするか、又はや
や大きくする。最後に、平坦化されたオゾンテオス膜5
の上に平行平板型枚葉式プラズマ化学気相成長装置を用
いて、プラズマテオス膜7を0.5μmの厚さで堆積す
ることで、図1の構造が完成される。
Next, as shown in FIG. 2B, an organic silica film 6 is formed with a thickness of about 1 μm by a spin coating method. Then, as shown in FIG. 2C, a parallel plate type batch type reactive ion etching apparatus was used, and the CF4 gas flow rate was 100 SCCM, the O2 gas flow rate was 15 SCCM, the pressure was 0.1 torr, the frequency was 13.56 MHZ, and the high frequency power was 0. Under the condition of 3 W / cm 2 , the entire surface of the organic silica film 6 and a part of the surface of the ozone TEOS film 5 are etched back to flatten the surface of the ozone TEOS film 5. Here, the etching rate of the ozone TEOS film 5 is made substantially the same as or slightly higher than the etching rate of the organic silica film 6. Finally, the flattened ozone TEOS film 5
The structure shown in FIG. 1 is completed by depositing the plasma TEOS film 7 with a thickness of 0.5 μm on the substrate using a parallel plate type single wafer type plasma chemical vapor deposition apparatus.

【0011】このように、第2下地絶縁膜としてプラズ
マ酸化膜を用いることにより、図3に示すようにアルミ
ニウム上とプラズマ酸化膜上でのオゾンテオス膜の成長
速度が、シリコン基板上での成長速度と同程度であるの
で、アルミニウムによるオゾンテオス膜のパターン依存
性を解消してその表面の凹凸が顕著になることが回避さ
れる。したがって、配線間寸法が微細な構造でもオゾン
テオス膜のカバレッジ性を改善し、配線間にボイド等が
発生することが防止される。例えば、配線間が0.25
μmの次世代デバイスへの適用が可能となる。また、こ
の実施例では、その表面を有機シリカ膜を利用してエッ
チングバックしているので平坦性を更に進めることがで
きる。更に、この場合オゾン濃度の高いオゾンテオス膜
(5%)のみで層間絶縁膜が形成されるため、膜中水分
量の多いオゾンテオス膜(1%)を第1層間絶縁膜とし
て形成することが不要となり、オゾンテオス膜の製造工
程の簡略化を図るとともに、層間絶縁膜の膜質を改善す
ることが可能となる。
As described above, by using the plasma oxide film as the second base insulating film, the growth rate of the ozone TEOS film on the aluminum and the plasma oxide film is increased as shown in FIG. 3 on the silicon substrate. Since it is about the same as the above, it is possible to eliminate the pattern dependence of the ozone TEOS film due to aluminum and prevent the surface irregularities from becoming conspicuous. Therefore, the coverage of the ozone TEOS film is improved even with a structure in which the dimension between wirings is fine, and voids and the like are prevented from occurring between the wirings. For example, 0.25 between wiring
It is possible to apply μm to next-generation devices. Further, in this embodiment, since the surface is etched back by using the organic silica film, the flatness can be further promoted. Further, in this case, since the interlayer insulating film is formed only by the ozone TEOS film having a high ozone concentration (5%), it is not necessary to form the ozone TEOS film (1%) having a large amount of water content in the film as the first interlayer insulating film. Thus, it becomes possible to simplify the manufacturing process of the ozone TEOS film and improve the film quality of the interlayer insulating film.

【0012】ここで、下地絶縁膜として前記実施例では
BPSG膜とプラズマ酸化膜の2層構造としているが、
配線の直下の下地絶縁膜がプラズマ酸化膜で形成されて
いれば、その下側の絶縁膜は他の絶縁膜で形成してもよ
い。また、前記実施例では層間絶縁膜として5%のオゾ
ンテオス膜を採用しているが、オゾン濃度は多少増減し
てもよい。また、このオゾンテオス膜(5%)の上にプ
ラズマテオス膜を形成することは任意である。
Here, the underlying insulating film has a two-layer structure of a BPSG film and a plasma oxide film in the above embodiment,
If the underlying insulating film directly below the wiring is formed of a plasma oxide film, the insulating film below it may be formed of another insulating film. Further, in the above embodiment, the 5% ozone TEOS film is used as the interlayer insulating film, but the ozone concentration may be increased or decreased to some extent. Further, it is optional to form the plasma TEOS film on this ozone TEOS film (5%).

【0013】[0013]

【発明の効果】以上説明したように本発明は、下地絶縁
膜をシラン系プラズマ酸化膜で形成し、かつ層間絶縁膜
を高オゾン濃度のオゾンテオス膜のみで形成しているた
め、低オゾン濃度のオゾンテオス膜と高オゾン濃度のオ
ゾンテオス膜を形成することなく、オゾンテオス膜の表
面荒れを抑止し、かつ成長速度のパターン依存性を抑止
することができるので、より高信頼性の層間絶縁膜を形
成することができる。また、高オゾン濃度のみを用いて
いるので吸湿性が減少し、膜質も向上する。また、本発
明方法によれば、低オゾン濃度のオゾンテオス膜を形成
する工程が不要となるので、オゾンテオス膜の製造工程
の簡略化を実現できる効果がある。
As described above, according to the present invention, the base insulating film is formed of the silane-based plasma oxide film, and the interlayer insulating film is formed of only the ozone TEOS film having a high ozone concentration. Since the surface roughness of the ozone TEOS film and the pattern dependence of the growth rate can be suppressed without forming the ozone TEOS film and the ozone TEOS film of high ozone concentration, a more reliable interlayer insulating film is formed. be able to. Further, since only high ozone concentration is used, hygroscopicity is reduced and film quality is improved. Further, according to the method of the present invention, the step of forming the ozone TEOS film having a low ozone concentration is not necessary, so that there is an effect that the manufacturing process of the ozone TEOS film can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の一実施例の断面図であ
る。
FIG. 1 is a sectional view of an embodiment of a semiconductor device of the present invention.

【図2】図1の半導体装置の製造方法を工程順に示す断
面図である。
FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. 1 in process order.

【図3】オゾンテオス膜の成膜時間とその膜厚の関係を
示す特性図である。
FIG. 3 is a characteristic diagram showing the relationship between the film formation time of an ozone TEOS film and its film thickness.

【図4】従来の半導体装置の製造方法を工程順に示す断
面図である。
FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

【図5】従来の他の半導体装置の断面図である。FIG. 5 is a cross-sectional view of another conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 BPSG膜(第1下地絶縁膜) 3 プラズマ酸化膜(第2下地絶縁膜) 4 アルミニウム配線 5 オゾンテオス膜(5%) 6 有機シリカ膜 7 プラズマテオス膜 1 Silicon Substrate 2 BPSG Film (First Underlayer Insulating Film) 3 Plasma Oxide Film (Second Underlayer Insulating Film) 4 Aluminum Wiring 5 Ozone Theos Film (5%) 6 Organic Silica Film 7 Plasma Theos Film

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年9月22日[Submission date] September 22, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0001[Correction target item name] 0001

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0001】[0001]

【産業上の利用分野】本発明は下地絶縁膜上に形成され
た配線上に層間絶縁膜が形成されている半導体装置に関
し、特にその下地絶縁膜と層間絶縁膜の構造およびその
製造方法に関する。
The present invention relates to relates to a semiconductor device in which interlayer insulating film on the wiring formed over the base insulating film is formed, in particular to a structure and a manufacturing method thereof of the base insulating film and the interlayer insulating film.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0002[Name of item to be corrected] 0002

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0002】[0002]

【従来の技術】従来の高集積化を図った半導体装置で
は、下地絶縁膜上に配線が形成され、この配線上に層間
絶縁膜が形成されて更に上層の配線が形成される多層配
線構造が採用されている。この層間絶縁膜としては、ケ
イ酸エチル(Si(OC2 5 4 :以下、TEOSと
称する)とオゾンを原料とする常圧化学気相成長(CV
D)法を用いて形成した酸化シリコン膜(以下、オゾン
テオス膜と称する)が用いられている。このオゾンテオ
ス膜は、下地絶縁膜がポリシリコン(多結晶シリコン)
膜の場合は表面の平坦性に優れているが、下地絶縁膜が
熱酸化膜の場合は表面に凹凸が生じる場合がある。ま
た、このオゾンテオス膜は形成時のオゾン濃度が高い
程、下地の配線を構成するアルミニウムの影響を受けて
表面の凹凸の差は大きくなる傾向にある。このため、オ
ゾンテオス膜の凹凸表面上に形成した配線にストレスが
かかり、断線等が生じ易くなって信頼性が劣化すること
がある。
2. Description of the Related Art In a conventional semiconductor device having high integration, a wiring is formed on a base insulating film, and an interlayer insulating film is formed on the wiring to form an upper wiring. Has been adopted. As this interlayer insulating film, there is used atmospheric pressure chemical vapor deposition (CV) using ethyl silicate (Si (OC 2 H 5 ) 4 : hereinafter referred to as TEOS) and ozone.
A silicon oxide film (hereinafter referred to as an ozone TEOS film) formed by using the method D) is used. In this ozone TEOS film, the underlying insulating film is polysilicon (polycrystalline silicon).
The film is excellent in flatness of the surface, but when the underlying insulating film is a thermal oxide film, unevenness may occur on the surface. Further, the higher the ozone concentration at the time of forming the ozone TEOS film, the larger the difference in the unevenness of the surface tends to be due to the influence of aluminum forming the underlying wiring. Therefore, stress is applied to the wiring formed on the uneven surface of the ozone TEOS film, and disconnection or the like is likely to occur, which may deteriorate reliability.

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0010[Correction target item name] 0010

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0010】次に、図2(b)に示すように、スピン塗
布法により、有機シリカ膜6を約1μmの厚さで形成す
る。次いで、図2(c)に示すように、平行平板型バッ
チ式反応性イオンエッチング装置を用い、CF4 ガス流
量100SCCM,2 ガス流量15SCCM,圧力
0.1torr,周波数13.56MHZ,並びに高周
波電力0.3W/cm2 の条件で、有機シリカ膜6の全
部及び前記オゾンテオス膜5の表面の一部をエッチング
バックして、オゾンテオス膜5の表面を平坦化する。こ
こで、オゾンテオス膜5のエッチングレートを有機シリ
カ膜6のエッチングレートとほぼ同じにするか、又はや
や大きくする。最後に、平坦化されたオゾンテオス膜5
の上に平行平板型枚葉式プラズマ化学気相成長装置を用
いて、プラズマテオス膜7を0.5μmの厚さで堆積す
ることで、図1の構造が完成される。
Next, as shown in FIG. 2B, an organic silica film 6 is formed with a thickness of about 1 μm by a spin coating method. Then, as shown in FIG. 2 (c), a parallel plate type batch type reactive ion etching apparatus is used, CF 4 gas flow rate 100 SCCM, O 2 gas flow rate 15 SCCM, pressure 0.1 torr, frequency 13.56 MHZ, and high frequency power. Under the condition of 0.3 W / cm 2 , the entire surface of the organic silica film 6 and a part of the surface of the ozone TEOS film 5 are etched back to flatten the surface of the ozone TEOS film 5. Here, the etching rate of the ozone TEOS film 5 is made substantially the same as or slightly higher than the etching rate of the organic silica film 6. Finally, the flattened ozone TEOS film 5
The structure shown in FIG. 1 is completed by depositing the plasma TEOS film 7 with a thickness of 0.5 μm on the substrate using a parallel plate type single wafer type plasma chemical vapor deposition apparatus.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/90 K ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 21/90 K

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板上に下地絶縁膜を有し、この下地絶
縁膜上に配線を有し、この配線を覆うように層間絶縁膜
が形成されている半導体装置において、前記下地絶縁膜
がシラン系プラズマCVD法によるプラズマ酸化シリコ
ン膜であり、前記層間絶縁膜がオゾン濃度の高い有機シ
ラン・オゾン系常圧CVD法による酸化シリコン膜であ
ることを特徴とする半導体装置。
1. A semiconductor device having a base insulating film on a substrate, wiring on the base insulating film, and an interlayer insulating film formed to cover the wiring, wherein the base insulating film is silane. 1. A semiconductor device, which is a plasma silicon oxide film formed by a system plasma CVD method, wherein the interlayer insulating film is a silicon oxide film formed by an organic silane / ozone system atmospheric pressure CVD method having a high ozone concentration.
【請求項2】 下地絶縁膜がBPSG膜とシラン系プラ
ズマCVD法によるプラズマ酸化シリコン膜との2層構
造である請求項1の半導体装置。
2. The semiconductor device according to claim 1, wherein the base insulating film has a two-layer structure of a BPSG film and a plasma silicon oxide film formed by a silane plasma CVD method.
【請求項3】 層間絶縁膜が有機シラン・オゾン系常圧
CVD法による酸化シリコン膜と、有機シラン系プラズ
マCVD法からなる酸化シリコン膜との2層構造である
請求項1または2の半導体装置。
3. The semiconductor device according to claim 1, wherein the interlayer insulating film has a two-layer structure of a silicon oxide film formed by an organic silane / ozone-based atmospheric pressure CVD method and a silicon oxide film formed by an organic silane-based plasma CVD method. .
【請求項4】 シリコン基板上に下地絶縁膜としてシラ
ン系プラズマCVD法によるプラズマシリコン膜を形成
する工程と、この下地絶縁膜上に所要パターンのアルミ
ニウム配線を形成する工程と、このアルミニウム配線を
含む全面に層間絶縁膜としてオゾン濃度の高い有機シラ
ン・オゾン系常圧CVD法による酸化シリコン膜を形成
する工程とを含むことを特徴とする半導体装置の製造方
法。
4. A step of forming a plasma silicon film by a silane plasma CVD method as a base insulating film on a silicon substrate, a step of forming an aluminum wiring of a required pattern on the base insulating film, and including the aluminum wiring. And a step of forming a silicon oxide film as an interlayer insulating film on the entire surface by an organic silane / ozone-based atmospheric pressure CVD method having a high ozone concentration.
【請求項5】 シリコン基板上に第1下地絶縁膜として
BPSG膜を形成する工程と、その上に第2下地絶縁膜
としてシラン系プラズマCVD法によるプラズマシリコ
ン膜を形成する工程と、この下地絶縁膜上に所要パター
ンのアルミニウム配線を形成する工程と、このアルミニ
ウム配線を含む全面に層間絶縁膜としてオゾン濃度の高
い有機シラン・オゾン系常圧CVD法による酸化シリコ
ン膜を形成する工程と、その上に有機シリカ膜を塗布
し、かつこの有機シリカ膜と前記酸化シリコン膜とをエ
ッチングバックして表面を平坦化する工程と、平坦化さ
れた前記酸化シリコン膜の上に有機シラン系プラズマC
VD法からなる酸化シリコン膜を形成する工程とを含む
半導体装置の製造方法。
5. A step of forming a BPSG film as a first base insulating film on a silicon substrate, a step of forming a plasma silicon film by a silane plasma CVD method as a second base insulating film thereon, and the base insulating film. A step of forming an aluminum wiring having a desired pattern on the film, a step of forming a silicon oxide film by an organic silane / ozone-based atmospheric pressure CVD method having a high ozone concentration as an interlayer insulating film on the entire surface including the aluminum wiring, and A step of applying an organic silica film on the surface of the silicon oxide film, and etching back the organic silica film and the silicon oxide film to planarize the surface; and an organosilane-based plasma C on the planarized silicon oxide film.
And a step of forming a silicon oxide film by the VD method.
JP32333693A 1993-11-30 1993-11-30 Semiconductor device and its manufacture Pending JPH07153840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32333693A JPH07153840A (en) 1993-11-30 1993-11-30 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32333693A JPH07153840A (en) 1993-11-30 1993-11-30 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH07153840A true JPH07153840A (en) 1995-06-16

Family

ID=18153669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32333693A Pending JPH07153840A (en) 1993-11-30 1993-11-30 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH07153840A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012736A (en) * 1996-06-17 1998-01-16 Taiwan Moshii Denshi Kofun Yugenkoshi Planarizatioh for manufacturing integrated circuit
US8008730B2 (en) 2008-08-26 2011-08-30 Renesas Electronics Corporation Semiconductor device, and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159157A (en) * 1989-11-16 1991-07-09 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH05291415A (en) * 1992-04-07 1993-11-05 Nec Corp Production of semiconductor device
JPH05308103A (en) * 1992-04-28 1993-11-19 Nec Corp Manufacture of semiconductor device
JPH06104249A (en) * 1992-09-22 1994-04-15 Kawasaki Steel Corp Semiconductor device
JPH06267939A (en) * 1992-03-13 1994-09-22 Kawasaki Steel Corp Manufacture of semiconductor device
JPH06283523A (en) * 1993-03-26 1994-10-07 Kawasaki Steel Corp Manufacture of semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03159157A (en) * 1989-11-16 1991-07-09 Sanyo Electric Co Ltd Semiconductor device and manufacture thereof
JPH06267939A (en) * 1992-03-13 1994-09-22 Kawasaki Steel Corp Manufacture of semiconductor device
JPH05291415A (en) * 1992-04-07 1993-11-05 Nec Corp Production of semiconductor device
JPH05308103A (en) * 1992-04-28 1993-11-19 Nec Corp Manufacture of semiconductor device
JPH06104249A (en) * 1992-09-22 1994-04-15 Kawasaki Steel Corp Semiconductor device
JPH06283523A (en) * 1993-03-26 1994-10-07 Kawasaki Steel Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012736A (en) * 1996-06-17 1998-01-16 Taiwan Moshii Denshi Kofun Yugenkoshi Planarizatioh for manufacturing integrated circuit
US8008730B2 (en) 2008-08-26 2011-08-30 Renesas Electronics Corporation Semiconductor device, and manufacturing method thereof

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