SU368647A1 - MEMORY DEVICE - Google Patents

Description

one

A memory device (memory) is known, which contains an address storage device, the address selection block of which is connected via the “And to associative —to a storage device” circuit. The first input of the accumulator is connected with the output of the decimator connected to the first output of the lock-and: controller, the second output of which is connected to the local control unit connected with the bit unit of the address accumulator.

However, the number of faulty cells in which the device is operational is limited by the storage capacity.

The proposed storage device differs from the known one in that it contains encoding and decoding units and a power register of the correction code, the counting input of which is connected to the second output of the Counter-indicator. The first control output is connected to one of the inputs of the coding block, the other input is connected with the second input of the associative drive, and the output is connected with the discharge block of the address accumulator. The second control output of the register is connected to one of the inputs of the decoding unit, the other input of which is connected to the bit unit and the output to the local control unit.

This allows the device to operate when the number of failures exceeds the capacity of the associative accumulator.

The drawing shows a block diagram of the memory. The memory contains the address accumulator AH /, the block for selecting the address 2 of which is connected via an AND 3 circuit to an associative accumulator 4, the first input 5 of which is connected to the output of the decoder 6. The decoder 6 is connected to the first output 7 of the counter-indicator 8, the second output 9 of which (Attached to the local control unit BMU 10, associated

with bit unit 11 AH /. In addition, the device contains an input register 12 with information inputs 13 and control inputs M connected with the BMU 10. The output 15 of the register 12 controls the polling input 16 of the accumulator 4 and the input 17 of the circuit "And 3, to the input 18 of which the bus 19 is connected negative response of the accumulator 4. The memory also contains the coding unit 20, the decoding unit 21, the power register of the correction code

PMCC 22, the counting input 23 of which is connected to the second output 9 of the counter-indicator 8, the first control output 24 is connected to one of the inputs of the coding unit 20, the other INPUT 25 of which is connected to the second

input: 1 26 accumulator 4, and output 27 - with a discharge unit // AN 1. The second control output 28 of the MSCC 22 is connected to input 29 of the decoding unit 21, input 30 of which is connected to the discharge unit 11, and output 31

with BMU 10, one input 32 register word 32

connected to the BMU 10, another input 34 is connected to the “ILR1 35” circuit, the output 37 of the storage device 4 is connected to the nerve input 36, and the output 39 of the decoding unit 21 is connected to the second input 38. The associative storage 4 has recording entries 40, the BMU - input operations 41.

The device works as follows.

One of the methods (for example, using monitoring programs, writing and reading direct and reverse codes, followed by comparison, etc.) determines the addresses of the failing cells. These addresses are entered at the input of the record 40 into the indicative parts of the cells of the storage device 4, the information parts of which are used to replace the non-addressable cells of the address storage device /. The SCC 22 is set to the minimum power input 42.

In this case, there are two modes of operation.

In the first mode, the PMCC 22 adjusts to a code that detects one error. The addresses of the failed cells are sequentially recorded in the free cells of the accumulator 4, the numbers of which are determined by the state of the counter-indicator 8.

When recording the next address of the failed cell in the drive 4, "1." Thus, the indicator-indicator 8 not only determines the number of the next free cell of the accumulator 4, but also records the number of occupied cells. After the 4 addresses of all the failing AH1 cells are written to the drive 4 and in the absence of an overflow signal at the output 9 of the counter-indicator 8, the device is ready for operation.

The inputs 13 of register 12 receive the address of the cell to which it is necessary to turn, and the inputs 41 of the local control unit the signals of the operation code and the beginning of the operation. BMU 10 generates the necessary sequence of control signals, under the influence of which the address of register 12 is fed to the polling inputs 16 of accumulator 4. From accumulator 4, an answer is retrieved whether this address is stored in it. If not, then bus 19 receives a signal permitting access to AH 1 at the requested address. If this address is stored in the accumulator 4, then the information part of the cell of this accumulator 4 is accessed, in the attribute part of which the requested address is stored.

Suppose that in one of the cells AH 1, whose address is not recorded in drive 4, a failure occurred. The decoding unit 21 generates a signal "error that goes to the BMU 10. This signal restores the distorted information (for example, by reading it from an external memory) and writes it to drive 4. At the same time, the address is written to the indicative part of the corresponding cell 4. failed cell. Subsequently, a call to this address leads to reading information from the accumulator 4. This is how the system works until the accumulator 4 overflows. In this case, an overflow signal is generated, which is fed via bus 9 to the input of the BMU 10 and to the counting input 23 of the PMCC 22. By this signal, the power of the correction code is increased (the content of the PMCC 22 is added to "1, as a result of which the encoding and decoding

the devices are adjusted to the corresponding code), the information encoded in this code is overwritten in AN 1, the addresses of the faulty cells in which there is more than one failure (indicated above

ways), and these addresses are recorded at the input of record 40 in the characteristic parts of cells of accumulator 4, the information parts of which are used to replace faulty cells AH /. In the absence of an overflow signal at output 9, the device operates in a new cycle, as described. When overwriting the information, the addresses of the faulty cells whose errors are corrected by the correction code used in this cycle are not recorded in the accumulator 4. Thus, the accumulator 4 is partially released and the addresses of the faulty cells can be written to it as they are detected by the correction code.

To increase the likelihood of detecting an error, it is possible to periodically check AH 1 with the HELP of the previously mentioned methods for detecting addresses of malfunctioning cells that are not detected by a correction code.

The beginning of each new cycle is the accumulator overflow signal 4. At this, the memory repeats the previously indicated actions.

The second mode differs from the first one in that at the beginning of the system operation the minimum power correction code must detect two errors and correct one, and during further operation the code power in the corresponding cycle is always 1 more than the first. The signal "error corrected information from the output of the decoding unit 21 simultaneously with its issuance through the register of the word 32 to other devices, is recorded in the free cell of the accumulator 4, in the characteristic part of which

the address of the corresponding cell of the AN is entered. Subsequently, the address at this address is made to the cell of the accumulator 4. Thus, the restoration and recording of information from the external memory is not required

if in this cell there will be another failure during the current cycle.

Subject invention

A storage device containing an address accumulator, the address selection block of which is connected via the AND circuit to the associative accumulator, the first input of which is connected to the output of the decoder connected to the first output of the indicator-stepper, the second output of which is connected to the local control unit A single block of the address accumulator, characterized in that, in order to ensure the operation of the device with the number of failures exceeding the capacity of the associative accumulator, it contains encoding and decoding blocks and p .korrektiruyuschego code power, the count input of which is connected to the second

the output of the indicator counter, the first control output Connected to one of the inputs of the coding block, the other input of which is connected to the second input of the associative drive, and the output to the bit block of the address storage drive, the second 11 directing output connected to one of the inputs of the decoding block, the other input is connected to the bit unit and the output is to the local control unit.

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