JPH10116856A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH10116856A JPH10116856A JP26698696A JP26698696A JPH10116856A JP H10116856 A JPH10116856 A JP H10116856A JP 26698696 A JP26698696 A JP 26698696A JP 26698696 A JP26698696 A JP 26698696A JP H10116856 A JPH10116856 A JP H10116856A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor integrated
- circuit device
- board
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体集積回路装置
に関する。The present invention relates to a semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】従来の半導体集積回路装置を特開平8−9
7319号公報の図１（ａ）（ｂ）及び図２を用いて説明す
る。前記公報の図１（ａ）（ｂ）は、この半導体集積回
路装置をセラミックス製ＢＧＡ（Ball Grid Array ）パ
ッケージに適用した実施例の要部構成を模式的に示した
図である。図１（ａ）はその下面図、（ｂ）は断面図で
ある。セラミックス製ＢＧＡパッケージ１を構成するセ
ラミックス多層配線基板２は、その裏面がはんだバンプ
形成面３とされており、外部との電気的信号の入出力端
子としてはんだバンプ４が形成されている。そのバンプ
形成面３におけるはんだバンプ４の形成領域Ａの外周部
は、空白領域Ｂとされており、その空白領域Ｂの各角部
に補強用ピン５がそれぞれ設けられている。この補強用
ピン５は、前記公報の図２に示すように、セラミックス
多層配線基板２の上面側にＬＳＩチップ６が搭載され、
プリント基板８に搭載された場合に、プリント基板８に
設けられたピン挿入孔内に挿入され、セラミックス製Ｂ
ＧＡパッケージ１をプリント基板８に機械的に固定す
る。これにより、セラミックス製ＢＧＡパッケージ１と
プリント基板８との熱膨張差による熱応力は補強用ピン
５により直接はんだバンプ４には加わらず、温度サイク
ルが負荷されても、はんだバンプ４の熱的疲労強度やセ
ラミックス製ＢＧＡパッケージ１自体の熱応力破壊等を
防止できる。2. Description of the Related Art A conventional semiconductor integrated circuit device is disclosed in
This will be described with reference to FIGS. 1 (a) and 1 (b) of FIG. 7 and FIG. FIGS. 1 (a) and 1 (b) of the above publication are diagrams schematically showing a main part configuration of an embodiment in which this semiconductor integrated circuit device is applied to a ceramic BGA (Ball Grid Array) package. FIG. 1A is a bottom view and FIG. 1B is a sectional view. The ceramic multilayer wiring board 2 constituting the ceramic BGA package 1 has a solder bump formation surface 3 on the back surface, and has solder bumps 4 formed as input / output terminals for electric signals with the outside. An outer peripheral portion of the formation region A of the solder bump 4 on the bump formation surface 3 is a blank region B, and a reinforcing pin 5 is provided at each corner of the blank region B. The reinforcing pin 5 has an LSI chip 6 mounted on the upper surface of the ceramic multilayer wiring board 2 as shown in FIG.
When mounted on the printed circuit board 8, it is inserted into a pin insertion hole provided in the printed circuit board 8, and the ceramic B
The GA package 1 is mechanically fixed to the printed circuit board 8. As a result, the thermal stress due to the difference in thermal expansion between the ceramic BGA package 1 and the printed circuit board 8 is not directly applied to the solder bumps 4 by the reinforcing pins 5, and the thermal fatigue of the solder bumps 4 even when a temperature cycle is applied. The strength and thermal stress destruction of the ceramic BGA package 1 itself can be prevented.
【０００３】また、もう一つの従来の半導体集積回路装
置を特開平7−73110号公報の図４を用いて説明する。前
記公報の図４は、ＬＳＩチップ１４とキャリア基板１６
（セラミックスなどでできた多層配線基板）を電気的に
接合してあるはんだボール４のまわりの部分にＬＳＩチ
ップ１４の熱膨張係数とほぼ同等の熱膨張係数を有する
封止樹脂１５を充填して構成されたＬＳＩパッケージを
模式的に示した断面図である。このＬＳＩパッケージは
はんだバンプ１７にてプリント基板８へ接続され、はん
だバンプ１７の劣化や、ゴミの侵入等を防ぐため、封止
はんだ６がはんだバンプ１７の周辺部分に設けられてい
る。これにより、ＬＳＩチップ１４とキャリア基板１６
の熱膨張差による変形を緩和し、はんだボール４の接続
信頼性が向上したうえ、半導体集積回路装置自体の熱応
力破壊等を防止できる。Another conventional semiconductor integrated circuit device will be described with reference to FIG. 4 of JP-A-7-73110. FIG. 4 of the publication discloses an LSI chip 14 and a carrier substrate 16.
A sealing resin 15 having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the LSI chip 14 is filled in a portion around the solder ball 4 to which the (multilayer wiring substrate made of ceramics or the like) is electrically connected. FIG. 2 is a cross-sectional view schematically illustrating a configured LSI package. The LSI package is connected to the printed circuit board 8 by solder bumps 17, and a sealing solder 6 is provided around the solder bumps 17 in order to prevent the deterioration of the solder bumps 17 and the invasion of dust. Thereby, the LSI chip 14 and the carrier substrate 16
In addition, the deformation due to the difference in thermal expansion of the semiconductor integrated circuit device is reduced, the connection reliability of the solder ball 4 is improved, and the thermal stress destruction of the semiconductor integrated circuit device itself can be prevented.
【０００４】[0004]
【発明が解決しようとする課題】しかし、ＢＧＡパッケ
ージのようなはんだボールを用いた接続実装構造がパー
ソナルコンピュータや携帯機器等の電子部品の接続実装
構造として採用されている以上、例えば上述したような
大型かつ複雑なセラミックス製ＢＧＡパッケージでは、
安価な高密度実装を追求する携帯機器等には不向きであ
る。つまり、製造方法が複雑になることによる価格の上
昇、また、構造が大きいことによるダウンサイジングへ
の障害等が大きな問題となっていた。また、例えばＬＳ
Ｉパッケージにおいて、ＬＳＩチップとキャリア基板を
接続するはんだボールのまわりの部分に、ＬＳＩチップ
の熱膨張係数と同等の熱膨張係数を有する樹脂を充填さ
せても、プリント基板へ実装後、機器の筐体へ搭載する
際に生じるプリント基板の曲げやねじれによるＬＳＩパ
ッケージやはんだボールといった半導体集積回路装置を
構成する各部品への変形影響は防ぐことができないとい
う問題があった。However, since a connection mounting structure using solder balls such as a BGA package has been adopted as a connection mounting structure for electronic components such as a personal computer and a portable device, for example, as described above. For large and complex ceramic BGA packages,
It is unsuitable for portable equipment pursuing inexpensive high-density mounting. In other words, there have been significant problems such as an increase in price due to a complicated manufacturing method and an obstacle to downsizing due to a large structure. Also, for example, LS
In the I-package, even if the area around the solder balls connecting the LSI chip and the carrier substrate is filled with a resin having a thermal expansion coefficient equivalent to the thermal expansion coefficient of the LSI chip, after mounting on the printed circuit board, the housing There has been a problem that it is not possible to prevent the deformation effect on each component constituting the semiconductor integrated circuit device such as an LSI package and a solder ball due to the bending or torsion of the printed circuit board generated when mounting on a body.
【０００５】本発明の目的では、ＬＳＩパッケージをプ
リント基板へ接続したような半導体集積回路装置の実装
構造に関し、製造コストを抑えた高密度かつ簡略な構造
を有し、また、はんだの接続部信頼性を損なうことのな
いＬＳＩパッケージの実装構造を有する半導体集積回路
装置を提供することにある。An object of the present invention is to provide a mounting structure of a semiconductor integrated circuit device in which an LSI package is connected to a printed circuit board. It is an object of the present invention to provide a semiconductor integrated circuit device having an LSI package mounting structure without impairing the performance.
【０００６】[0006]
【課題を解決するための手段】半導体集積回路装置に使
用されるはんだの接続信頼性の問題は、例えばセラミッ
クス多層基板とプリント基板の熱膨張差から生じる熱応
力のように、半導体集積回路装置に使用される各部品の
熱膨張差によって引き起こされたり、また、機器の筐体
に搭載する際に生じるプリント基板の曲げやねじれによ
っても引き起こされる。つまり、このプリント基板の変
形を抑えられる構造であれば、はんだの接続信頼性を確
保することができる。しかし、補強用ピンでＬＳＩパッ
ケージを固定するような従来技術の半導体集積回路装置
では構造が大きくしかも複雑である。そこで、はんだバ
ンプの接続信頼性を確保するために、はんだバンプのま
わりの部分に樹脂を注入し、はんだバンプを封止するこ
とにより、はんだバンプに生じる変形を緩和することで
この問題は顕著に解決され、さらに製造方法の複雑さ
や、コストの問題に対しても大幅な改善となる。A problem in connection reliability of solder used in a semiconductor integrated circuit device is that a semiconductor integrated circuit device has a problem such as a thermal stress caused by a difference in thermal expansion between a ceramic multilayer substrate and a printed circuit board. It is caused by a difference in thermal expansion of each component used, and also caused by bending or twisting of a printed circuit board generated when the printed circuit board is mounted on a housing of an apparatus. That is, if the structure can suppress the deformation of the printed circuit board, the connection reliability of the solder can be ensured. However, a conventional semiconductor integrated circuit device in which an LSI package is fixed by a reinforcing pin has a large and complicated structure. Therefore, in order to secure the connection reliability of the solder bumps, resin is injected into the area around the solder bumps, and the solder bumps are sealed. This is a significant improvement over the complexity of the manufacturing method and cost issues.
【０００７】[0007]
【発明の実施の形態】本発明の一実施例について、図面
を参照して説明する。図１は本発明をセラミックス製Ｂ
ＧＡパッケージの実装構造に適用した実施例の要部構成
を模式的に示した断面図である。図２はこの半導体集積
回路装置の詳細形状を示した斜視図である。図１でＬＳ
Ｉチップ６は、その裏面に形成されたはんだボール形成
面８に取り付けられたＬＳＩチップ６の電気的信号を入
出力するための端子であるはんだボール９によってセラ
ミックス多層配線基板２に接続搭載されている。また、
これらのセラミックス製ＢＧＡパッケージ１も同様に、
その裏面に形成されたはんだバンプ形成面３に取り付け
られた電気的信号の入出力端子であるはんだバンプ４に
よってプリント基板７に接続搭載されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the present invention using ceramic B
It is sectional drawing which showed typically the principal part structure of the Example applied to the mounting structure of GA package. FIG. 2 is a perspective view showing a detailed shape of the semiconductor integrated circuit device. LS in FIG.
The I chip 6 is connected and mounted on the ceramic multilayer wiring board 2 by solder balls 9 which are terminals for inputting and outputting electric signals of the LSI chip 6 attached to the solder ball forming surface 8 formed on the back surface. I have. Also,
Similarly, these ceramic BGA packages 1
It is connected and mounted on a printed circuit board 7 by solder bumps 4 serving as input / output terminals for electric signals attached to a solder bump forming surface 3 formed on the back surface.
【０００８】はんだバンプ４によりセラミックス製ＢＧ
Ａパッケージ１とプリント基板７が接続された後、はん
だバンプ４の形成されてあるセラミックス多層配線基板
２とプリント基板７との間隙部分に封止樹脂１０を充填
する。また、この実施例では、ＬＳＩチップ６とセラミ
ックス多層配線基板２との接続部分にも封止樹脂５が用
いられている。これにより、例えば熱膨張差によって引
き起こされる熱応力や、機器の筐体に実装される際に生
じるプリント基板の曲げやねじれによる変形は緩和さ
れ、はんだバンプの接続信頼性を大幅に向上させる一
方、製造コストを抑えた簡略で高密度な実装が可能とな
る。Ceramic BG by solder bump 4
After the A package 1 and the printed board 7 are connected, a sealing resin 10 is filled in a gap between the ceramic multilayer wiring board 2 on which the solder bumps 4 are formed and the printed board 7. In this embodiment, the sealing resin 5 is also used at the connection between the LSI chip 6 and the ceramic multilayer wiring board 2. Thereby, for example, the thermal stress caused by the difference in thermal expansion and the deformation due to the bending and torsion of the printed circuit board that occurs when the printed circuit board is mounted on the housing of the device are alleviated, and while the connection reliability of the solder bump is greatly improved, Simple, high-density mounting with reduced manufacturing costs is possible.
【０００９】次に、前記実施例のセラミックス製ＢＧＡ
パッケージ１の製造過程を図３(ａ)（ｂ）（ｃ）（ｄ）
に示す。ＬＳＩチップ６をセラミックス多層配線基板２
にはんだボール９で接続搭載後、封止樹脂５ではんだボ
ール９のまわりの部分を封止する（ａ）。次に、はんだ
バンプ４をセラミックス多層配線基板２のはんだ形成面
３に形成し（ｂ）、プリント基板７に接続実装する
（ｃ）。その後、封止樹脂１０を、はんだバンプ４の形
成されてあるセラミックス多層配線基板２とプリント基
板７との間隙部分に充填する（ｄ）。この時、充填する
封止樹脂１０は、ＬＳＩチップ６とセラミックス多層配
線基板２の間にある封止樹脂５のガラス転移点よりも低
い温度でベークできる樹脂とする。これにより、樹脂は
一般的にガラス転移点を越える温度では急激に膨張する
傾向があるが、この場合、封止樹脂１０のベーク時に封
止樹脂５が急激に膨張し、ＬＳＩチップ６とセラミック
ス多層配線基板２の間にあるはんだボール９が破断する
のを防ぐことができる。それにより、半導体集積回路装
置を形成するその他の部品に与える損傷影響も防ぐこと
が可能となる。Next, the ceramic BGA of the above embodiment is described.
3 (a), 3 (b), 3 (c), 3 (d)
Shown in LSI chip 6 is replaced with ceramic multilayer wiring board 2
After connection and mounting with a solder ball 9, a portion around the solder ball 9 is sealed with a sealing resin 5 (a). Next, the solder bumps 4 are formed on the solder forming surface 3 of the ceramic multilayer wiring board 2 (b), and are connected and mounted on the printed board 7 (c). Thereafter, the sealing resin 10 is filled into the gap between the printed circuit board 7 and the ceramic multilayer wiring board 2 on which the solder bumps 4 are formed (d). At this time, the sealing resin 10 to be filled is a resin that can be baked at a temperature lower than the glass transition point of the sealing resin 5 between the LSI chip 6 and the ceramic multilayer wiring board 2. As a result, the resin generally tends to expand rapidly at a temperature exceeding the glass transition point. In this case, the sealing resin 5 expands rapidly when the sealing resin 10 is baked, and the LSI chip 6 and the ceramic multilayer are expanded. Breakage of the solder balls 9 between the wiring boards 2 can be prevented. This makes it possible to prevent damage to other components forming the semiconductor integrated circuit device.
【００１０】図４（ａ）（ｂ）に本発明の実施例である
実施例のセラミックス製ＢＧＡパッケージ１を示す。プ
リント基板７の板厚はセラミックス多層配線基板２より
も薄く、曲げ剛性（曲げ剛性ＥＩ＝ｂｈ3Ｅ／１２ で与
えられる。ここで、Ｅは基板材料の縦弾性係数、Ｉは断
面二次モーメント、ｂは板幅、ｈは板厚）がセラミック
ス多層配線基板２よりも低くなるようにしてある。この
ため、例えばこの半導体集積回路装置が機器の筐体に搭
載される際に生じるプリント基板７の曲げやねじれによ
る変形は、セラミックス多層配線基板２とプリント基板
７との間にある封止樹脂１０により抑えられ、セラミッ
クス多層配線基板２はプリント基板７の変形影響を受け
ず、セラミックス製ＢＧＡパッケージ１に損傷を与える
ことがなくなる。FIGS. 4A and 4B show a ceramic BGA package 1 according to an embodiment of the present invention. The board thickness of the printed circuit board 7 is smaller than that of the ceramic multilayer wiring board 2 and is given by bending stiffness (bending stiffness EI = bh 3 E / 12. Here, E is the longitudinal elastic modulus of the board material, and I is the second moment of area. , B is a board width, and h is a board thickness). Therefore, for example, the deformation caused by bending or twisting of the printed circuit board 7 when the semiconductor integrated circuit device is mounted on the housing of the device is caused by the sealing resin 10 between the ceramic multilayer wiring board 2 and the printed circuit board 7. The ceramic multilayer wiring board 2 is not affected by the deformation of the printed circuit board 7 and the ceramic BGA package 1 is not damaged.
【００１１】[0011]
【発明の効果】本発明によれば、ＢＧＡパッケージに代
表される、ＬＳＩパッケージを構成する各部品と、プリ
ント基板の熱膨張差によって引き起こされる熱応力の影
響によるプリント基板の曲げを抑えることができるう
え、ＬＳＩパッケージをプリント基板に実装した後、パ
ーソナルコンピュータ等の機器の筐体に搭載する際に生
じるプリント基板の曲げやねじれによるはんだバンプへ
の変形影響も緩和され、ＬＳＩパッケージとプリント基
板を接続するはんだバンプの接続部信頼性を大幅に向上
することができる。また、大型コンピュータ等に使用さ
れてきた、高価で複雑な半導体集積回路装置の実装構造
や製造方法も、本発明によって性能を損なうことなく大
きく改善できる。According to the present invention, it is possible to suppress the bending of the printed circuit board due to the effect of thermal stress caused by the difference in thermal expansion between the components constituting the LSI package, represented by the BGA package, and the printed circuit board. In addition, after mounting the LSI package on a printed circuit board, the deformation effect on the solder bumps due to the bending and twisting of the printed circuit board when mounting it on the housing of a device such as a personal computer is reduced, and the LSI package is connected to the printed circuit board. The connection reliability of the solder bumps to be used can be greatly improved. Further, the mounting structure and manufacturing method of an expensive and complicated semiconductor integrated circuit device used for a large computer or the like can be greatly improved without impairing the performance by the present invention.
【図１】本発明の実施例であるセラミックス製ＢＧＡパ
ッケージをプリント基板へ実装した場合の断面図。FIG. 1 is a cross-sectional view when a ceramic BGA package according to an embodiment of the present invention is mounted on a printed circuit board.
【図２】本発明の実施例であるセラミックス製ＢＧＡパ
ッケージをプリント基板へ実装した場合の斜視図。FIG. 2 is a perspective view when a ceramic BGA package according to an embodiment of the present invention is mounted on a printed circuit board.
【図３】本発明の実施例であるセラミックス製ＢＧＡパ
ッケージの製造過程を示す断面図。FIG. 3 is a sectional view showing a manufacturing process of the ceramic BGA package according to the embodiment of the present invention.
【図４】本発明の実施例であるセラミックス製ＢＧＡパ
ッケージがプリント基板の曲げに影響を受けない断面
図。FIG. 4 is a cross-sectional view of a ceramic BGA package according to an embodiment of the present invention, which is not affected by bending of a printed circuit board.
２…セラミックス多層配線基板、３…はんだバンプ形成
面、４…はんだバンプ、５…封止樹脂、６…ＬＳＩチッ
プ、７…プリント基板、８…はんだボール形成面、９…
はんだボール、１０…封止樹脂。2 ... ceramic multilayer wiring board, 3 ... solder bump forming surface, 4 ... solder bump, 5 ... sealing resin, 6 ... LSI chip, 7 ... printed board, 8 ... solder ball forming surface, 9 ...
Solder balls, 10 ... sealing resin.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐藤 俊彦 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshihiko Sato 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.
Claims (3)
Ｉパッケージが、複数のはんだバンプでプリント基板に
接続されて成る半導体集積回路装置において、前記ＬＳ
Ｉパッケージと前記プリント基板の間に樹脂を入れたこ
とを特徴とする半導体集積回路装置。An LS formed by connecting an LSI to a multilayer wiring board
A semiconductor integrated circuit device comprising an I package connected to a printed circuit board by a plurality of solder bumps;
A semiconductor integrated circuit device wherein a resin is inserted between an I package and the printed board.
と前記プリント基板の間に入れた前記樹脂のベーク温度
が、前記ＬＳＩと前記多層配線基板の間に入れた樹脂の
ガラス転移点より低い半導体集積回路装置。2. The semiconductor integrated circuit according to claim 1, wherein a baking temperature of the resin placed between the LSI package and the printed board is lower than a glass transition point of the resin placed between the LSI and the multilayer wiring board. Circuit device.
げ剛性がプリント基板の曲げ剛性より高い半導体集積回
路装置。3. The semiconductor integrated circuit device according to claim 1, wherein the bending rigidity of the multilayer wiring board is higher than the bending rigidity of the printed board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26698696A JPH10116856A (en) | 1996-10-08 | 1996-10-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26698696A JPH10116856A (en) | 1996-10-08 | 1996-10-08 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10116856A true JPH10116856A (en) | 1998-05-06 |
Family
ID=17438479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26698696A Pending JPH10116856A (en) | 1996-10-08 | 1996-10-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10116856A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6514792B2 (en) * | 1998-06-24 | 2003-02-04 | Nortel Networks Limited | Mechanically-stabilized area-array device package |
| US6559390B1 (en) | 1998-12-22 | 2003-05-06 | Nec Corporation | Solder connect assembly and method of connecting a semiconductor package and a printed wiring board |
-
1996
- 1996-10-08 JP JP26698696A patent/JPH10116856A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6514792B2 (en) * | 1998-06-24 | 2003-02-04 | Nortel Networks Limited | Mechanically-stabilized area-array device package |
| US6559390B1 (en) | 1998-12-22 | 2003-05-06 | Nec Corporation | Solder connect assembly and method of connecting a semiconductor package and a printed wiring board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6756663B2 (en) | Semiconductor device including wiring board with three dimensional wiring pattern | |
| JPH09162322A (en) | Surface-mount semiconductor device and manufacture thereof | |
| JP2002305286A (en) | Semiconductor module and electronic component | |
| US6317333B1 (en) | Package construction of semiconductor device | |
| JPH0685161A (en) | High density package type semiconductor device | |
| US20050062151A1 (en) | Semiconductor integrated circuit and electronic apparatus having the same | |
| JP2885414B2 (en) | Semiconductor device, mounting method thereof, and electronic device | |
| JP2002217514A (en) | Multichip semiconductor device | |
| JPH07115151A (en) | Semiconductor device and manufacture thereof | |
| JP2000216550A (en) | Laminate printed wiring board | |
| JP3656861B2 (en) | Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device | |
| JPH10116856A (en) | Semiconductor integrated circuit device | |
| JP2000243862A (en) | Interposer board | |
| JP3150560B2 (en) | Semiconductor device | |
| US20020135050A1 (en) | Semiconductor device | |
| JP4556671B2 (en) | Semiconductor package and flexible circuit board | |
| JP2002231761A (en) | Electronic component and mounting body thereof | |
| JP4128722B2 (en) | Circuit board and electronic equipment | |
| JPH0419806Y2 (en) | ||
| JP3372169B2 (en) | Semiconductor package | |
| KR100402835B1 (en) | Structure of chip scale package and method for fabricating it | |
| JPH11177015A (en) | Semiconductor package and intermediate substrate for mounting the same | |
| JP3087721B2 (en) | Memory module | |
| JPH1074885A (en) | High-density integrated circuit package | |
| JP2725621B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20040308 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040524 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040601 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040802 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20040831 |