JPH0399518A - Logic circuit - Google Patents

Abstract

PURPOSE:To form a logic circuit of high speed and low power consumption by providing a bias circuit whose bias voltage is not considerably changed for the change of a supply voltage and impressing the bias output to the gate of a first FET. CONSTITUTION:The gate voltage of a P-channel MOSFET MP1 for load connected between a power source VDD and an output terminal is given from the bias output terminal of a bias circuit 1. This circuit 1 consists of an enhancement P-channel MOSFET MP2 and a resistance R1 connected in series between the power source VDD and the earth. The output of this bias circuit has an approximate earth potential in the lower limit of the operating supply voltage by a sharp characteristic in the vicinity of the threshold voltage. Meanwhile, when the supply voltage is high, the current value of the P-channel MOSFET MP1 is not increased more than necessary because a bias output potential A of the bias circuit 1 rises; and thus, the current is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit using complementary MIS (metal-insulating-film-semiconductor) FETs, and particularly to a logic circuit configured with a ratio circuit.

[Prior Art] Conventionally, a general N
A circuit shown in FIG. 5 is known as an OR circuit. This circuit consists of P-channel MO8FETs MP, MP, connected in series between the power supply vno and the output end. ,...
, MP, and N-channel MO8FET MN111MNI2 . connected in parallel between the output terminal and ground. ...
9MN1. , and input signals 5IIS21 . is what is output.

However, in this circuit, the output terminal is n P-channel MO
8FETMP, □+MP 121..., MP,
. Since it is connected to the power supply VOO via the power supply VOO, there is a problem that it takes time for the signal to rise.

As a solution to this drawback, an 0MO8-NOR circuit using a ratio circuit as shown in FIG. 6 is known. In this circuit, n P-channel MO3FETs MP II, MP,
. , ..., MP, , a P-channel MO8FET MP as a load whose gate is grounded is connected to the power supply VD.
N-channel MO8FET MN, , MN, connected between D and the output end and connected in parallel. , . . . , MN, are made to function as drivers for driving the P-channel MO8FET MP.

According to this circuit, since only one FET is connected between the power supply VDD and the output end, the rise time of the output is short, and the circuit can be made faster. This effect becomes more pronounced as the number of inputs increases.

Further, according to this circuit, since the gate width of the P-channel MO8FET can be made small, it is possible to reduce the drain junction capacitance of the P-channel MO3FET, and the gate capacitance does not become a load on the previous stage.
Not only the rise time but also the fall time can be shortened.

Similarly, FIG. 7 shows a conventional ratioless NAND circuit, and FIG. 8 shows a NAND circuit using a ratio circuit.

In FIG. 7, n P-channel MOS FETMPs 31. are connected between the power supply VDD and the output terminal. MP3
2゜..., MP3. , are connected in parallel, and n N-channel MO8FETMN2. is connected between the output terminal and the ground. ,
MN2゜,...1MN2. , are connected in series.

On the other hand, in the circuit shown in FIG.
Instead of N2rl, an N-channel MOS F E as a load whose gate is biased to the supply voltage VD+)
T M N 2 is connected.

In this NAND circuit as well, the latter ratio circuit can speed up the circuit operation due to the absence of series-connected FETs.

[Problems to be Solved by the Invention] However, although logic circuits using the conventional ratio circuits described above can achieve higher speeds than normal ratioless circuits, Low current is an important issue in this type of circuit because of the disadvantage of current flow. Especially the load F
Since the power supply voltage is directly applied between the gate and source of the ET, if the operating power supply voltage range is wide, the target operating speed must be guaranteed at the lower limit of the operating power supply voltage. If the voltage is high, there is a problem in that an unnecessarily large current flows through the circuit.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a logic circuit that can prevent an unnecessarily large current from flowing even when the power supply voltage becomes high, and can achieve high speed and low power consumption at the same time.

[Means for Solving the Problems] A logic circuit according to the present invention includes a load including a first FET of a first conductivity type connected between a first power source and an output terminal;
a driver consisting of a plurality of second FETs of a second conductivity type connected in parallel between the output end and a second power supply and inputting an input signal to each gate; a bias circuit that applies a bias voltage, and the bias circuit has a bias output terminal and the second bias circuit.
a resistor connected between the bias output terminal and the first power source, and a third FET of the first conductivity type connected between the bias output terminal and the first power source and having a gate input with a feedback signal from the resistor. The threshold value of the third FET and the resistance value of the resistor are such that the voltage at the bias output terminal is the threshold value of the first FET when the lower limit value of the operating power supply voltage range is given as the power supply voltage. It is characterized by being set to a value that is equivalent to the value voltage.

[Function] According to the present invention, the gate bias voltage of the 10th FET as a load connected between the first power supply and the output terminal is
Provided by the bias circuit. When the power supply voltage applied to the third FET that constitutes the bias circuit changes and the voltage between its gate and source changes, the third FET changes its drain current accordingly. For this reason, the third FE
Feedback is applied to the gate of T by a resistor, and the third FE
T acts so that the bias output terminal maintains a constant bias voltage.

On the other hand, the threshold value of the third FET constituting the bias circuit and the resistance value of the same resistor are such that when the lower limit value of the operating power supply voltage range is given as the power supply voltage, the voltage at the bias output terminal is set to the first value. The voltage is set to a value equivalent to the threshold voltage of the FET.

Therefore, sufficiently high-speed operation is possible even when the power supply voltage is low, and even when the power supply voltage increases, there is little variation in the gate bias voltage of the first FET, which prevents the DC current from increasing more than necessary. It can be prevented.

[Embodiment 1] Logic circuits according to embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 1 shows the CMOS ratio N according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of an OR circuit. In FIG. 1, the same parts as those in FIG. 6 are given the same reference numerals, and the explanation of the overlapping parts will be omitted.

The circuit of this embodiment is different from the conventional circuit shown in FIG.
The gate voltage of TMP is applied from the bias output terminal of the bias circuit 1.

The bias circuit 1 has a power supply V. l: Enhancement type P-channel MO8F connected in series between l and ground
It consists of ETMP2 and resistor R+. MOS
The gate and drain of FETMP2 are connected, and this connection point serves as the bias output terminal of MO
Connected to the gate of 8FET MPI.

MO8FET MP2 is set so that its threshold value is approximately equal to the lower limit of the operating power supply voltage range, and resistor R1 has a resistance value ( ”Vos
/Ios: 1/2000~ of Vos is the drain-source voltage, IDs is the drain-source current)
It is set to 115.

By setting in this way, the output of this bias circuit becomes almost the ground potential at the lower limit of the operating power supply voltage due to the steep ID1ilVDS characteristic near the threshold voltage, which is similar to the conventional example shown in FIG. It is possible to obtain the rise characteristics of On the other hand, when the power supply voltage is large, the bias output potential A of the bias circuit 1 increases, so that the current value of the P-channel MO8FET MP does not become larger than necessary, and the current value can be reduced.

Next, the above actions and effects can be obtained when the operating power supply voltage range is 1.8 to 3.
．． The case of 6v will be specifically explained.

The operating power supply voltage range of 1.8-3.6v is currently used primarily in 3V-based systems.

In this case, since the lower limit of the operating power supply voltage is 1.8V,
The threshold voltage of MO3FET MP2 is set to -1.8V. P channel MO8 with threshold voltage of this level
FET is the current 1-2μm rule silicon game)C
In the MO8 integrated circuit process, this can be obtained by not performing the general ion implantation into the gate region for threshold adjustment.

The P-channel MOS FETM thus obtained
Fig. 2 shows the measured values of the current characteristics of P2. In this figure, the horizontal axis shows the gate-source voltage of MO8FET MP2 expressed by Vt (=absolute value of the threshold voltage of MO8FET MP2), and the vertical axis shows the drain of the same P-channel MO3FET as MO8FET MP2 connected to the gate. Current value between source and drain (relative current value)
This shows the current characteristics. Note that the relative current value here refers to the source-drain current of the P-channel MO8FET normalized by the source-drain current when the gate-source voltage is the threshold voltage. be. However, this vertical axis is expressed on a logarithmic scale. As is well known, the source-to-drain current shows an exponential change with respect to the gate-source voltage in the region where the gate-source voltage is lower than Vt, and changes to the second power as the gate-source voltage increases. It begins to show characteristics.

Figure 3 shows the MO3FE of Figure 1 based on the characteristics of Figure 2.
The horizontal axis represents the characteristics of the voltage VBB of the bias output A of the bias circuit 1 consisting of TMP2 and resistor R1 (VDD)
Taking (VDD VBB) on the vertical axis, MO3FETMP
The relative resistance value of R1 with respect to R2 is expressed as a parameter. Here, the relative resistance value of the resistor R1 with respect to MO8FE TMP2 is the resistance value when the gate and drain of MO8FET MP2 are biased to their threshold values Vt/I Ds (I as : source-drain current) It is.

Further, VDD-VBB represents the gate-to-source voltage itself of the load MO8FETMP that constitutes the n-input NOR.

As is clear from this Figure 3, the relative resistance value! /18
1, at the lowest operating voltage of 1.8V, Voo-V
an= 1, 799 V k: Pickpocket, MO8FE
A gate-to-source voltage similar to that of the conventional example shown in FIG. 5 in which the gate of TMP1 is grounded is obtained, and MO8FETM
The ability of P is similar to that of the conventional circuit, and a fast rise speed can be obtained.

On the other hand, VDD = 3 V Teha, VDD VBB”9
2. At 28V, V, D = 3.6V, Voo '/
'BB'92.40V, and even when the power supply voltage is high, the gate bias applied to MO8FETMP is suppressed, so the ability of MO8F'ETMP is suppressed from increasing more than necessary, and current consumption can be reduced. .

By the way, the threshold voltage of MO3FETMP is -0,
7V % Low level output voltage S of n-input NOR circuit
. When the current reduction effect of the circuit of this embodiment at the time of low level output is estimated with OV as OV, the following is obtained when the power supply voltage is 3V.

(2,28-0,7) 2/ (3,0-0,7)”
→0.472 Also, when the power supply voltage is 3.6V, it becomes as follows.

(2,4-0,7)2/ (3,6-0,7) 2″:
0344 As is clear from the above calculation results, the former is about 1/2.1 of the conventional value, and the latter is about 1/2 of the conventional value.
2.9, the current is reduced respectively.

As is clear from FIG. 3, this current reduction effect is achieved by reducing the relative resistance value of resistor R1 to 1/2000 when VDD=3V.
It is expected to a certain extent. In addition, if the relative resistance value of resistor R1 is increased, the current reduction effect will be further increased, but since VDD-VBB at 1.8V, which is the lower limit of the operating power supply voltage range, will be smaller, please note that the rise speed will decrease. There is a need to. By the way, VDD = 1, 8 V (when D, R
rcv relative resistance value is 1/19 and Voo VBB”?
1,73 V, Rt relative resistance W is 1/10 V.

, -VBB''==1.66V.

Therefore, the relative resistance value of the resistor R1 is 1/200
It is desirable that the resistance value is set to 0 to 1/10.

Next, in this example, M OS F E T M P
A case where the threshold value of 2 is shifted from -1.8V will be explained.

If the threshold value is further shifted in one direction, this corresponds to moving each curve in FIG. 3 in parallel to the upper right direction approximately parallel to the straight line of VBl'1=OV.

At this time, if the threshold value has an absolute value larger than the limit of the operating power supply voltage range, the current reduction effect will be completely lost, so this point must be kept in mind.

On the other hand, when the threshold value is shifted in the child direction, when the relative resistance value of R1 is 1/181, 0.5X (1,8V
-Vt) ~ (1,8V-Vt) only at 1.8V VDo
-vB13 value becomes small and the rising speed decreases, so this point needs to be taken into account.

FIG. 4 is a circuit diagram showing an n-input CMOS ratio NOR circuit according to a second embodiment of the present invention. Note that in FIG. 4, the same parts as in FIGS. 1 and 6 are designated by the same reference numerals, and explanations of overlapping parts will be omitted.

The circuit of this embodiment differs from the circuit of the first embodiment shown in FIG. 1 in the configuration of the bias circuit.

The bias circuit 2 in this embodiment includes an enhancement type P-channel MO8FET MP3 connected between the power supply VDD and the bias output terminal, a resistor R2 connected between the bias output terminal and the ground, and the power supply VDD and the bias MO8FE is connected between the output terminal and its divided voltage output.
It is composed of a voltage dividing circuit consisting of resistors R3 and R4 applied to the gate of TMP3. That is, the second embodiment differs from the first embodiment in that the gate of the MO8FET MP is not directly connected to the bias output terminal, and the voltage from the power supply 4VDD to the bias voltage is divided and applied. Note that the resistance value of the resistor R3 + the resistance value of the resistor R4 is set to be sufficiently high (set) relative to the resistance value of the resistor R2. This voltage division ratio is set so that VDD operates as in the embodiment shown in FIG. When it is the lower limit of the power supply voltage range, MOS FET M P
It is set to match the threshold of 3.

According to this embodiment, the large P-channel MO8
Even when no FET is used, the MO8FET MP4, whose absolute value is smaller than the lower limit of the power supply voltage range, can be biased near the threshold by dividing the output voltage using resistors R, , R4. However, resistance R3
, R4 decreases the feedback amount by the voltage division ratio, so the first
It should be noted that the current reduction effect is smaller than in the embodiment. Note that P channel MO8 with different thresholds
In the case of a FET as well, if the gate voltage is expressed by the threshold value Vt, the characteristics will almost match the characteristics shown in FIG.

In each of the above embodiments, an n-input NOR circuit with a P-channel MO8FET as a load has been described, but it goes without saying that the present invention is also applicable to an n-input NAND gate with an N-channel MO8FET as a load.

Furthermore, the present invention is applicable not only to CMO8 logic circuits but also to ratio logic circuits using other complementary MISFETs using nitride film gates.

[Effects of the Invention] As described above, according to the present invention, when the lower limit of the operating power supply voltage range is given as the power supply voltage, the bias equal to the threshold voltage of the first FET, which is the load, is A bias circuit is provided which outputs a voltage and whose bias voltage does not change much even with changes in the power supply voltage, and the output of this bias circuit is applied to the gate of the first FET. Therefore, sufficiently high-speed operation is possible even when the power supply voltage is low, and even when the power supply voltage increases, there is little variation in the gate bias voltage of the first FET, which prevents the DC current from increasing more than necessary. It is possible to provide a logic circuit with high speed and low power consumption.

[Brief explanation of drawings]

FIG. 1 shows the CMOS ratio N according to the first embodiment of the present invention.
A circuit diagram of the OR circuit, Fig. 2 is a graph showing the current characteristics of the P-channel MO8FET when the gate and drain are connected, and Fig. 3 is a graph showing the bias voltage characteristics with respect to the power supply voltage of the bias circuit in the same example. 4 is a circuit diagram of a CMOS ratio NOR circuit according to a second embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional CMOS ratioless NOR circuit, and FIG. 6 is a circuit diagram of a conventional CMOS ratio NOR circuit. The circuit diagram of the R circuit, Figure 7 is a conventional CMOS ratioless N
The circuit diagram of the AND circuit, Figure 8, is a conventional CMOS register N.
It is a circuit diagram of an AND circuit. 1.2; Bias circuit, MP, , MP2゜MP+, M
P,, ~MP, n, MP, 1~MP3. l; P channel MO8FET1MNtt ~MNIn, MN2゜M
N 2r~MN2□; N channel MO8F'ET, S
. ~Sn: Input signal, So: Output signal, R1+R2
+R31R4; resistance

Claims (1)

[Claims] (1) A load consisting of a first FET of a first conductivity type connected between a first power supply and an output terminal, and a load consisting of a first FET of a first conductivity type connected between the output terminal and a second power supply and each gate connected in parallel between the output terminal and a second power supply. a driver including a plurality of second FETs of a second conductivity type that inputs an input signal to the first FET; and a bias circuit that applies a gate bias voltage to the gate of the first FET, and the bias circuit has a bias circuit that applies a gate bias voltage to the gate of the first FET. a resistor connected between the output end and the second power source; and a first conductivity type transistor connected between the bias output end and the first power source and having a gate input with a feedback signal from the resistor. a third FET, and the threshold value of the third FET and the resistance value of the resistor are such that the voltage at the bias output terminal is set to the third FET when the lower limit of the operating power supply voltage range is given as the power supply voltage. 1. A logic circuit characterized in that the voltage is set to a value equivalent to the threshold voltage of FET No. 1.