JPH0389178A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To markedly enhance the trouble detection rate of the whole of a test pattern or a combination circuit by testing the combination circuit part connected to the data input terminal or enable signal input signal of a scanning flip-flop circuit individually or simultaneously. CONSTITUTION:A scanning flip-flop circuit 11 equipped with enable function is selectively set to the first test mode reading the data input from a combination circuit regardless of '1', '0' of enable signal input corresponding to the combination of the logical levels of the first and second test mode setting signal inputs, the second test mode reading the enable signal input from the combination circuit regardless of '1', '0' of data input and a usual mode making a system clock effective only in such a case that the enable signal input is '1' when the system clock is inputted to read data input.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit, and in particular to a scan with an enable function in a semiconductor integrated circuit that employs a scan design to facilitate testing. The present invention relates to a flip-flop circuit.

(Conventional technology) Due to the miniaturization of semiconductor integrated circuits, the degree of integration is increasing year by year.
Large scale integrated circuits (LSIs) having on the order of 100 gates within a chip are becoming readily available. However, when it comes to testing to determine whether a manufactured LSI is a good product or a defective product, it is becoming exponentially more difficult to create test patterns with sufficient failure coverage, and creating test patterns manually is difficult. It's almost impossible.

Therefore, automatic creation methods using computers have been proposed as an efficient method for creating test patterns, and LS
A scan design in which memory elements within I are scanned in a chain has been put into practical use.

In this scan design, when forming a circuit including a sequential circuit, a scan flip-flop circuit is used as each memory circuit inside the sequential circuit to separate it from other circuits, and these multiple scan flip-flop circuits are serially connected. connection to enable sequential data transfer,
The inputs and outputs of the internal circuit are virtually used as the outputs and inputs of the scan flip-flop circuit to form a combinational circuit.

As a result, the input test data is shifted to the scanning flip-flop circuit group and set to the input terminal of the combinational circuit to be tested, and the output data from the output terminal of the combinational circuit is read into the scanning flip-flop circuit group. This method not only improves the testability of the entire system, but also facilitates the creation of test patterns using a computer, which is expected to be very effective in terms of reducing the labor required to create test data. be.

FIG. 4 shows a part of a conventional LSI employing a scan design, in which 40 is a combinational circuit section, 41 . . . are scan flip-flop circuits.

Scanning flip-flop circuit 41 in FIG. 4...
have five input terminals (data input terminal, system clock CK input terminal, shift-in data Sl input terminal, shift clock A input terminal, shift clock B input terminal) and two output terminals (data output Q terminal, shift clock B input terminal), respectively. out data SO output terminal). This scan flip-flop circuit 41 is a normal D-type flip-flop circuit to which a scan function is added, and its operating signal waveform is shown in FIG.

According to the circuit shown in FIG. 4, the input value to the input terminal of the combinational circuit section 41 can be set by shifting the input test data using the shift-in data input SDI and the shift clock ASB. In addition, to read the output value from the output terminal of the combinational circuit section 41 (observation), input the system clock CK and take in the data at the output terminal to the data input terminal of the scan flip-flop circuit 41. After that, the shift-out data SDO is shifted by shift clocks A and B.
It can be extracted as

Figure 6 shows another conventional LS using scan design.
A part of I is shown, 60 is a combinational circuit section, 61...
・ is a scan flip-flop circuit. Each of the scan flip-flop circuits 61 in FIG. 6 has six input terminals (data input terminal, enable signal EN input terminal, system clock CK input terminal, shift-in data Sl input terminal, shift clock A input terminal). Shift clock B input terminal) and two output terminals (data output Q terminal, shift out data SO output terminal). This scan flip-flop circuit 61 is the same as the scan flip-flop circuit 41 in FIG. 4 with an enable function for controlling the validity/invalidity of the system clock CK input. When the enable signal EN input is “1”
Only in this case, the system clock CK becomes valid and data input is read, and the operating signal waveform thereof is shown in FIG.

According to the circuit of FIG. 6, the input value to the input terminal of the combinational circuit section 60 can be set by shifting the input test data using the shift-in data input SDI and the shift clock ASB. In addition, to read the output value from the output terminal of the combinational circuit section 60 (observation), input the system clock CK and take in the data at the output terminal to the data input terminal of the scanning flip-flop circuit 61. After that, the shift out data SDO is shifted by shift clock A%B.
It can be extracted as

By the way, normally in an LSI, all scan flip-flop circuits rarely read data inputs at the same time. Therefore, when the scanning flip-flop circuits 61 shown in FIG. 6 are used, in a certain state, the scanning flip-flop circuits 61...
・Part of the device operates while the other part enters the hold state, reducing power consumption. Therefore, the scanning flip-flop circuit 61 shown in FIG. 6 must be used.

However, when the scan flip-flop circuit 61 shown in FIG. 6 is used, there are problems as described below.

That is, among the scan flip-flop circuits 61..., the scan flip-flop circuit 61 to which 0' is input as the enable signal EN input cannot receive data input even if the system clock CK is input. , this data input p cannot be a virtual output. Therefore, only the data input of the scanning flip-flop circuit 61 to which the enable signal EN input is 1' is tested, which reduces the efficiency in increasing the failure detection rate of the test pattern. Testing the combinational circuit section 60 that generates EN becomes almost impossible.

Here, scan flip-flop circuit 6 in FIG.
A combinational circuit section 6 connected to the data input terminal of 1...
FIG. 8 shows the relationship between the combinational circuit unit 60 connected to the 0 and enable signal input EN terminals. To test the combinational circuit section 60 connected to the data input terminal of the scan flip-flop circuit 61, the enable signal EN input must be set to "12" and the system clock CK must be input. The combinational circuit section 60 always outputs “1” as the enable signal EN.
” and perform the test. At this time,
The problem is that it becomes impossible to perform a test in a state where the combinational circuit section 60 connected to the enable signal EN generates "0" as the enable signal EN, and the failure detection rate of the entire combination circuit section 60 is significantly reduced. There is. In addition, all scan flip-flop circuits 61... rarely read data input at the same time, and the enable signal EN inputs of all scan flip-flop circuits 61... are set to "1" at the same time. Since it is almost impossible to do so, the generated test pattern becomes a redundant and long pattern, which increases the test cost.

(Problems to be Solved by the Invention) As described above, a semiconductor integrated circuit using a conventional scan design is a scan flip-flop circuit group that receives data input only when "1" is input as an enable signal input. , there is a problem in that the failure detection rate of the test pattern and the failure detection rate of the entire combinational circuit section are significantly reduced.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a combinational circuit section connected to a data input terminal of a scan flip-flop circuit and a combinational circuit section connected to an enable signal input terminal. It is now possible to test both individually or simultaneously.
An object of the present invention is to provide a semiconductor integrated circuit that can significantly improve the failure detection rate of test patterns and the failure detection rate of the entire combinational circuit section.

[Structure of the Invention] (Means for Solving the Problems) The first invention is to shift input test data and set it at an input terminal of a combinational circuit to be tested, and output data from an output terminal of the combinational circuit. In a semiconductor integrated circuit that employs a scan design using a scan flip-flop circuit with an enable function that reads, shifts, and outputs a signal, the scan flip-flop circuit with an enable function has a first test mode setting signal input and a second test mode setting signal input. The first test mode reads data input from the combinational circuit regardless of whether the enable signal input is "1" or "0" depending on the combination of the logic levels of the signal inputs. A second test mode that reads the enable signal input from the combinational circuit regardless of ° and the system clock is enabled and reads the data input only if the enable signal input is '1' when the system clock is input. It is characterized in that it can be selectively set to a normal mode.

A second invention provides a scanning flip-flop with an enable function that shifts input test data and sets it at the input terminal of a combinational circuit to be tested, and reads and shifts output data from the output terminal of the combinational circuit and outputs the shifted data. In a semiconductor integrated circuit that employs a scan design using a flip-flop circuit, the scan flip-flop circuit with an enable function receives data input from the combinational circuit when the system clock is input, depending on the logic level of the test mode setting signal input. There is a test mode in which the exclusive OR logic between and enable signal input is taken and output, and when the system clock is input, the enable signal input is “
It is characterized in that it is selectively set to a normal mode in which the system clock is enabled and data input is read only when the clock is set to 1''.

(Function) In the semiconductor integrated circuit of the first invention, by setting the first test mode, it becomes possible to test the combinational circuit section connected to the data input and terminal of the scan flip-flop circuit. .

When set to the second test mode, it becomes possible to test the combinational circuit section connected to the enable signal input terminal of the scan flip-flop circuit. Setting it to normal mode allows normal operation.

In the semiconductor integrated circuit of the second invention, when the test mode is set, the combinational circuit section connected to the data input terminal of the scanning flip-flop circuit and the combinational circuit section connected to the enable signal input terminal Even if there is a failure in either of them, the output of the exclusive OR logic of the data input and the enable signal input will differ from the expected value, making it possible to test both of the combinational circuit sections.

Setting it to normal mode allows normal operation.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a scan with an enable function that shifts input test data and sets it to the input terminal of a combinational circuit section 1o to be tested, reads output data from the output terminal of the combinational circuit section 10, shifts it, and outputs it. This figure shows part of an LSI that employs a scan design using flip-flop circuits 11 .

Scanning flip-flop circuit 11 shown in FIG.
. . , the shift-out data output terminal SO of the flip-flop circuit 11 at the previous stage and the shift-in data SI input terminal of the flip-flop circuit 11 at the next stage are connected serially as a whole.

Here, SDI is a shift data input, SDO is a shift data output, -12 to 16 are a system clock signal line and a first shift clock signal line that are commonly connected to all scan flip-flop circuits 11... and a second shift clock signal line, a first test mode setting signal line, and a second test mode setting signal line.

FIG. 2 shows a specific example of one scanning flip-flop circuit 11 in FIG. 1, which has eight input terminals (data input terminal, enable signal EN input terminal, test mode setting signal T1 input terminal, second test mode setting signal T2 input terminal, system clock CK input terminal, shift-in data S1 input terminal, shift clock A input terminal, shift clock B input terminal),
It has a 3-input 1-output data multiplexer 20, a D-type flip-flop circuit FF, an OR gate 21, and two output terminals (data output Q terminal, shift-in data S1 input terminal).

That is, the data input terminal is connected to the data multiplexer 20.
The enable signal EN input terminal is connected to the second input terminal of the data multiplexer 20, and the first input terminal of the OR gate 21, and the enable signal EN input terminal is connected to the first input terminal of the OR gate 21 to output the first test mode setting signal. The T1 input terminal is connected to the second input terminal of the OR gate 21, and the output terminal of this OR gate 21 is connected to the first input terminal of the data multiplexer 20.
The second test mode setting signal T2 input terminal is connected to the second switching control terminal of the data multiplexer 20.

The output terminal of this data multiplexer 20 is connected to the data input terminal of the D-type flip-flop circuit FF,
The system clock CK input terminal is connected to the clock input CLK terminal of the D-type flip-flop circuit FF, and the shift clock A input terminal and shift clock B input terminal are the shift clock input input terminal and shift clock input terminal of the D-type flip-flop circuit FF, respectively. The data output Q of this D-type flip-flop circuit FF is connected to the B terminal.
is connected to the data output Q terminal and also to the third input terminal of the data multiplexer 20, and the shift-out data SO output of this D-type flip-flop circuit FF is connected to the shift-out data output SO terminal.

In the scanning flip-flop circuit 11, the data multiplexer 20 selects the input signal of the first input terminal when the input of the first switching control terminal and the input of the second switching control terminal C are each "1". When the input of the first switching control terminal is "1°" and the input of the second switching control terminal is "0", the input signal EN of the second input terminal is selected and output, and the input signal EN of the second switching control terminal is selected and output. When the input of the first switching control terminal is "0" and the input of the second switching control terminal is "1", when EN is '11, D is selected and EN is "0".
Select Q when .

Therefore, the scan flip-flop circuit has (
1) A first test mode in which the first test mode setting signal T1 input and the second test mode setting signal T2 input are each at the '1° level; (2) the first test mode setting signal T1 input is at the '1 degree level; ” level, the second test mode in which the second test mode setting signal T2 input is at the “0” level; (3) the first test mode setting signal T1 input is in the “0” level;
0” level, the second test mode setting signal T2 input is “
There is a normal mode at the 1" level, each of which operates as described below.

First, in the first test mode, the data multiplexer 20 selects and outputs the input signal regardless of whether the enable signal EN is '1' or '0', and when the system clock CK input becomes '1', the D-type flip-flop The circuit FF reads the selection output signal D% of the data multiplexer 20 and outputs it to the data output Q terminal.

In the second test mode, the data multiplexer 20 selects and outputs the enable signal EN input regardless of whether the data input is "1" or "0", and when the system clock CK input becomes "1", the D-type flip-flop The output circuit FF reads the selection output signal EN of the data multiplexer 20 and outputs it to the data output Q terminal.

In the normal mode, if the enable signal EN is 11°, the output of the OR gate 21 becomes "1', the data multiplexer 2o selects and outputs the input signal, and the system clock CK input becomes "1". Then, the D-type flip-flop circuit FF reads the selection output signal of the data multiplexer 20 and outputs it to the data output Q terminal.On the other hand, if the enable signal EN is "0", the output of the OR gate 21 is "0". 0", the data multiplexer 20 selects and outputs the data output Q of the D-type flip-flop circuit FF, and the system clock CK input becomes "1".
”, the D-type flip-flop circuit FF holds the data output Q.

Next, the operation of the circuit shown in FIG. 1 will be explained.

(1) When testing the combinational circuit section 10 connected to the data input terminals of the scan flip-flop circuits 11, etc., the first test mode is set. The input value to the combinational circuit unit 10 is set by shifting the input test data using the shift-in data input SDI and shift clocks A and B. That is, the first shift clock signal A is applied to the first shift clock signal line 13, and the second shift clock signal B is applied to the second shift clock signal line 14, and in synchronization with this, the shift-in data input SDI is shifted by the scan flip-flop circuits 11 .

Furthermore, when reading the output value from the output terminal of the combinational circuit unit 10 (observation), the data at the output terminal is read by the scanning flip-flop circuit 11 using the system clock CK.
・After inputting the data to the data input terminal, shift clock A
, B, and is taken out as shift-out data SDO. That is, the system clock signal CLK is applied to the system clock signal line 12, and in synchronization with this, the signal at the output terminal of the combinational circuit section 10 is taken into the scanning flip-flop circuit 11. Thereafter, the data of the scan flip-flop circuits 11... is shifted and the shift-out data SDO output is taken out.

Tests can be executed by repeating such a sequence for the required number of test data.

(2) When testing the combinational circuit section 10 connected to the enable signal EN input terminal of the scan flip-flop circuit 11, etc., the second test mode is set. The setting of input values to the combinational circuit section 10 is as follows:
Setting is performed by shifting input test data using shift-in data input SDI and shift clock ASB.

Furthermore, when reading the output value from the output terminal of the combinational circuit unit 10 (observation), the data at the output terminal is read by the scanning flip-flop circuit 11 using the system clock CK.
After taking in data to the data input EN terminal of ., it is shifted by shift clocks A and B and taken out as shift-out data SDO.

(3) During normal operation, set to normal mode. In this case, the scanning flip-flop circuit 11...
is the system clock C only if the enable signal EN input is “1” when the system clock CK is input.
K becomes valid and reads the data input.

In the above embodiment, a D-type flip-flop circuit was used as the flip-flop circuit FF, but even if other flip-flop circuits (for example, set or reset type flip-flop circuits) are used, they will have the above-mentioned modes. If the configuration is such that the same effect as in the above embodiment can be obtained through the same operation.

FIG. 3 shows another specific example of one of the scan flip-flop circuits 11 in FIG. 1, and compared to the scan flip-flop circuit 11 shown in FIG. The points (1) to (3) are different, and the others are the same, so the same reference numerals as in FIG. 2 are used, and the explanation thereof will be omitted. That is, (1) one test mode setting signal T input terminal is provided in place of the first test mode setting signal T1 input terminal and the second test mode setting signal T2 input terminal. (2) A 2-input, 1-output data multiplexer 30 is provided in place of the 3-input, 1-output data multiplexer 20. (3) Data input is exclusive OR gate 3
1, an enable signal EN input and a test mode setting signal T input are input to an AND gate 32, the output of this AND gate 32 is input to an exclusive OR gate 31, and the output of this exclusive OR gate 31 is input to a data multiplexer 30. The data output Q of the D-type flip-flop circuit FF is input to the first input terminal of the data multiplexer 3.
0, the enable signal EN input and the test mode setting signal T input are input to the OR gate 33, and the output of this OR gate 33 is input to the switching control terminal of the data multiplexer 30. The selected output is a D-type flip-flop circuit F.
It is connected to the data input terminal of F.

In the scan flip-flop circuit 11# of FIG. 3, when the input of the switching control terminal is "1", the data multiplexer 30 selects and outputs the input signal of the first input terminal, and outputs the input signal of the switching control terminal. When is “0”,
The input signal of the second input terminal is selected and output.

Therefore, in the scan flip-flop circuit 11'',
There are (1) a test mode in which the test mode setting signal T input is at the "1" level, and (2) a normal mode in which the test mode setting signal T input is at the "0" level, each of which operates as described below.

First, in the test mode, the output of the OR gate 33 is “1”.
'', the data multiplexer 30 selects and outputs the output obtained by exclusive ORing the data input and the enable signal EN, and when the system clock CK input becomes 41'', the D-type flip-flop circuit FF outputs the data. The selected output of the multiplexer 30 is read and output to the data output Q terminal.

Furthermore, in the normal mode, if the enable signal EN is '1', the output of the OR gate 33 becomes '1', and the data multiplexer 30 is connected to the data input and the AND gate 32.
selects and outputs the output (that is, data input D) that has exclusive OR logic with the output (at this time, the test mode setting signal T input is "02, so it is "0"); When the system clock CK input reaches "1m," the D-type flip-flop circuit FF reads the selected output of the data multiplexer 30 and outputs it to the data output Q terminal. On the other hand, if the enable signal EN is O", the output of the OR gate 33 becomes "0", the data multiplexer 30 selects and outputs the data output Q of the D-type flip-flop circuit FF, and outputs the system clock CK. Even if the input becomes '1', the D-type flip-flop circuit FF holds the data output Q.

Therefore, when testing the case where the scan flip-flop circuits 11'' as described above are used in the circuit shown in FIG.
・Combination circuit section 1 connected to the data input terminal of
0 and the combinational circuit section 10 connected to the enable signal EN input terminal, the logic level of the input (data input or enable signal EN input) of the exclusive OR gate 31 is different, and the exclusive OR gate 31 The OR output is “
Since the value is different from the expected value, the combinational circuit section 10 can be tested. Further, during normal operation, the normal mode is set. In this case, the scanning flip-flop circuit 11"... will only enable the system clock CK and read the data input if the enable signal EN input is "11" when the system clock CK is input. .

[Effects of the Invention] As described above, according to the present invention, the combinational circuit section connected to the data input terminal of the scanning flip-flop circuit and the combinational circuit section connected to the enable signal input terminal, Since testing can be performed individually or simultaneously, it is possible to realize a semiconductor integrated circuit that can significantly improve the failure detection rate of test patterns and the failure detection rate of the entire circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a part of an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a logic circuit diagram showing a specific example of the scan flip-flop circuit in FIG. 1, and FIG. 1 is a logic circuit diagram showing another specific example of the scanning flip-flop circuit shown in FIG. 1, FIG.
The figures show operating waveforms of the scanning flip-flop circuit in Fig. 4, Fig. 6 is a configuration explanatory diagram showing part of another conventional semiconductor integrated circuit employing a scan design, and Fig. 7
The figure shows the operating waveforms of the scan flip-flop circuit in FIG. 6, and FIG. 8 shows the combinational circuit connected to the data input terminal of the scan flip-flop circuit in FIG. 6, and the combination connected to the enable signal input terminal. FIG. 3 is a diagram showing the relationship between circuit parts. 10...Combination circuit section, 11.11"...Scan flip-flop circuit with enable function, 12...
・System clock signal line, 13.14... Shift clock signal line, 15.16... Test mode setting signal line, SO... Shift out data, Sl... Shift in data, SDI... Shift Data input, SDO・
...Shift data output, FF...D type flip-flop circuit, 20.30...Data multiplexer, 21
．． 33...OR gate, 31...Exclusive OR gate, 32...AND gate.

Claims (2)

[Claims] (1) A scan flip-flop circuit with an enable function that shifts input test data and sets it to the input terminal of a combinational circuit to be tested, reads the output data from the output terminal of the combinational circuit, shifts it, and outputs it. In the semiconductor integrated circuit that employs a scan design, the scan flip-flop circuit with an enable function generates an enable signal according to a combination of logic levels of a first test mode setting signal input and a second test mode setting signal input. The first test mode reads the data input from the combinational circuit regardless of the input "1" or "0", and the first test mode reads the enable signal input from the combinational circuit regardless of the data input "1" or "0". A second test mode in which the system clock is input and a normal mode in which the system clock is enabled and data input is read only if the enable signal input is “1” when the system clock is input. Features of semiconductor integrated circuits. (2) A scan flip-flop circuit with an enable function that shifts input test data and sets it to the input terminal of a combinational circuit to be tested, reads and shifts the output data from the output terminal of the combinational circuit, and outputs the shifted data. In a semiconductor integrated circuit employing a scan design, the scan flip-flop circuit with an enable function receives the data input from the combinational circuit and the enable signal when the system clock is input, depending on the logic level of the test mode setting signal input. There is a test mode that performs exclusive OR logic with the input and outputs the output, and a normal mode that enables the system clock and reads the data input only if the enable signal input is “1” when the system clock is input. A semiconductor integrated circuit characterized by being selectively configured.