JPH037971B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a digital signal processor (hereinafter referred to as DSP).
The present invention relates to an arithmetic unit.

BACKGROUND ART A conventional DSP arithmetic unit is shown in, for example, the μPD7720 Signal Processor User's Manual (published by NEC Corporation).

Fig. 2 shows a block diagram of the arithmetic unit of this conventional DSP, and 1 and 2 are an accumulator A and an accumulator B for temporarily storing data.
(hereinafter referred to as AccA and AccB), 3 is an ALU with two inputs P and Q, 4 is a multiplexer that selects the P input of ALU3, 5 is a shifter that shifts the output of AccA1 or AccB2, and 6 is a data A memory, 7 a multiplier, and 8 an internal bus.

When performing an operation in ALU3 in the DSP arithmetic unit configured as above, the Q input of ALU3 is given the value of AccA1 or AccB2, and the P
The input is given by the output of multiplexer 4. The calculation result is stored in the same accumulator as the one selected for the Q input of ALU3. Furthermore, since the DSP as a whole needs to process at high speed, it is designed to be able to transfer data in parallel with the calculations by the ALU3. For example, in the arithmetic device shown in Fig. 2, (AccA←(AccA)op (data memory) AccB←(AccA), where ( ) is the output of the block shown in ( ), op is the operation by ALU3, ← indicates that the output of the block on the right side of ← is stored in the block on the left side of ←.

This operation can be performed. this is
The Q input of the ALU 3 is set as AccA1, the P input of the ALU 3 is operated on the data memory 6 by the multiplexer 4, and before storing the result of the operation in AccA1, the contents of AccA1 are stored in AccB2.

Problems to be Solved by the Invention However, with the above configuration, the operation (AccA←(AccA)op(AccB) data memory←(AccA) cannot be performed because the data memory 6
This is because, although it is necessary to use the internal bus 8 to transfer data to, the internal bus 8 is used to provide the output of AccB2 via the multiplexer 4 to the P input of the ALU3. Therefore, to execute this, calculation and transfer must be executed separately, resulting in twice the execution time. On the other hand, the data memory of a DSP can generally only be read or written once per machine cycle, so being able to access the data memory in each machine cycle is important for increasing the overall processing speed of the DSP. This is the point. Therefore, the above situation will not occur.
Prevents increasing DSP processing speed.

In view of the above-mentioned points, it is an object of the present invention to provide a DSP arithmetic device with high data transfer efficiency, which can transfer data to a data memory in parallel with calculation even in the above-mentioned cases.

Means for Solving the Problems The present invention provides a two-port type register file, first and second data buses to which the outputs of the register file are connected, and an arithmetic circuit that receives a value as an arithmetic input and outputs the result to the register file; a first selector that outputs one of the first and second data buses to the register file; and a data memory that stores data; The computing device includes the data memory and a second selector that connects either the first or second bus.

Effect The present invention has the above-described configuration, and the first and second
loading data on any data bus into a data memory or register file, or
It is possible to simultaneously perform an output of the data memory or the register file to either the first or second data bus and an operation using data on the first and second data buses.

Embodiment FIG. 1 shows a block diagram of an arithmetic unit in an embodiment of the present invention. In Figure 1, 1
0 is two input terminals IA, IB and two output terminals
It is a 2-port type register file with OA and OB, and consists of register A11 and register B12. 13 is data bus A, 14 is data bus B, 15 is data bus A13, data bus B1
an arithmetic circuit that performs an arithmetic operation between the data on the register file 10 and outputs the result to the input terminal IA of the register file 10;
16 is a selector that connects either the data bus A 13 or the data bus B 14 to the input terminal IB of the register file 10; 17 is a data memory that stores data; 18 is a data pointer that provides an address to the data memory; 19 is a data memory 17 This is a selector that connects the data bus A13 to either the data bus A13 or the data bus B14.

The operation of the arithmetic device of this embodiment configured as described above will be explained below according to the case.

(a) (Register A ← (Register A) op (data memory) Register B ← (Register A) The contents of register A11 are output to data bus A13, and the data at the address indicated by data pointer 18 is output to data bus B14. memory 1
The contents of 7 are outputted via the selector 19, and the result of the calculation in the calculation circuit 15 is stored in the register A11. Further, data on the data bus A13 is stored in the register B12 via the selector 16. That is, the contents of register A11 are copied to register B12.

(b) (Register A ← (Register A) op (Register B) Data memory ← (Register A) The contents of register A11 are output to data bus A13, and the contents of register B12 are output to data bus B14, and the arithmetic circuit 15 The data on the data bus A13 is stored in the data memory 17 at the address indicated by the data pointer 18 via the selector 19. That is, the contents of the register A11 are stored in the data memory 17. will be forwarded to.

(c) (Register A ← (register A) op (data memory) Register B ← (data memory) The contents of register A11 are on data bus A13, and the data pointer 18 is on data bus B14.
The contents of the data memory 17 at the addresses indicated by are outputted via the selector 19, respectively,
It is calculated by the calculation circuit 15 and stored in the register A11. Furthermore, data on the data bus B14 is stored in the register B12 via the selector 16. That is, the contents of data memory 17 are transferred to register B12.

(d) (Register A ← (Register A) op (Register B) Data memory ← (Register B) The contents of register A11 are output to data bus A13, and the contents of register B12 are output to data bus B14, and the arithmetic circuit 15 The data on the data bus B14 is stored in the data memory 17 at the address indicated by the data pointer 18 via the selector 19.In other words, the contents of the register B12 are stored in the data memory 17. Transferred to 17.

It is clear that the essence of the operation of the register A11 and register B12 used in the above explanation does not change even if their positions are reversed.

As described above, according to this embodiment, the register file 10 is of a two-port type, and the selector 1
By providing 6 and 19, the data memory 17 can be accessed in all cases where the arithmetic circuit 15 performs an operation using the register file 10 and the data memory 17, and the data necessary for the operation can be accessed from the data memory 17. or direct transfer of data extracted from the register file 10 to the data memory 17 for calculation.

Effects of the Invention As explained above, according to the present invention, the data memory can be accessed in all cases of calculations performed using the data memory and register file, and the efficiency of using the data memory can be improved. can. In other words, it is no longer necessary to separately perform operations between registers and transfer the contents of registers to data memory prior to the operation as in the past, and a DSP using the arithmetic unit of the present invention can increase the processing speed of the entire DSP. The practical effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional arithmetic device. 10...Register file, 13...Data bus A, 14...Data bus B, 15...Arithmetic circuit, 16, 19...Selector, 17...Data memory.

Claims (1)

[Claims] 1 A two-port register file that temporarily stores data and has first and second output terminals and first and second input terminals, and the first and second output terminals of the register file are connected, respectively. A calculation is performed using the first and second data buses and the first and second data buses as input, and the result of the calculation is sent to the register in the register file that outputs the data to the first data bus. an arithmetic circuit that outputs data through a first input terminal of the register file; a first selector that connects one of the first and second data buses to the second input terminal of the register file; and data that stores data. a memory, a data pointer giving an address to said data memory, and said data memory and said first
and a second selector that connects either one of the buses and the second bus.