JPH037439A - Monitoring system for digital communication channel - Google Patents

Abstract

PURPOSE:To prevent a malfunction by providing a 3rd line monitoring means detecting the bit error of the entire communication channel at a reception terminal station and a means raising a line deterioration alarm with ORing signals representing faults being the result of detection of 1st-3rd line monitoring means. CONSTITUTION:A deterioration detection circuit 47 detects a bit error rate between terminal stations and sends an output when the error rate exceeds a prescribed threshold level. The detection output is faulty from its occurrence time t1 when the disconnection of the line takes place on the midway section and the faulty state is consecutive till the time when the fault is recovered. Then even when a frame synchronization fault is not detected for a short time between times t1 and t2, the detection output of the deterioration detection circuit 37 compensates it and an alarming output from an OR circuit 38 is sent consecutively. Thus, even when the line is switched by the OR circuit 38, misrecognition that a line is recovered due to interrupted alarm output caused by a delay in the fault detection of the frame synchronization does not take place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used in digital communications. The present invention is utilized to monitor a digital communication line in which a large number of repeaters are inserted and connected in cascade.

The present invention is suitable for use in digital wireless communication systems.

The present invention is suitable for use in a system that automatically switches between a working line and a protection line based on a line deterioration alarm.

[Conventional technology]

Conventionally, in multi-relay digital wireless transmission systems, quality deterioration due to a decrease in the bit error rate of a wireless line is detected in each relay section, and the detection results are superimposed on the main signal of that line as monitoring information and transmitted. At stations, a technique is widely used that sends out an alarm signal for line switching when an abnormality is received in the monitoring information.

FIG. 6 is a block diagram of a conventional system. A digital signal is transmitted from a transmitting terminal station to a single communication line, is relayed by a large number of repeaters provided along the way, and reaches the receiving terminal station. FIG. 6 shows only one of the many repeaters, and moreover, with respect to the repeater and both terminal stations, only blocks related to line monitoring, which are closely related to the present invention, are shown.

In FIG. 6, in the repeater, the frame synchronization detection circuit 22
Frame synchronization is detected, and the bit error rate of the immediately preceding relay section is detected by the deterioration detection circuit 23. This deterioration detection circuit 23 calculates a CRC or parity using a bit error detection signal included in the received signal.
Bit errors in the immediately preceding section are detected, and when the error rate is greater than a predetermined threshold, monitoring information is inserted into predetermined information transfer bits of the main signal and transmitted. FIG. 7 is a frame configuration diagram of this main signal, in which an information transfer bit insertion position A is set within one frame, and within this insertion position A, the bit position assigned to the repeater is 1-bit monitoring information indicating an abnormality in the detection output of the deterioration detection circuit 23 is transmitted.

At the receiving terminal station, the frame synchronization detection circuit 32 similarly detects the received signal, and the deterioration detection circuit 3 similarly detects the frame synchronization detection circuit 32.
3 to detect the deterioration of the bit error rate in the immediately preceding relay section. Further, at the receiving terminal station, the bit detection circuit 35 detects the monitoring information inserted into the above-mentioned main signal and transmitted. This monitoring information is taken out via the flip-flop circuit 31. Since the monitoring information of this flip-flop circuit 31 is one bit, which is extremely short, the flip-flop circuit 31 is a circuit for continuously transmitting an abnormality for a predetermined period of time when a bit indicating an abnormality is received. Frame synchronization detection circuit 3
2 frame asynchronous signal, abnormal bit error rate in the immediately preceding section of the deterioration detection circuit 33, and flip-flop circuit 3
The OR circuit 38 performs a logical sum on the signals whose monitoring information obtained from the output No. 1 indicates an abnormality, and outputs an alarm.

[Problem to be solved by the invention]

Although this method is widely used, the following phenomenon was observed during long-term operation tests. To explain using FIG. 8, it is assumed that the bit error rate changes in one relay section as shown in FIG. 8(a). This is one typical example.

The deterioration detection circuit 23 in the relay section is activated at time t. This is detected and the deterioration information is sent out as shown in FIG. 8(b). This is transferred to the receiving terminal station, but the reception status of this monitoring information at the receiving terminal station may become as shown in FIG. 8(C).

That is, if a deterioration occurs that causes the signal to be disconnected at time t1 in FIG. 8(a), frame synchronization of that line cannot be achieved, so the signal will be disconnected in the section following the relay section where the deterioration occurred. When the signal loss condition is restored at time t3, frame synchronization is restored and this monitoring information is transmitted again.

In the prior art, the frame synchronization detection circuit 32 of the receiving terminal station also monitors the frame synchronization, and if there is an asynchronous condition or a problem, an output is generated in the OR circuit 38, so the signal is interrupted at time t1. If this happens, the frame synchronization becomes abnormal and the abnormality should be detected continuously, but in an actual line, something like the one shown in FIG. 8(d) occurs. In other words, it takes a certain amount of time to detect that frame synchronization is abnormal, and time t1
Even if frame synchronization is lost, this is detected a little later at time t2.

The short time t from time t1 to time t2 is shown in Fig. 8 (
As in C), the monitoring information is not received and the deterioration disappears.
Frame synchronization abnormalities will also not be detected. This time 1. During the time t from 1 to t2, the alarm output is temporarily stopped as shown in FIG. 8(e), and it appears that the line has returned to normal. During this time, the line that was once switched to the protection line may be switched back to the working line.

The inventors attempted to remedy the phenomenon in which information indicating an abnormality disappears in the short time t from time t1 to time t2 by extending the operating time of the flip-flop circuit 31 of the receiving terminal station, but frame synchronization Since there is a probabilistic element in the detection of , and the time t from time t1 to time t2 is not uniformly determined, it has been found that it is not appropriate to reliably avoid this by extending the time of the flip-flop circuit 31.

In other words, if this problem is to be relieved by extending the time of the flip-flop circuit 31, it will be necessary to set the set time of the flip-flop circuit 31 to a considerably long time, which will cause a delay in the operation at the time of abnormality recovery. I found out that I can put it away.

The present invention has such a background, and even when the monitoring information received from the repeater at the receiving terminal station temporarily disappears, indicating that the abnormality in the line has been recovered, the present invention is implemented in a section in the middle of the relay transmission line. It is an object of the present invention to provide a method that prevents line switching from being performed by mistake by continuing to output a warning when an abnormal state continues.

[Means to solve the problem]

The present invention is capable of performing conventional line monitoring, namely: (1) Line monitoring based on monitoring information of each relay section (first line monitoring means); (2) Line monitoring by detecting frame synchronization of the communication line (2nd line monitoring means); ), in addition to ■ line monitoring (third line monitoring means) by detecting bit errors of the entire communication line at the receiving terminal station, the above-mentioned first, second and third line monitoring means It is characterized in that a line deterioration alarm is generated based on the logical sum of signals indicating an abnormality in the detection results.

[Effect]

By determining that the line is abnormal when any of the three pieces of information above indicates an abnormality, it is possible to indicate that the line is abnormal in the short time it takes to detect that the frame synchronization is abnormal as described above. This prevents the signal from disappearing and prevents line switching from being performed erroneously.

〔Example〕

FIG. 1 is a block diagram of a method according to an embodiment of the present invention. A communication line is constructed by inserting and connecting a large number of repeaters in cascade between a transmitting terminal station and a receiving terminal station that constitute a relay transmission path in a digital wireless transmission system.

FIG. 1 illustrates a transmitting terminal station, a receiving terminal station, and one repeater between them. Furthermore, regarding the configurations of the transmitting terminal station, receiving terminal station, and repeater, only circuits directly related to the present invention are illustrated.

In the repeater, a frame synchronization detection circuit 22 detects frame synchronization, and a deterioration detection circuit 23 detects the bit error rate of the immediately preceding repeat section. The deterioration detection circuit 23 calculates a CRC or parity using a bit error detection signal included in the received signal, detects a bit error in the immediately preceding section, and detects a bit error whose error rate is higher than a predetermined threshold. Sometimes, monitoring information is inserted into predetermined information transfer bits of the main signal and transmitted. FIG. 2 is a frame configuration diagram of this main signal, in which an information transfer bit insertion position A is set within one frame, and within this insertion position, the bit position assigned to the repeater is 1-bit monitoring information indicating an abnormality in the detection output of the deterioration detection circuit 23 is transmitted.

At the receiving terminal station, the frame synchronization detection circuit 32 similarly detects the received signal, and the deterioration detection circuit 3 similarly detects the frame synchronization detection circuit 32.
3 to detect the deterioration of the bit error rate in the immediately preceding relay section. Further, at the receiving terminal station, the bit detection circuit 35 detects the monitoring information inserted into the above-mentioned main signal and transmitted. This monitoring information is taken out via the flip-flop circuit 31. Since the monitoring information of this flip-flop circuit 31 is one bit, which is extremely short, the flip-flop circuit 31 is a circuit for continuously transmitting an abnormality for a predetermined period of time when a bit indicating an abnormality is received. Frame synchronization detection circuit 3
2 frame asynchronous signal, abnormal bit error rate in the immediately preceding section of the deterioration detection circuit 33, and flip-flop circuit 3
The OR circuit 38 performs a logical sum on the signals whose monitoring information obtained from the output No. 1 indicates an abnormality, and outputs an alarm.

Here, the feature of the present invention is that the receiving terminal station is provided with another deterioration detection circuit 37 for calculating and detecting the bit error rate for the signal from the transmitting terminal station to the receiving terminal station.
This detection output is supplied to the OR circuit 38.

That is, in the signal configuration shown in FIG. 2, the bit error rate of each relay section is calculated using pop parity Ph,
The bit error rate for all lines from the transmitting terminal station to the relay terminal station is calculated using section parity Ps.

With this configuration, the receiving terminal station can detect abnormal bit error rates in each intermediate relay section, abnormal frame synchronization, abnormal bit error rates in the immediately preceding relay section, and bit error rate errors between terminal stations. When any abnormality is detected, an alarm indicating line deterioration is sent out.

To explain in detail using FIG. 3, it is assumed that the bit error rate changes in one relay section as shown in FIG. 3(a). This is one typical example. The deterioration detection circuit 23 in the relay section is activated at time t. This is detected and the deterioration information is sent out as shown in Figure 3, et al.

This is transferred to the receiving terminal station, but the reception status of this monitoring information at the receiving terminal station may be as shown in FIG. 3(C). That is, if a deterioration occurs that causes the signal to be disconnected at time t1 in FIG. 3(a), frame synchronization of that line cannot be achieved, so the signal will be disconnected in the section following the relay section where the deterioration occurred. When the signal loss condition is restored at time t3, frame synchronization is restored and this monitoring information is transmitted again. The frame synchronization detection circuit 32 of the receiving terminal station also monitors frame synchronization, and the frame synchronization detection circuit 32
The detection output is as shown in FIG. 3(d).

- Shiki In the device of the invention, the deterioration detection circuit 37 calculates and detects the bit error rate between terminal stations, and sends out an output when this error rate exceeds a predetermined threshold.

A signal as shown in FIG. 3(e) is obtained as the detection output. If a line disconnection occurs in the middle of the section, this detection output will be output at the time of occurrence 1. It becomes abnormal from then on, and the abnormal state continues until the time when it recovers (generally at a time between ts and ts). Therefore, even if an abnormality in frame synchronization is not detected during the short time t from time t1 to time t2, which is the problem described above, the deterioration detection circuit 37
This will be covered by the detection output of , and the alarm output of the OR circuit 38 will continue to be sent out. Therefore, even if the line is switched by the OR circuit 38, there will be no possibility that the alarm output will be interrupted due to a delay in detecting an abnormality in frame synchronization and the user will mistakenly think that the line has been restored.

FIG. 4 is a block diagram of a system according to a second embodiment of the present invention. In this example, a block configuration diagram of a configuration including line switching is shown. Further, in this example, error correction is performed for each relay section, and the bit in which an error has occurred is not transmitted to the subsequent relay section. Note that this method also includes a circuit for detecting frame synchronization and a circuit for sending out an abnormal signal when frame synchronization is abnormal, but these are not shown in Figure 4 because the drawing would be complicated. It is.

FIG. 5 is a signal configuration diagram of this second embodiment system. At the end of the information bits, an information transfer bit for transferring abnormalities in each relay section is assigned, and a check bit for error correction is inserted afterwards. Regarding the information bits, a section parity Ps is placed in the frame and used to detect bit errors on all lines from the transmitting terminal station to the receiving terminal station.

To explain line switching, this communication line has two equivalent lines, one line is the working line and the other line is the backup line.When the above-mentioned alarm output occurs, the transmitting terminal station and the receiving terminal station The configuration is such that the working line is switched to the protection line at the same time. The receiving terminal station is equipped with a line switching control circuit 12, and the transmitting terminal station is equipped with a line switching control circuit 13. Control 10.

Also in this second embodiment, the deterioration detection circuits 37 and 3
7' calculates and detects the bit error rate of all lines from the transmitting terminal station to the receiving terminal station, and sends out an abnormality alarm when the bit error rate exceeds a predetermined threshold. This prevents the receiving terminal station from mistakenly determining that a normal recovery has occurred when the error continues.

Note that the bit error rate abnormality detection threshold for all lines can be set in a state where frame synchronization does not become abnormal, and in this way the detection threshold can be set in a state where the degree of deterioration has not progressed relatively. It is effective to do this in practical lines. Furthermore, a simple configuration using a parity method is sufficient for error rate detection for all line sections, and implementing the present invention has almost no economic impact on the entire device.

〔Effect of the invention〕

As described above, according to the present invention, even if an abnormal condition continues in a section in the middle of a relay transmission path, it is no longer possible for the receiving terminal station to become unable to detect it. Therefore, according to the present invention, there is no possibility that a line abnormality alarm is interrupted and a line that was once switched to a protection line is switched back to a working line that has not actually recovered.

Since the present invention can be implemented by adding a simple device to the receiving terminal station, an increase in device cost due to implementing the present invention is hardly a problem. Further, since it is not necessary to substantially change other standards by implementing the present invention, there is an advantage that the present invention can be implemented easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the system according to the first embodiment of the present invention. FIG. 2 is a signal configuration diagram of the first embodiment system. FIG. 3 is an explanatory diagram of the operation. FIG. 4 is a block diagram of a system according to a second embodiment of the present invention. FIG. 5 is a diagram of the signal configuration. FIG. 6 is a block diagram of a conventional system. FIG. 7 is a diagram of the signal configuration. FIG. 8 is an operation explanatory diagram for explaining the problem of the conventional method. DESCRIPTION OF SYMBOLS 11... Transmission signal processing circuit, 22... Frame synchronization detection circuit of a repeater, 23... Deterioration detection circuit for detecting degradation of bit error rate in the immediately preceding section, 24... Bit insertion circuit, 31. . . . Flip-flop circuit, 32 . . . Frame synchronization detection circuit of receiving terminal station, 33 .
- Bit detection circuit that detects the monitoring information bit inserted into the main signal, 36... Reception code processing circuit, 37... Deterioration detection circuit that detects the bit error rate from the transmitting terminal station to the receiving terminal station, 38 ...AND circuit.

Claims (1)

[Scope of Claims] 1. A first line monitoring means that monitors the line by detecting bit errors in a plurality of relay sections constituted by a plurality of relay devices cascaded and connected to one communication line; , means for superimposing the monitoring result of the first line monitoring means on a signal transmitted to the communication line, and detecting frame synchronization of the communication line at a receiving end station of the communication line, thereby monitoring the line. and a second line monitoring means for monitoring the digital communication line, the third line monitoring means for monitoring the line by detecting bit errors of the entire communication line at a receiving end station of the communication line. and means for generating a line deterioration alarm based on a logical sum of signals indicating an abnormality in the detection results of the first, second and third line monitoring means.