JPH0338786B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a serial data receiving circuit, and more particularly to a serial data receiving circuit that enables noise removal.

FIG. 1 is a connection diagram of a serial transmission system in a one-line system, FIG. 2 is a block diagram of a receiving circuit in a conventional serial transmission system, and FIG. 3 is an example of the time chart. In the figure, T is the transmitting side, R is the receiving side, L is the signal line, SR is the shift register, C ₁ and C ₂ are the counters, O is the oscillator, and G
indicates a gate. Next, the operation will be explained with reference to a data transfer time chart shown in FIG. In FIG. 3, a is the transmission signal, b is the read timing at the receiving side R, which triggers a change in logic level from "1" to "0" at the receiving side R, and the counter _C1 starts counting, t ₀ hours later counter C ₁
The input signal line was sampled with the output of , and when it was "0" again, the counter C ₂ was activated, and thereafter the counter C ₂ sampled every 2t ₀ hours and read it into the shift register SR. In this example, the first
“1” as the bit, “0” as the second bit
are hereinafter referred to as "0", "0", "1", "0", etc. Therefore, if noise appears on the data line L while the receiving side R is waiting for a start bit to be input, the receiving side R will be impressed by the change in the data line L from "1" to "0" and will not perform the receiving operation. It starts. Even when such severe noise does not occur, the waveform becomes dull due to the wiring capacitance of the signal line, making it difficult to identify the start position of the shift register.

For this reason, if the detection position of the start bit shifts, the sampling position of the data bits following the start bit will shift accordingly, resulting in reading incorrect data or data that is in the process of changing. Furthermore, since the data bits following the start bit are sampled once per bit, if noise is present during sampling,
The drawback was that there was a high risk of reading incorrect data.

The present invention eliminates such conventional drawbacks, and includes a start signal generation circuit that outputs a start signal when M logic values of n sampled start bits are input, and a start signal generation circuit that outputs a start signal when M logic values of n sampled start bits are input. The device has a read signal generating means for generating a read signal of the majority decided value.

This is to avoid malfunctions or erroneous readings due to noise. An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a block diagram of a serial data receiving circuit according to the present invention, in which 1 is an input signal line of an n-stage shift register 3, 2 is a clock signal line thereof, 4 is a block diagram having n inputs, and 4 has n inputs. ”M inputs (n≧M)
In the above case, the logic level "1" is output to OUT0, and the majority decision result of the n inputs is output to the majority decision output OUT1.The decoder 5 outputs the logic level "1" output from the start signal output OUT0. An n-ary counter is used as an instruction input to start frequency division and counts a clock signal, 6 is an oscillator, 7 is a shift register, and 8 is an AND gate. Fifth
The figure is a time chart of each part in Fig. 4, where a is an example of the serial signal input to the input signal line 1, b is the clock signal output from the oscillator 6, c is the output of OUT0 of the decoder 4, and d is also the output of OUT1. output, e
is the output of the gate 8, and f, g, h are the outputs of the first stage, second stage, and third stage of the shift register 7, respectively.

To operate this, suppose that serial data as shown in FIG. 5a is received. The n-stage shift register 3 samples and reads this signal a n times using a clock signal b with a period t ₀ /n.
Output sampling data from q ₀ to q _o . The output OUT0 of the decoder 4 outputs a logic value "1" when the number of logic level "0" in the sampling data q ₀ to q _o becomes M or more, as shown in the output waveform c,
Similarly, OUT1 outputs the majority decision result of the sampling data q ₀ to q _o as shown in the output waveform d. The n-ary counter 5 starts with the pulse of _C1 in the output waveform of OUT0 as a start signal, and starts with the n-ary pulse of the clock signal.
Start counting. The AND circuit 8 performs an AND logic between the predetermined value output of the n-ary counter and the clock signal, and generates a read signal as shown in the output waveform e. Shift register 7 is OUT1 of decoder 4
Inputs the majority vote result output and read signal, reads the logic level at the time of input of the majority vote result read signal, and outputs output waveforms f, g, and h as outputs of the first, second, and third stages, respectively. .

As a result, the shift register 7 has input signal line 1.
The data sent to the system will be recorded in the correct order.

In this way, the start bit is detected when the logic level "0" of the first input start bit is input to the shift register 3 for more than M/n of time _t0 , so it is difficult to know the change point of the start bit. It is possible to generate a read signal without any need. Therefore, a read signal can be generated even if the start bit signal is distorted and the starting point of the start bit cannot be detected.

Furthermore, if there is noise in the start bit and data bit, the decoder's OUT0 output will be
Since a start signal consisting of a logic level "1" is not generated unless the number of logic level "0"s is M or more input, if there is little noise, the shift register 7 is made to read the majority vote result at a relatively early timing. If there are many, the shift register 7 is made to read the majority vote result at a relatively late timing. This makes it possible to vary the majority interval depending on the amount of noise.
It will be possible to take a majority vote based on the noise.

In this way, every time _t0 , that is, every time M/n or more of the input bit time width is input to the shift register 3, a "0" or "1" determination is made from the output contents of the shift register 3. Since this is done by majority vote, even if there is noise on signal line 1 and erroneous data at that moment is read on the receiving side, the number of erroneous data reads due to noise and the unnecessary data of M/n or less in shift register 3 will be reduced. The sum of the number of reads is
M/n bits or more in the shift register are compared in size with the number of times the data was read when there was no noise, and cannot be valid in determining the read data, and incorrect data due to noise is invalid. This means that you have received the correct data.

As explained in detail above, according to the present invention, the detection of the start bit and the determination of the logic level of the input data are performed based on the cumulative number of logic levels of the input data over a certain period of time in the past. Even if it gets mixed in, it will be removed as a result. Therefore, it can be used in places that require a transmission system that is resistant to noise and has great effects.

[Brief explanation of drawings]

Figure 1 is a connection diagram for a one-line serial transmission system, Figure 2 is a block diagram of a serial data receiving circuit in a conventional serial transmission system, Figure 3 is a diagram showing an example of the time chart, and Figure 4 is a diagram showing an example of the time chart. FIG. 5 is a block diagram of a receiving circuit showing one embodiment of the serial data receiving circuit of the present invention, and is also an example of a time chart of each part thereof. 1...Input signal line, 2...Clock signal line, 3...n
stage shift register, 5...n-ary counter, 6... oscillator, 7... shift register, 8... gate.

Claims (1)

[Claims] 1. In a serial data receiving circuit to which serial data consisting of a start bit having a predetermined logic level and data bits following the start bit is input, the serial data is sequentially input, and the serial data is a first n-stage storage circuit that samples the logic level n times using a clock signal and outputs n signals; and inputs the n output signals of the storage circuit, and the logic value of the start bit is determined by the number of sampling times. a start signal generation circuit that outputs a signal of a predetermined logic level when M fewer than n input signals are input; and a start signal generation circuit that receives n output signals of the storage circuit and outputs a majority result signal of the n sampling data. a majority circuit; an n-ary counter that starts counting upon receiving the output signal of the start signal generation circuit and outputs a count signal in response to an input clock signal; and when the output signal of the counter is a predetermined value; 1. A serial data receiving circuit comprising: means for generating a read signal at a time; and a second storage circuit for reading the majority vote result signal using an output signal of the read signal generating circuit.