JPH03269592A - Musical sound generating device - Google Patents

Abstract

PURPOSE:To read and write parameters fast by using random access memories as registers in a sound source and writing data in optional channels, reading and using the random access memories in parallel alternately. CONSTITUTION:Parameters featuring a musical sound to be generated can be stored in optional addresses of the random access storage means 16 and 17. Write and read means 11 - 15 write the parameters in the random access storage means 16 and 17 and read the parameters out of the random access storage means 16 and 17 in order. Thus, the parameter storage means are composed of the random access storage means 16 and 17, so data can be write in optional channels irrelevantly to channel counters and the random access storage means 16 and 17 are read out and used in parallel alternately. Consequently, the parameters can be written and read out fast.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a musical tone generator applied to electronic musical instruments, etc., and more specifically, to a musical tone generating device that is applied to electronic musical instruments, etc. musical tone generator, and random access memory (RAM).
) in parallel to alternately read and use data.

[Prior Art] Conventionally, in electronic musical instruments, various parameter values are written into a plurality of shift registers (parameter storage means) that store parameters, and musical tones are generated with tones according to these parameters.

For example, in an FM sound source of an electronic musical instrument, parameter values (timbre data, etc.) are stored in the shift register of a predetermined channel in order to give a frequency number (F number) to the carrier operator and modulator operator inside the musical tone forming means.
It was necessary to write

[Problems to be Solved by the Invention] By the way, in a musical tone generating device having such a conventional parameter storage means, there is a method of detecting coincidence between a channel counter and a write channel register, and generating a write signal to perform writing. A method was adopted.

Therefore, one register write takes at most the time required for the channel counter to complete one cycle.

For example, when writing parameter data from the CPU to a register continuously, after instructing to write one data, you may have to wait for the channel counter to complete one cycle before writing the next data. There was a problem.

SUMMARY OF THE INVENTION In view of the above-mentioned problems with the conventional type, it is an object of the present invention to provide a musical tone generating device for use in electronic musical instruments, etc., which is capable of speeding up the writing and reading of parameters.

[Means for Solving the Problems] In order to achieve the above object, the musical tone generating device according to the present invention includes random access storage means that can store parameters characterizing the musical tone to be generated at arbitrary address locations. , characterized in that it comprises a writing means for writing parameters into the random access storage means, and a reading means for sequentially reading out the parameters from the random access storage means.

However, the random access storage means is accompanied by a certain degree of operational delay, and when reading parameters from the random access storage means in time with the high-speed time-division musical tone synthesis calculation of the tone generator circuit, the readout operation may not be in time. There was also. Therefore, in the present invention, in order to speed up the read operation, the first parameter storage means and the second parameter storage means that store parameters characterizing the musical tone to be generated are further provided, and the first parameter storage means and A means for instructing the second parameter storage means to write and read parameter data at the same address and a signal that switches between "O" and "1" at high speed are input, and as the signal is switched, output means for switching between outputting the parameter data of the first parameter storage means and outputting the parameter data of the second parameter storage means; inputting the parameters output from the output means; It is characterized by comprising a musical tone forming means for forming a musical tone.

[Operation] According to this configuration, since the parameter storage means is constituted by random access storage means, data can be written to any channel regardless of the channel counter. A read operation using a channel counter and a write operation by specifying a channel may be performed in a time-sharing manner.

Also, if you parallelize the RAM and read and use it alternately, the speed of the RAM will be somewhat lower than that of a shift register, etc.
It is possible to read parameters at sufficient speed using .

[Example] Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an electronic keyboard instrument to which a musical tone generator according to an embodiment of the present invention is applied.

In this figure, key press data generated by pressing keys on a keyboard 2 is manually input to a microcomputer 4 via an interface 3.
After predetermined processing, input is made manually to the interface 11 of the musical tone generator (sound source) 1.

Similarly, operation data generated by operating operators 5 such as various panel switches is input to the microcomputer 4 via the interface 6, and after predetermined processing is input to the interface 11 of the sound source 1.

Sound source 1 includes interface 11, latch 12゜13,
It includes a differentiation circuit 14, a clock generator 15, a channel register section 16, a voice register section 17, and a tone generation block (tone generation means) 18.

Parameters such as timbre data are inputted from the microcomputer 4 to the interfinice 11 after being divided into addresses and data.

This address is an address indicating to which storage location of a register in the channel register section 16 or voice register section 17 data is to be written. This address is information that specifies the channel and slot, as will be described later.

This channel and slot specific information is latched as data in the latch 13 at the output timing of the write signal WR, and transferred to the channel register section 16 or voice register section 17.

Immediately after transferring the channel and slot specific information corresponding to the address in the register, the parameter data to be actually written into the register is transferred. This parameter data is latched to 1 at the rising timing of the write signal WR output.
3 is stored.

On the other hand, the register address specifying the register is latched into the latch 12 at the rising timing of the output of the write signal WR. The latched register address RAD is input from the latch 12 to the channel register section 16 or the voice register section 17. The parameter data WRD stored in the latch 13 is then stored in the channel register section 1.
6 or voice register section 17, and is stored in a designated storage location of a designated register inside channel register section 16 or voice register section 17 at the output timing of write signal pulse WRP.

The write signal WR passes through the differentiating circuit 14 and is outputted to each register section as a write signal pulse WRP at an appropriate timing.

The clock generator 15 outputs a clock signal that defines the write and read timing of registers and the like. Specifically, the clock generator 15 generates pulse signals φ0 to φ6 . φS1 to φS4 are generated. φO
~φ6 is 2° bits for φ0, 21 bits for φ1,
The value of each digit is output when 7-bit data with φ2 as a 22-bit digit, φ6 as a 26-bit digit is sequentially counted up. Among these pulse signals φ1 to φ6 are used for writing to and reading from the register. The apparatus of this embodiment has 16 time-division sounding channels, each channel consisting of four time slots corresponding to four operators. In order to specify each operator and write parameters, it is necessary to specify the channel and operator. Therefore, in the device of this embodiment, the upper 4 bits φ6 to φ3 are used as a channel counter for specifying the channel, and the lower 2 bits φ2 . φ1 is used as a slot counter to identify the operator. Furthermore, slot/sort signals φS1 to φS4 representing the timing of each slot are output.

The channel register section 16 includes a plurality of registers that store parameter data for each channel. Parameters for each channel stored in this register include, for example, the frequency number (F number), initial phase, depth of the low frequency oscillator LFO for applying vibrato to the musical tone signal, and interpolation of several aftertouch detection values. There are touch EG (envelope generator) data to make aftertouch work smoothly, and attack rate and peak level to apply to each channel to make the most of initial touch. Furthermore, the channel register stores a voice number for specifying parameter data for each voice to be stored in the voice register section 17.

The voice register section 17 includes a plurality of registers for storing parameter data for each voice. The data stored in this voice register includes, for example, data that instructs a musical tone synthesis calculation algorithm that specifies the timbre of each voice, EG level and rate data, LFO data, and attack pitch data for each operator. and so on. In this example, the channel register is 1
It is designed to be able to store data for 6 channels, and the voice register that contains parameter data that determines timbres can store parameter data for 8 timbres.

The tone data of the voice register designated by the voice number stored in the channel register is transferred to the musical tone generation block 18. The musical tone signal (digital value) output from the musical tone generation block 18 is input to the sound system 8 via the digital/analog converter 7, and is generated as a musical tone.

FIG. 2 is a detailed block circuit diagram of the channel register section 16 of the electronic musical instrument of this embodiment.

FIG. 3 is a detailed block circuit diagram of the differential circuit 14 of this electronic musical instrument. FIG. 5 is a block circuit diagram showing the configuration of the voice register section 17.

Referring to FIG. 2, the channel register section 16 includes address decoders 21, 22, and 23 that input and decode a register address RAD. 24, 25.26
are the ANDs of the decoded signals of the address decoders 21, 22, and 23 and the write signal pulse WRP, respectively.
This is the D circuit.

The output of the AND circuit 24 is input to the channel and slot instruction latch 27 as a write instruction signal.

The sound source of this embodiment is of a type in which four operators are combined using various algorithms to form one voice. Therefore, in order to provide parameters for each operator, each channel has four time timings (slots) corresponding to four operators.

Therefore, the location within the register of the parameter to be written is specified by channel and slot. Latch 27 latches the channel and slot instruction data at which parameter data is to be stored. The output of latch 27 is 6 bits. Since there are 16 channels, 4 bits of information are needed to specify the channel, and since there are 4 slots, 2 bits of information are needed to specify the slot.
The bits are channel information and the lower two bits are slot information.

The selector 28 selects the data of the latch 27 or the counters φ6 to φ6 according to the timing of the slot signal φs4.
Data of φ1 is selected and output.

29, 31, and 33 are channel registers that store parameter data for each channel.

There are two types of channel registers: one type that stores common parameter data for all four operators in a channel, and the other type that stores different parameters for each operator in a channel.
There are two types.

Two are parameters common to all operators of the channel (
For example, it is a register that stores an F number indicating pitch, a voice number indicating the timbre of the channel, etc.). The register 29 is a register having a storage area for storing parameter data for the number of channels (16 pieces). The register 29 receives a write signal output from the AND circuit 25. The selector 28 outputs the 6-bit data stored in the latch 27 (the upper 4 bits specify the channel, and the lower 2 bits specify the slot), but the two registers only need to specify the channel. Therefore, only the upper 4 bits of the 6-bit output of the selector 28 are manually input. Furthermore, the WRD of parameter data to be written is manually entered into two registers.

The registers 31 and 33 are of a type that stores parameters for each operator in the channel (eg, attack rate, peak level, etc. for each operator). Registers 31 and 33 have a parallel structure, and data at even addresses is written to register 31 (first parameter storage means), and data at odd addresses is written to register 33 (second parameter storage means). be included. Inverter 36 and AND circuit 37°3
8 realizes the parallel structure of this register 31,33. That is, of the 6-bit channel and slot specifying data output from the selector 28, the lower 1 bit is inputted to the AND circuit 37 via the inverter 36. This lower 1 bit is also input manually to the AND circuit 38.

AND circuits 37 and 38 input the output signal (write instruction signal) of the AND circuit 26. The output of the AND circuit 37 is input as a write signal to the register 31, and the AND circuit 3
The output signal of 8 is input to the register 33 as a write signal. Therefore, of the 6-bit channel and slot specific data output from the selector 28, the lower one
If the bit is “0”, register 31 is written;
Writing to the register 33 is performed when this lower one bit is "1". Write data WRD is input to the register 3133.

Since register 31 and register 33 have a parallel structure in this way, only the upper 5 bits need to be used for the address data for these registers 3133.

That is, the upper five bits from the selector 28 are manually input to the registers 31 and 33.

A latch 30 is provided for reading out the parameter data in the register 29. Additionally, latches 32 and 34 are provided for reading the parameters of the registers 31 and 33, respectively. Latches 30, 32, 34 store parameters read from their respective registers based on count signal φ1. Latch 30 from 2 registers
Parameters for each channel, such as the F number or voice number, are output via the channel.

The selector 35 is connected to the register 31 via latches 32 and 34.
．． This is a selector for selecting and outputting parameter data output from 33. The selector 35 is a counter φ
Depending on the value of 1, the stored value of the latch 32 or 34 is output. This parameter is, for example, attack rate or peak level.

Write pulse WRP is synchronized with slot signal φS4, as will be described later. In addition, the selector 28 is connected to the latch 2.
It is at the timing of the slot signal φS4 that the instruction data of channel and slot No. 7 is selected and output.

That is, in the circuit diagram of FIG. 2, each register 29,
Writing to 31.33 is performed at the timing of slot signal φS4.

Next, the write operation in the channel register section 16 shown in FIG. 2 will be explained in detail.

First, data (address information) specifying the channel and slot for writing is stored in the latch 27.

For this purpose, a register address instructing the latch 27 is output to register address RAD, and write data WRD is output.
Channel (upper 4 bits) and slot (lower 2 bits)
bit) data. And the slot signal φ
A write pulse WRP synchronized with s4 is output. As a result, the latch 27 stores write data WRD, ie, data specifying the channel and slot, at the timing of the write pulse WRP.

Next, write the parameter data to be written into the write data WR.
The register address RAD outputs data indicating the register to be written to. Then, a write pulse WRP synchronized with the slot signal φS4 is output.

As a result, if the register 29 that stores parameters for each channel is written, for example, the 6-bit address information that specifies the channel and slot stored in the latch 27 is output from the selector 28 at the timing of the slot signal φS4. be done. Register 29 has A
A write instruction signal is input manually from the ND circuit 25, and
The upper 4 bits of the output from the selector 28, ie, channel data, are input manually. Therefore, write data WRD, that is, parameter data, is written to the channel position designated here.

On the other hand, in the case of storing the iF into the registers 31 and 33 having a parallel structure, data specifying the channel and slot are first stored in the latch 27 in the same manner as described above. next,
The parameter data to be written is output as write data WRD, and the register address RAD is outputted as data indicating the register 31 or 33 to which writing is to be performed. and,
A write pulse WRP synchronized with slot signal φS4 is output.

As a result, 6-bit address information specifying the channel and slot stored in the latch 27 is output from the selector 28 at the timing of the slot signal φS4. When the lower 1 bit of the 6-bit address information output from the selector 28 is "0", the AND circuit 3
A write instruction signal is input from 7 to the register 31. Furthermore, when the lower 1 bit of the 6-bit address information output from the selector 28 is "1", the AND circuit 3
A write instruction signal is manually inputted from 8 to the register 33. The upper five bits of the output from the selector 28 are input to the registers 31 and 33. As described above, write data WRD, that is, parameter data, is written to the storage location designated here.

Next, generation of the write pulse WRP by the differentiating circuit 14 will be explained with reference to FIG.

In FIG. 3, the write signal WR is input to the S terminal of the flip-flop circuit 43, and the inverter 41
Enter. The output of the inverter 41 is output from the AND circuit 42
Enter. The output of the AND circuit 42 is connected to the R terminal of the flip-flop circuit 43. The output of the flip-flop circuit 43 is input to a delay circuit 44, and the output of the delay circuit 44 is input to a latch 45. This latch 45 latches the human data at the timing of the slot signal φS2. The output of the latch 45 is the AND circuit 4
2 and the delay circuit 46. The output of the delay circuit 46 is input to a delay circuit 47 and an inverter 48.

The outputs of the delay circuit 47 and the inverter 48 are AN
Input to four D circuits. AND circuit 49 generates write pulse WRP as its output.

FIG. 4(a) shows a timing chart when the write signal WR rises. As already mentioned, the rise of the write signal WR is the timing at which the latches 12 and 13 in FIG. 1 latch the register address and data, respectively. ■
is the output of the delay circuit 44 and represents the signal of the manual position of the latch 45.

2 indicates a signal at the output of the latch 45 and at the input of the delay circuit 46. As a result, write pulse WRP does not generate a pulse when write signal WR rises.

FIG. 4(b) shows a timing chart when the write signal WR falls. As a result, a write pulse WRP is generated when the write signal WR falls.

As described above, the differentiating circuit 14 generates the write pulse WRP at the timing of the slot signal φS4.

Next, reading out parameter data from the channel register section 16 will be described in detail with reference to FIG.

At the timing of slots other than slot signal φS4, selector 28 selects channel counters φ6 to φ3 (upper 4 bits) and slot counters φ2 . Outputs φ1 (lower 2 bits). This becomes the read address, and the registers 29, 31, and 33 are read. The parameter data read from the register is sent to the slot signal φS.
l, At the timing of φS3, latches 30, 32.3
4 and is taken into the latches 30, 32, and 34 at the timing of the rise of the slot count φ1.

The latches 30, 32, and 34 output the captured data as new data at the timing of the subsequent fall of the slot count φ1. Therefore, the parameter is latch 3 delayed by two time slots from the given address.
Output from 0.32.34.

That is, in two registers, slot signals φSl,
φS2. At the timing of φS3, the parameter data of the channel indicated by the channel counters φ6 to φ3 at that time becomes readable, and the latch 30 receives the slot signal φSl as described above.

It operates at the timing of φS3. As a result, the parameter data in the register 29 is the slot signal φSl, φ
It is read out at the timing of S3 and transferred to the tone generation block 18 in FIG. Further, the read voice number data is transferred to the voice register section 17 and used for reading voice parameters. .

Since the parameter data in the register 29 is accessed using the upper 4 bits of the output from the selector 28, the 16 parameter data for each channel are sequentially read out according to channel counters φ6 to φ3. No data is left unread.

In the registers 31 and 33, the slot signal φSl.

φS2. At the timing of φS3, the parameter data indicated by the counters φ6 to φ2 at that time can be read. As mentioned above, the parameter data of the registers 31.33 is the slot signal φSl of the latches 32.34.
, φS3, and the latch 32.
34, then latched 32 two time slots later.
．． It is output from 34. . After being latched, it can be read at any time. The selector 35 outputs the parameter data of the register 31 when the least significant bit φ1 is “O”, and outputs the parameter data of the register 33 when the least significant bit φ1 is “1”. The read parameter data is transferred to the tone generation block 8 in FIG.

Since the parameter data in the registers '31, 33 is first stored in the latches 32, 34 and then output via the selector 35, there is no data that cannot be read.

Next, the configuration and operation of the voice register section 17 will be explained with reference to FIG.

The voice register section 17 has almost the same configuration as the channel register section 16 described above, and operates similarly. The correspondence relationship is as follows.

■The address decoders 61, 62, and 63 in Figure 5 are
They correspond to address decoders 21, 22, and 23 in the figure, respectively.

(2) AND circuits 64, 65, 66, 78, and 79 in FIG. 5 correspond to AND circuits 24, 25, 26, 37, and 38 in FIG. 2, respectively.

(2) Latches 67, 71, 73, and 75 in FIG. 5 correspond to latches 27, 30, and 32, 34 in FIG. 2, respectively.

■Selectors 68 and 76 in Figure 5 are selectors 2 and 2 in Figure 2.
8.35 respectively.

(2) Registers 70, 72, and 74 in FIG. 5 correspond to registers 29, 31, and 33 in FIG. 2, respectively. Here, the register 70 stores LFO control parameters and frequency glide parameters for each voice.
2.74 stores parameters such as FM algorithm data and EG parameters of each operator.

The differences are that while there are 16 channels, there are 8 voices, and that the selector 68 and its peripheral circuits are different.

Since there are eight whistles, that is, there are eight tone colors that can be set, the latch 67 is a 5-bit latch.

The output of selector 68 is also 5 bits, and the lower one bit is connected to inverter 77 and AND circuit 79. The upper 4 bits are input to each register as address information. However, since the register 70 is a register that stores parameters for each of the eight voices, the upper three bits are sufficient.

The selector 68 selects an output in accordance with a 2-bit input with the slot signal φS4 as the upper bit and the slot signal φS2 as the lower bit. That is, the slot signal φS4. φS2
When the value is "10", the value of the latch 67 is output, and when it is "01", the values of the counters φ5 to φ1 are output, respectively.

Also, when it is "00", the voice number VN (for each channel) transferred from the channel register is taken as the upper 3 bits, the bit obtained by inverting the slot counter φ2 by the inverter 69 is taken as the data of the second pitch from the lower, and the slot counter Outputs 5-bit data with the bit of φ1 as the least significant bit. The reason why the value of the slot counter is converted by the inverter 69 is to compensate for the delay of two time slots when the voice number is output as viewed from the channel counter. The state of this delay is shown in the read timing chart of FIG.

The counter uses φ5 to φ3 (upper 3 bits) as a refresh counter, φ2. φ1 (lower 2 bits) is used as a slot counter. This is because the refresh counter requires refreshing because dynamic RAM is used as the registers 70, 72, and 74.

Note that the data stored in the register is not limited to the parameters of the FM sound source. It can also be applied to sound source parameters such as PCM and harmonic synthesis, or parameters for reverberation effect circuits.

In addition, in the above embodiment, the register is a dynamic RAM.
is used, but static RAM may also be used.

Further, in the above embodiment, the number of channels is 16 and the number of voices is 8, but the number and combination of the number of channels and the number of voices are not limited to these.

[Effects of the Invention] As explained above, according to the present invention, since a RAM is used as a register in the sound source, data can be written to any channel, and the writing speed can be increased. It is also possible to perform a read operation using a channel counter and a write operation by specifying a channel in a time-sharing manner.

Furthermore, since the RAMs are arranged in parallel and read and used alternately, parameters can be read out at a sufficient speed even if a RAM whose speed is somewhat lower than that of a shift register or the like is used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electronic keyboard instrument to which a musical tone generator according to an embodiment of the present invention is applied. FIG. 2 is a detailed block diagram of a channel register section of the electronic musical instrument of this embodiment. Figure 3 is a detailed block circuit diagram of the differential circuit of this electronic musical instrument, Figure 4 is a timing chart at the rise and fall of the WR signal, and Figure 5 shows the configuration of the voice register section. The block circuit diagram shown in FIG. 6 is a timing chart of the clock tg, etc. 1: Sound source, 2: Keyboard, 3.6, 11: Interface, 4: Microcomputer, 5: Operator, 12.13: Latch, 14: Differential circuit, 15: Clock generator, 16: Channel register section, 17: voice register section; 18; musical tone generating block (musical tone forming means);

Claims (2)

[Claims] (1) Random access storage means capable of storing parameters characterizing musical tones to be generated at arbitrary address locations; Writing means for writing parameters into the random access storage means; and Write means for writing parameters from the random access storage means. 1. A musical tone generating device comprising: reading means for sequentially reading data. (2) A first parameter storage means and a second parameter storage means for storing parameters characterizing the musical tone to be generated, and a parameter storage means for the first parameter storage means and second parameter storage means at the same address. A means for instructing data writing and reading, and a signal that rapidly switches between "0" and "1" is input, and as the signal is switched, parameter data of the first parameter storage means is output. and output means for switching the output of the parameter data of the second parameter storage means, and musical tone forming means for inputting the parameters outputted from the output means and forming a musical tone based on the designation of the parameters. Characteristic musical tone generator.