JPH073439Y2 - Automatic rhythm playing device - Google Patents

Description

[Detailed description of the device]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic rhythm playing device, and more particularly to an automatic rhythm playing device capable of arbitrarily moving a sound image position of a generated sound. [Prior Art] An automatic rhythm playing device that generates a plurality of percussive sound sources in synchronization with a predetermined rhythm pattern is incorporated in, for example, an electronic organ, or is used in combination with various musical instruments. It contributes to the improvement of the performance effect. [Problems to be solved by the invention] By the way, in the conventional automatic rhythm playing device, since the sound image of the generated musical sound is fixed, there is no spatial spread of the generated sound. There was a shortcoming that it was scarce. The present invention has been made in view of the above-mentioned circumstances, and can control the sound image position and the overall sound volume in synchronization with the rhythm pattern to obtain the spatial spread of the generated musical sound and improve the dynamic feeling of the rhythm. An object is to provide an automatic rhythm playing device. [Means for Solving the Problems] In order to solve the above problems, the present invention provides a rhythm signal generating means for generating a predetermined rhythm signal in accordance with a stored rhythm pattern, and a plurality of types of rhythm tone waveforms with the predetermined rhythm tone waveform. Musical tone waveform generating means for generating in accordance with a rhythm signal, a plurality of spatially discrete musical tone generating portions for generating a rhythmic musical tone corresponding to the rhythmic musical tone waveform, and a sound image position and volume for each of the rhythmic musical tone waveforms. Control data storage means for storing control data to be designated, and control for reading the control data and individually controlling each volume in each of the musical tone generating units and uniformly increasing or decreasing based on the control data. And a sound volume control means for controlling the sound image position and the sound volume for each rhythm tone. [Operation] According to the above configuration, the volume of each tone generation section is controlled individually or uniformly based on the control data corresponding to the tone. Therefore, it is possible to appropriately change the sound image position and the overall volume, and the spatial expansion of the sound and the dynamic expression can be obtained. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

[Configuration of Example]

FIG. 1 is a block diagram showing the construction of an embodiment of the present invention. In the embodiment shown in this figure, plural kinds of percussive musical tone data are stored in advance, and the musical tone data are read out as appropriate to generate a rhythm sound by a plurality of musical instrument sounds. The speakers 1L and 1R provided are appropriately and selectively supplied to one or both of them to move the sound image of the specific musical instrument sound to the left or right, or to add an accent. Further, the formation of each musical instrument sound in the embodiment is performed by the channel signal CH of a constant cycle.
By performing time-division processing within one cycle (described later), each musical instrument sound formed within the same cycle is sounded at the same time. Now, in FIG. 1, the channel counter 2 is an octal up counter that counts the clock pulse φ ₁ , and its count outputs “0” to “7” are channel signals.
It is output as CH to each part of the circuit. In this case, the timing of forming various musical instrument sounds (including the position of the sound image and the accent) is assigned to each of the channel signals CH “0” to “7”, for example, 0: bass drum (strong) 1: Bass drum (weak) 2: Clap hand (clapping sound) central sound image 3: Clap hand left sound image 4: Clap hand right sound image 5: Cowbell 6: Snare drum 7: Hi-hat cymbal. The above-mentioned allocation can be changed appropriately by the configuration described later. Next, waveform memory RAM (random access memory) 3
Is, for example, as shown in FIG. 2, eight storage blocks 3a ...
It is a RAM having 3h, and eight kinds of tone waveforms are stored in advance in each memory block. In this case, the musical tone waveforms stored in the storage blocks 3a to 3h are waveforms from the rising of each waveform to the attenuation and muffling, and this waveform data is the start address of each storage block (hereinafter referred to as start address STAD It is remembered sequentially). Waveform ROM (read only memory) 4 is waveform RAM3
Is a memory that supplies waveform data to the waveform RA
Each waveform data in M3 is the same as the data in this waveform ROM4. Further, the waveform ROM 4 is configured to be exchangeable, and if the waveform ROM 4 is exchanged with a different content, the content of the waveform RAM 3 will be different. In this case, data transfer from the waveform ROM 4 to the waveform RAM 3 is performed by the read / write control circuit 5, and in the figure, S ₁ is a read / write control signal and RWAd is address data. Next, the address RAM 6 has an end address table 7, a start address table 8 and a control data table 9
Made of. In this case, the end address table 7
Is a table in which the relative end addresses ENADa 'to ENADh' of the eight kinds of tone waveforms stored in the waveform RAM3 are stored. Where the relative end address ENADa ′
~ ENADh ′ is the actual end address ENA of each tone waveform
Start address S from Da to ENADh (see Fig. 2)
It is a value obtained by subtracting TADa to STADh. Then, the end address table 7 outputs the relative end addresses ENADa 'to ENADh' of the tone waveform specified by the channel signal CH to the input terminal A of the comparison circuit 11. In this case, when the channel signal CH is "0" or "1", the relative end address ENADa 'of the bass drum is selected, and "2", "3",
When it is "4", the relative end address ENAD of the clap hand
When b'is selected and "5" to "7", cowbell,
Relative end addresses ENADc 'to ENADe' of the snare drum and hi-hat cymbal are selected. The start address table 8 is a table in which the start addresses STADa to STADh of the tone waveforms in the waveform RAM 3 are stored, and the start addresses STADa to STADh of the tone waveforms specified by the channel signal CH are input to the adder circuit 12. Output to A. In this case, as in the case of the end address table 7 described above, the start address STADa is selected when the channel signal CH is "0" or "1", and when the channel signal CH is "2", "3", or "4". Start address ST
When ADb is selected and when it is "5" to "7", start addresses STADc to STADe are selected. This is because the waveform data is determined only by the type of musical sound (type of musical instrument),
This is because the sound image position and accent of the musical sound are not related to the waveform data. As shown in FIG. 3, the control data table 9 is composed of 1-byte storage areas 9a to 9h selected by the channel signals CH "0" to "7", respectively.
Control data of 2 bits is stored in each of the 0th and 1st bits of 9h to 9h. When this control data "D ₁ D ₀ " is "11", the sound image position is in the center, when it is "01" and "10", the sound image position is left and right respectively, and when it is "00". Is controlled so that the position of the sound image is in the center and has a strong beat.
Then, these bit outputs D ₀ and D ₁ are output as signals Q ₁ and Q ₂ , respectively. Next, the address ROM 14 goes to each of the tables 7 to 9 described above,
It is a memory for supplying address data and control data, and stores a plurality of sets of combinations of address data and control data supplied to each of the tables 7-9. And
Any one of the combinations of data is selected by the output signal of the rhythm selection switch 15, and the data of the selected set is controlled by the read / write control circuit 5 in each of the tables 7 to 7 in the address RAM 6. 9 is transferred. The change detection circuit 16 is a circuit for detecting whether or not the output signal of the rhythm selection switch 15 has changed. When the change detection circuit 16 outputs the change detection signal, the read / write control circuit 5 is newly selected. Data set in address ROM is converted to address RAM
It transfers to each table 7-9 in 6. In this way, if you change the rhythm with the rhythm selection switch 15, the address
The contents of RAM6 change, and as a result, the selected musical sound data (see FIG. 2) also differs. That is, the musical sound assigned to each of the channel signals CH “0” to “7” is changed. The address ROM 14 is configured to be convertible, and by exchanging it with an address ROM of different contents,
The degree of freedom in assigning musical tones to the channel signals CH “0” to “7” can be greatly expanded. The rhythm pattern generation circuit 18 is a circuit that generates eight types of rhythm pulses corresponding to each rhythm, and the pattern of each rhythm pulse (rhythm pattern) is a rhythm selection switch.
It is determined by the type of rhythm selected by 15 (for example, disco, rock, swing, etc.), and on / off of the start switch 19 controls the generation / stop of each rhythm pulse. Then, each generated rhythm pulse is time-divisionally output according to the channel signal CH. That is, when the channel signal CH is "0", the rhythm pulse of the bass drum (strong) is "1", the rhythm pulse of the bass drum (weak) is ... Each rhythm pulse is output. Next, the address data generating circuit 20 has the configuration shown in FIG. In the figure, 21 is an adder circuit, 22 is a terminal DIS
When a "0" signal is supplied to, it becomes an opening, and when a "1" signal is supplied, it closes (gates whose output ends are all "0" signals, 23
Is a multi-bit (for example, about 15 bits) 8-stage shift register, 24 is a 1-bit 8-stage shift register, 25 to 27 are OR gates, and 28 is an AND gate. The shift registers 23 and 24 described above have clock signal φ ₁ respectively.
The signal supplied to the input terminal is sequentially shifted in synchronism with. The output signal of the shift register 23 is supplied to the input terminal B of the adder circuit 12 as address data ADD. The comparison circuit 11 uses the relative end addresses ENADa ′ to ENADh ′,
The address data ADD is compared, and when they match, a match signal EQ (“1” signal) is output to the terminal of the address data generation circuit 20.
Output to T ₃ . The adder circuit 12 adds the address data ADD and the data of the start addresses STADa to STADh, and outputs the addition result to the address terminal of the waveform RAM 3 as the address data AD. Next, when the "0" signal is supplied to the terminal EN, the shifter 30 shown in FIG. 1 outputs the output signal of the waveform RAM3 as it is to the accumulator 31,
When the signal is output to 32 and a “1” signal is supplied to terminal EN, waveform RA
Accumulators 31, 32 by lowering the output signal of M3 by one digit (one digit in binary)
Is a circuit for outputting to. Therefore, when the output of the AND gate 33 becomes "1", the output signal of the waveform RAM3 becomes the shifter 30.
When passing through, the value becomes 1/2. The accumulators 31 and 32 sequentially accumulate the output of the shifter 30 while the channel signal CH is "0" to "7", latch the accumulated result, and perform digital-analog conversion on the latched data. Vessel (hereinafter DAC
It outputs to 35, 36 and clears the accumulated result. Then, the accumulators 31 and 32 repeat the above operation.
However, when the “0” signal is supplied to the terminal EN, the accumulators 31 and 32 do not take in the output of the shifter 30 while the “0” signal is supplied. And the accumulator 31,
Both or one of the two 32 is selected by a selection circuit 38 consisting of two OR gates and one NOR gate. As a result, the output of the shifter 30 is output from the accumulator 3
It is supplied to both 1, 32, or only one of them.

[Operation of the embodiment]

Next, the operation of this embodiment having the above configuration will be described. When the power is turned on, the clock pulses phi ₁ is supplied to the individual circuit components, initial clear circuit initial clear signal having a long pulse width from (not shown) from 16 periods of the clock pulse φ ₁ ( _"1" Signal) is output. When the initial clear signal IC is output, the output signal of the OR gate 27 shown in FIG. 4 becomes "1" and all the stages of the shift register 24 become "1". When all the stages of the shift register 24 become "1", the OR gate 25 outputs the "1" signal and the gate 22
Is closed and all stages of the shift register 23 are cleared. On the other hand, assuming that the start switch 19 (Fig. 1) is off, the output signal of the rhythm pattern generation circuit 18 is "0".
Therefore, the "1" signal is output from the inverter 43 and supplied to the terminal T ₅ of the address data generation circuit 20 via the OR gate 42. As a result, a loop of shift register 24 → OR gate 26 → AND gate 28 → OR gate 27 holds “1” of each stage in the shift register 24 and keeps the gate 22 in the closed state. According to the above-described operation, the data “0” is always supplied to the input terminal B of the adder circuit 12, and as a result, the address data output from the adder circuit 12 is the channel signal CH “0” to
Start address STAD that is selected appropriately by CH "7"
Repeat a to STADe. In this case, since only the start address is accessed in the waveform RAM3 and a series of musical tone waveform data is not read out, no musical tone is formed. Next, when the operator turns on the start switch 19, the rhythm pattern generation circuit 18 generates a rhythm pulse, and the rhythm pulse corresponding to each musical sound is generated by the channel signal CH.
Are sequentially output in a time-division manner. FIG. 5 is a diagram showing a correspondence relationship between the generation timing of the clock signal φ ₁ and the channel signal CH, in which the channel signal CH “0” (as described above, the channel assigned to the bass drum (strong)). ) Will be explained. Now, between time t00 and t01, the rhythm pattern generation circuit
The output signal of 18 becomes "1", and after that time t00-t11,
It is assumed that the output signal of the rhythm pattern generation circuit 18 becomes "0" at t20-t21, t30-t31, tK10-tK11 .... In this case, a "0" signal is supplied to the terminal T ₅ (Fig. 4) at time t00-t01, and as a result, the signal read into the stage corresponding to the channel signal "0" of the shift register 24 at time t01 is " It becomes 0 ". Then, the read "0" signal has the next channel signal CH of "0".
At time t10-11, the shift register 24 outputs to the terminal DIS of the gate 22 via the OR gate 25.
As a result, the gate 22 is opened and the output signal of the adder circuit 21 is output to the shift register 23. At this time, as described above, the address data ADD “0” is output from the shift register 23.
Therefore, the output of the adder 21 is a signal obtained by adding "1" to the least significant bit of the address data ADD, that is, a signal "1" (decimal). Then, this signal "1" is read into the shift register 23 at time t11, and then the time t20-t21 at which the channel signal becomes "0".
At, the shift register 23 outputs the address data ADD. At this time, at the input terminal A of the adder circuit 12,
Since the start address TADa selected by the channel signal CH “0” is supplied, the address data AD output from the adder circuit 12 becomes AD = STADa + 1 (1), and the memory block 3a shown in FIG. Start address ST
The next address of ADa is accessed. Then, the data within the same address is supplied to the shifter 30. On the other hand, in the control data table 9 shown in FIG. 1, the area 9a is selected by the channel signal CH “0”, and as a result, the signals Q ₁ and Q ₂ shown in the same figure are both “0”. . This signal Q ₁ , Q ₂
When both are “0”, the terminal EN of the shifter 30 is supplied with the “0” signal, and the terminals EN of the accumulators 31 and 32 are both supplied with the “1” signal. As a result, the data in the head address of the bass drum waveform output from the waveform RAM 3 passes through the shifter 30 as it is and is supplied to both the accumulators 31 and 32. Then, thereafter, in the same manner as described above, the address for accessing the storage block 3a is incremented each time the channel signal CH becomes "0", and as a result, the waveform data of the bass drum is sequentially accumulated 31, It is supplied to both of 32, and each of the accumulators 31 and 32 sequentially accumulates the accumulated data every time one cycle of the channel signal CH is completed.
Supply to 6. This allows the left and right speakers 1
The bass drum sound is output from L and 1R. And
Relative end address ENAD selected by the output signal of the adder circuit 12 in which “1” is added to the address data ADD which is sequentially incremented, and the channel signal CH “0”
When the comparison circuit 11 detects a match with a ′, the comparison circuit 11 outputs a match signal EQ (“1” signal).
This signal EQ is supplied to the terminal DIS of the gate 22 via the terminal T ₃ and the OR gate 25 shown in FIG. As a result, the gate 22 is closed and the "0" signal is output to the shift register 23.
Is output to. Then, the channel signal CH is "0" next.
At the time, the address data ADD output from the shift register 23 becomes "0" again. Then, when the coincidence signal EQ is output, the "1" signal is written in the table corresponding to the channel signal "0" of the shift register 24.
Since the output signal of 18 maintains “0”, the “1” signal with this table is circulated and held by the loop of shift register 24 → OR gate 26 → AND gate 28 → OR gate 27,
As a result, the address data ADD maintains "0". Therefore, the address data ADD remains "0" until the output signal of the rhythm pattern generating circuit 18 becomes "1" again. Further, as is apparent from the above description, the data read operation from the storage block 3a ends just before the end address. As described above, the musical tone is formed in the channel signal CH "0". And other channel signal CH
Even in "1" to "7", the tone formation similar to that described above is performed, but other channel signals CH "1" to
In "7", the control data is different as shown in FIG. 3, and therefore, the position and volume of the sound image emitted from the speakers 1L and 1R are different. This point will be described below. First, when the channel signal CH is "1", the control data "D ₁ D ₀ " is "11", and as a result, the signal shown in FIG.
Both Q ₂ and Q ₁ are “1” signals. Signals Q ₁ and Q ₂ are both “1”
When it becomes a signal, the "1" signal is supplied to the terminal EN of the shifter 30, and the data read from the waveform RAM3 is
When passing through the shifter 30, its value is halved. When the signals Q ₁ and Q ₂ are both “1” signals, the “1” signal is supplied to both terminals EN of the accumulators 31 and 32. As a result, the output signal of the shifter 30 is the accumulator 31. , 32 supplied to both. In this case, the channel signal CH “1” is assigned to the bass drum (weak) as described above, and the waveform data to be read is stored in the storage block as in the case of the channel signal “0”.
It is waveform data of the bass drum in 3a (Fig. 2). Therefore, the sounds of the bass drum are output from the speakers 1L and 1R. However, this channel signal "1"
In the case of, the value of the waveform data is halved due to the digit lowering operation of the shifter 30, and as a result, the channel signal "0"
The volume is half that of the case. Here, FIG. 6 is a musical score showing a discorhythm pattern in this embodiment, and the bass drum part is shown between the first and the first stages of the musical score. Further, in this embodiment, in the channel signal CH "0" at the timing corresponding to the note to which the accent signal is added, the output of the rhythm pattern generating circuit becomes "1", and the accent symbol is not added. Channel signal CH of the timing corresponding to the note
At "1", the output of the rhythm pattern generating circuit 18 is set to "1". Therefore, as indicated by the same musical note, the bass drum sound is alternately output as strong, weak, strong, and weak, so that the bass drum part having an extremely high sense of presence can be played. Next, when the channel signals are "2", "3", and "4", the control data "D ₁ , D ₀ " are "11", "10", and "01", respectively, as shown in FIG. In each case, the waveform data to be selected is stored in the storage block 3b (second
(Fig.) Is the waveform of the clap hand. When the control data “D ₁ , D ₀ ” is “1, 1”, the data read from the waveform RAM 3 has a value of 1/1 by the shifter 30 as in the case of the channel signal CH “1” described above. It becomes 2 and is then supplied to both accumulators 31 and 32. Therefore, in the case of the channel signal CH "2", the clapping sound is emitted from both the speakers 1L and 1R (however, it is not a strong beat), and the position of the sound image is at the center. On the other hand, when the channel signal CH is "3", the control data "D ₁ , D ₀ " is "1, 0", so the signals Q ₂ , Q ₁ are "1", "0", respectively. As a result, "0" is input to the terminal EN of the shifter 33.
A signal is supplied and a “0” signal is supplied to the terminal EN of the accumulator 32 and a “1” signal is supplied to the terminal EN of the accumulator 31. As a result, in the case of the channel signal CH "3", the data read from the waveform RAM3 passes through the shifter 30 as it is,
It is supplied only to the accumulator 31. Therefore, in the case of the channel signal CH "3", the clapping sound is emitted only from the left speaker 1L. When the channel signal CH is "4", the control data "D ₁ , D ₀ " is "0, 1", so the signals Q ₂ , Q ₁ are "0", "1", respectively. As a result, contrary to the above case, a clap sound is emitted only from the right speaker 1R. Considering the volume of the clapping sound in the channel signals CH “2” to “4”, the clapping sound is emitted from both the left and right speakers 1L and 1R in the case of the channel signal “2”. Since the volume in the speaker is attenuated to 1/2, the total volume is the channel signal "3",
It is equal to the case of "4". As described above, the volume of the clapping sounds generated in the channel signals "2" to "4" are all the same, but the volume positions are different, such as the center, the left side, and the right side. By the way, the third level of the score shown in FIG. 6 shows the part of the clap hand, and the first to third notes (each quarter note) have the sound image position designated as the center, Fourth
The sound image positions of the eighth and fifth notes (both eighth notes) are designated as the left side and the right side, respectively (note that no accent mark is attached to these notes). And
In the case of such a performance part, the output of the rhythm pattern generation circuit 18 is set to "1" in the channel signal CH "2" of the timing corresponding to the first to third notes, and the fourth, The output of the rhythm pattern generating circuit 18 may be set to "1" in the channel signals CHA "3" and "4" of the timings corresponding to the respective fifth notes. In this way, the musical sound as shown in the third row of FIG. 6 is produced. That is, the clap sounds corresponding to the first to third notes are emitted from the center of the speakers 1L and 1R, and then the fifth and sixth notes are emitted in the order of the left speaker 1L and the right speaker 1R. To be In this way, the sound image of the clapping sound shifts from the center to the left and then from the left to the right in synchronization with a predetermined rhythm, so that the listener can feel the unprecedented rhythmic movement. Next, when the channel signal CH is “5” to “7”, the control data “D ₁ , D ₀ ” are both “1, 1”.
Both Q ₂ and Q ₁ become “1” signals, and as a result, the speaker 1L,
From 1R, cowbell sound, snare drum sound of 1/2 volume each,
The hi-hat cymbal sound is output. The score in the second row of FIG. 6 shows the part of the cowbell sound in the above-mentioned discorism. Therefore, when playing this part, the channel signal CH “5” at the timing corresponding to the note shown in the figure. In the rhythm pattern generation circuit
The output of 18 should be "1". Also, SD and HH in the score of the first row of FIG. 6 are snare drum sounds,
It shows the part of the hi-hat sound, and in this case also the channel signal CH “6” of the timing corresponding to each note,
At "7", the output of the rhythm pattern generating circuit 18 may be "1". Note that HHC and HHO in the first musical note indicate the parts of the sound when the hi-hat cymbals are closed and when they are opened. In this way, when there are many types of sounds, the number of channels of the timing signal , And the above-mentioned sound may be assigned to this added channel. Further, in this embodiment, since the shifter 30 is provided and the waveform data is appropriately lowered by one digit by the shifter 30, it is possible to control the presence / absence of accent for a desired note. Further, the above-described embodiment is an example in which the invention is applied to the time-division sounding type automatic rhythm playing device, but the invention can of course be applied to the parallel sounding type automatic rhythm playing device. . Also in this case, similarly to the above-described embodiment, the data designating the position and the accent of the sound image may be read out in synchronization with the rhythm pulse of each musical sound, and the sounding position and the volume may be controlled accordingly. Further, in the above-mentioned embodiment, for simplification of description, the positions of the sound images to be selected are three positions of left, center and right (the volume ratios of the speakers 1L, 1R are 1: 0, 1: 1, respectively). , 0: 1) has been shown, but the position of the sound image is not limited to this, and an arbitrary position between the left and right can be selected. That is,
Increase the number of bits of control data to control the position of the sound image,
A fine sound image position may be designated by this control data, and the volume ratio of the speakers 1L and 1R may be controlled so that the designated sound image position is obtained. Further, in the above embodiment,
Although there are two tone generation systems capable of controlling the volume, the number may be increased to control the volume position. [Advantages of the Invention] As described above, according to the present invention, the sound image position and volume of a desired sound source can be appropriately controlled according to a rhythm pattern. That is, the spatial spread of the generated sound is obtained by controlling the sound image position, and the dynamic feeling (strength expression) of the rhythm is obtained by controlling the overall volume.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a schematic diagram showing stored contents of a waveform RAM 3, FIG. 3 is a diagram showing control data in a control data table 9, and FIG. Is a block diagram showing a configuration example of the address data generating circuit 20, FIG. 5 is a timing chart showing a correspondence relationship between the clock φ ₁ and the channel signal CH in the same embodiment, and FIG. 6 is an example of a rhythm pattern in the same embodiment. It is the score shown. 1L, 1R ... Sound generator (speaker), 39, 40 ... Amplifier, 35, 36 ...
Digital-analog converter (above, 1L, 1R, 39,40,35,3
6 is a first and second musical tone generating section), 9 ... Control data table (control data memory), 31, 32 ... Accumulator, 38 ... Selection circuit (sound image position selection means).

Claims (1)

[Scope of utility model registration request] 1. A rhythm signal generating means for generating a predetermined rhythm signal according to a stored rhythm pattern, a musical sound waveform generating means for generating a plurality of types of rhythm musical sound waveforms according to the predetermined rhythm signal, and a rhythm musical sound waveform. A plurality of spatially discrete musical tone generators for generating corresponding rhythm musical tones; control data storage means for storing control data for designating a sound image position and a volume for each rhythm musical tone waveform; And a volume control means for individually controlling each volume in each of the musical tone generating sections and for uniformly increasing or decreasing the volume based on the control data, and the sound image position for each rhythm musical tone. And an automatic rhythm playing device characterized by controlling the volume.