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JPH03238829A - Manufacture of field effect transistor - Google Patents

Manufacture of field effect transistor

Info

Publication number
JPH03238829A
JPH03238829A JP3470290A JP3470290A JPH03238829A JP H03238829 A JPH03238829 A JP H03238829A JP 3470290 A JP3470290 A JP 3470290A JP 3470290 A JP3470290 A JP 3470290A JP H03238829 A JPH03238829 A JP H03238829A
Authority
JP
Japan
Prior art keywords
pad
layer
metal layer
electrode
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3470290A
Other languages
Japanese (ja)
Inventor
Yasunobu Saito
泰伸 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3470290A priority Critical patent/JPH03238829A/en
Publication of JPH03238829A publication Critical patent/JPH03238829A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To enable adhesion property between a pad an a semiconductor substrate to be improved and the pad without any increase in leak current to be formed by forming a pad to be connected to a source electrode, a drain electrode, and a gate electrode on a ground pad by performing heat treatment. CONSTITUTION:After forming a metal which makes an ohmic contact at an operation layer region on a semiconductor substrate 101, Ti is formed as a first metal layer 14 which becomes a Schottky junction as a ground pad and for example Pt is formed as a second metal layer 15 which becomes a barrier metal on it at a region which does not overlap the metal which makes an ohmic contact except the operation layer. Then, heat treatment is performed to enable an ohmic electrode (source/drain electrode) to be formed and at the same time the first metal layer 14 is allowed to strike through the semiconductor. After that, a pad 17 which is connected to an ohmic electrode and a Schottky electrode is formed on the second metal layer 15, thus enabling adhesion between the pad and the semiconductor substrate to be improved and a pad 17 without any increase in leak current to be formed.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は電界効果トランジスタの製造方法に係り、特に
電界効果トランジスタのパッドの形成方法に改良を施し
た電界効果トランジスタの製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor in which a method for forming pads of a field effect transistor is improved. Regarding the method.

(従来の技術) 近年超高周波帯で使用する半導体装置としてショットキ
ー型電界効果トランジスタが提案され、実用段階に至っ
ている。代表的なショットキー型GaAs電界効果トラ
ンジスタについて断面図で示す第3図および第4図を参
照して説明する。
(Prior Art) In recent years, a Schottky field effect transistor has been proposed as a semiconductor device used in an ultra-high frequency band, and has reached the practical stage. A typical Schottky type GaAs field effect transistor will be described with reference to FIGS. 3 and 4, which are cross-sectional views.

GaAs半絶縁性基板(以下基板と略称する)1o1の
上面にイオン注入法、またはエピタキシャル成長法によ
り選択的に形成した動作層領域102にソース電極、ド
レイン電極のためのオーミックメタル103を形成後、
熱処理によりオーミック電極(ソース、ドレイン電極)
を形成し、ゲート電極106を形成後、ゲート電極、ソ
ース電極、ドレイン電極から基板101上にボンディン
グワイヤとの接続が容易になるように例えばTi、 P
t、Auよりなるパッド107が形成されている。
After forming an ohmic metal 103 for a source electrode and a drain electrode in an active layer region 102 selectively formed on the upper surface of a GaAs semi-insulating substrate (hereinafter referred to as substrate) 1o1 by ion implantation or epitaxial growth,
Ohmic electrodes (source, drain electrodes) are formed by heat treatment.
After forming the gate electrode 106, for example, Ti, P is deposited on the substrate 101 from the gate electrode, source electrode, and drain electrode to facilitate connection with bonding wires.
A pad 107 made of Au is formed.

上記構造のGaAs電界効果トランジスタには次項に述
べるような問題点がある。
The GaAs field effect transistor having the above structure has the following problems.

次に、一般に行われている別の方法として、オーミック
電極を形成するためのオーミックメタルをパッドの下に
も形成し、基板と合金化することにより密着性を向上さ
せ、その上にパッドを形成することで半導体基板とパッ
ドとの密着性を上げる方法がある。その製造方法例を以
下に図面を参照して説明する。
Next, another commonly used method is to form an ohmic metal under the pad to form an ohmic electrode, improve adhesion by alloying it with the substrate, and then form a pad on top of it. There is a method of increasing the adhesion between the semiconductor substrate and the pad by doing so. An example of the manufacturing method will be described below with reference to the drawings.

第4図(a)に断面図で示すように基板101上の動作
層102上及びパッド形成領域にオーミックメタル11
3をリフトオフ法によりパターニングし、続いて熱処理
を施すことによりGaAs基板とオーミックメタル層と
の合金層を形成する。その後、第4図(b)に断面図で
示すようにゲート電極106を形成後、パッド107を
合金層上にリフトオフ法で形成する。これにより基板1
01とパッド層107どの密着性が向上する。
As shown in the cross-sectional view in FIG.
3 is patterned by a lift-off method, and then heat treated to form an alloy layer of the GaAs substrate and the ohmic metal layer. Thereafter, as shown in the cross-sectional view of FIG. 4(b), after forming a gate electrode 106, a pad 107 is formed on the alloy layer by a lift-off method. As a result, board 1
The adhesion between the pad layer 107 and the pad layer 107 is improved.

(発明が解決しようとする課題) 上記第3図によって説明した従来例の構造のGaAs電
界効果トランジスタは、半導体基板とパッドとの密着が
十分でないためパッド剥離を起こすことがあった。この
問題を解決するための一方法として、第3図に示される
構造でパッドを形成後シンターを施すことにより、パッ
ドメタルであるTiをGaAsに食い込ませて密着性を
向上させる方法がある。この方法で、十分な密着性を得
るためには400℃以上のシンターが望ましい。しかし
ながら、このシンターによりオーミックメタルとパッド
メタルが相互に拡散してオーミック特性が劣化する事が
あること、またゲート電極形成後に高温のシンターを行
うためにFET特性(飽和電流等)が変動する事もある
、などトランジスタ自身の特性に影響を与えるため、一
般には行われていない。
(Problems to be Solved by the Invention) In the GaAs field effect transistor having the conventional structure explained with reference to FIG. 3 above, pad separation may occur due to insufficient adhesion between the semiconductor substrate and the pad. One method for solving this problem is to improve adhesion by forming a pad in the structure shown in FIG. 3 and then sintering it so that Ti, which is the pad metal, bites into GaAs. In order to obtain sufficient adhesion with this method, sintering at 400° C. or higher is desirable. However, due to this sintering, the ohmic metal and pad metal may diffuse into each other, resulting in deterioration of the ohmic characteristics.FET characteristics (saturation current, etc.) may also fluctuate due to the high temperature sintering performed after forming the gate electrode. Generally, this is not done because it affects the characteristics of the transistor itself.

上記第4図によって説明した従来例の構造の電界効果ト
ランジスタではパッドと半導体基板の密着性を向上させ
るためのパッド下のオーミックメタル層103が熱処理
によりオーミック接触性をしめずため動作層以外の半導
体基板の結縁性が十分でないとパッド間のリーク電流が
増加するという問題があった。
In the field effect transistor having the conventional structure explained with reference to FIG. There is a problem in that if the bonding properties of the substrate are not sufficient, leakage current between pads increases.

この発明の目的は上記従来の問題に鑑みてなされたもの
で、オーミック特性、ショットキー特性に影響を与える
ことなく、半導体基板とパッドの密着性を向上させた電
極剥離が起こりにくい、しかもリーク電流が増加しない
信頼性の高いパッドをもった電界効果トランジスタの製
造方法を提供するにある。
The purpose of this invention was made in view of the above-mentioned conventional problems.The purpose of this invention is to improve the adhesion between the semiconductor substrate and the pad without affecting the ohmic characteristics and the Schottky characteristics, to prevent electrode peeling from occurring, and to reduce leakage current. An object of the present invention is to provide a method for manufacturing a field effect transistor having a highly reliable pad that does not increase the number of pads.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明にかかる電界効果トランジスタの製造方法は、半
導体基板上にパッド電極を形成するに当たり、半導体基
板上の動作層領域にオーミック接触となるようなメタル
を形成の後、動作層以外のオーミック接触となるような
メタルに重ならない領域に下地パッドとしてショットキ
ー接合となる第一のメタル層として例えばTi、その上
にバリアメタルとなる第二のメタル層として例えばpt
を形成し、その後熱処理を施すことによりオーミック電
極(ソース・ドレイン電極)を形成すると同時に第一の
メタル層を半導体に食い込ませ半導体基板との密着性を
向上させ、しかるのちにオーミック電極及びショットキ
ー電極に接続するパッドを第二のメタル層上に形成する
ことを特徴とする。
(Means for Solving the Problems) A method for manufacturing a field effect transistor according to the present invention includes forming a metal that makes ohmic contact with an active layer region on a semiconductor substrate when forming a pad electrode on a semiconductor substrate. After that, in a region other than the active layer that does not overlap with the metal that will make ohmic contact, a first metal layer of, for example, Ti, which will become a Schottky junction as a base pad, and a second metal layer, such as PT, which will become a barrier metal, will be formed on top of it.
is formed, and then heat-treated to form ohmic electrodes (source/drain electrodes). At the same time, the first metal layer digs into the semiconductor to improve adhesion with the semiconductor substrate, and then ohmic electrodes and Schottky electrodes are formed. The method is characterized in that a pad connected to the electrode is formed on the second metal layer.

(作 用) 本発明にかかるFETの製造方法によりショットキー特
性、オーミック特性に影響を与えることなくパッドと半
導体基板との密着を向上させるとともにリーク電流の増
大のないパッドが形成される。
(Function) The FET manufacturing method according to the present invention improves the adhesion between the pad and the semiconductor substrate without affecting the Schottky characteristics and ohmic characteristics, and forms a pad that does not increase leakage current.

(実施例) 以下、この発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第1図(a)、 (b)は一実施例の製造方法を工程順
に示すいずれも断面図で、各回において従来と変わらな
い部分には従来と同じ符号を付けて示し、説明を省略す
る。また、第2図に実施例にかかるMESFETの要部
を上面で示し、上記第1図はこの第2図中のA−A線に
沿う断面につき表すものである。
FIGS. 1(a) and 1(b) are cross-sectional views showing the manufacturing method of one embodiment in the order of steps, and in each step, the same parts as in the conventional method are denoted by the same reference numerals as in the conventional method, and the explanation thereof will be omitted. Further, FIG. 2 shows the main parts of the MESFET according to the embodiment from the top, and FIG. 1 shows a cross section taken along the line A--A in FIG.

まず、基板101上に例えばイオン注入法により選択的
に形成した動作層領域102上に写真蝕刻法によりオー
ム性電極(ソース・ドレイン電極)用のレジストパター
ニングを行い、オーミックメタルとして例えばAuGe
 : Ni層を蒸着したのちリフトオフを施しオーミッ
クメタル層13をパターニングする。続いて動作層領域
以外のオーミックメタル層に重ならない領域に写真蝕刻
法により下地パッドのレジストパターニングを行い、第
一のメタル層14として、例えばTi層を500Aの層
厚に、続いて第二のメタル層15として、例えばpt層
を500Åの層厚に夫々蒸着し、続いてリフトオフ法に
より下地パッドを形成する。次いで、450℃の熱処理
を施し、動作層領域にオーム性電極(ソース・ドレイン
電極)を形成する。このとき下地パッドの第一のメタル
層14はオーミック接触になることなく GaAs基板
1に食い込むためにリーク電流が増加することなく密着
性が増す。また、この時オーミックメタル層13と第一
のメタル層14.第二のメタル層15とは離れているた
め、上記熱処理により相互に反応を起こしてオーミック
特性を劣化させる事はない(第1図(a))。
First, resist patterning for ohmic electrodes (source/drain electrodes) is performed by photolithography on the active layer region 102 selectively formed on the substrate 101 by, for example, ion implantation.
: After depositing the Ni layer, lift-off is performed to pattern the ohmic metal layer 13. Subsequently, resist patterning of a base pad is performed by photolithography in a region other than the active layer region that does not overlap with the ohmic metal layer, and as the first metal layer 14, for example, a Ti layer is formed to a layer thickness of 500A, and then a second layer is formed. As the metal layer 15, for example, a PT layer is deposited to a thickness of 500 Å, and then a base pad is formed by a lift-off method. Next, heat treatment is performed at 450° C. to form ohmic electrodes (source/drain electrodes) in the active layer region. At this time, the first metal layer 14 of the base pad digs into the GaAs substrate 1 without forming ohmic contact, so that the adhesion is increased without increasing leakage current. Also, at this time, the ohmic metal layer 13 and the first metal layer 14. Since it is separated from the second metal layer 15, the heat treatment will not cause a reaction with each other and deteriorate the ohmic characteristics (FIG. 1(a)).

次に、ゲートメタルを形成した後、写真蝕刻法によりソ
ース・ドレイン電極103及びゲート電極106に接続
するパッド用のレジストパターニングを下地パッドに重
なるように行ない、パッドとして、例えばTi層を層厚
tooo人に、 pt層を層厚1000人に、 Au層
を層厚8000 Aに順次蒸着を施し、つづいてリフト
オフを施しパッド17を形成する(第1図(b))。
Next, after forming the gate metal, resist patterning for pads connected to the source/drain electrode 103 and the gate electrode 106 is performed by photolithography so as to overlap with the base pad, and as a pad, for example, a Ti layer is formed with a layer thickness of too much. A PT layer with a thickness of 1,000 Å and an Au layer with a thickness of 8,000 Å are sequentially deposited on a substrate, followed by lift-off to form a pad 17 (FIG. 1(b)).

〔発明の効果〕〔Effect of the invention〕

以上述べたようにこの発明によれば、ショットキー特性
、オーミック特性に影響を与えることなくパッドと半導
体基板との密着性を向上させ、また、従来一般に行われ
ている方法の欠点であるリーク電流の増大もないパッド
を形成できる方法を提供できる。
As described above, according to the present invention, the adhesion between the pad and the semiconductor substrate can be improved without affecting the Schottky characteristics and ohmic characteristics. It is possible to provide a method for forming a pad without increasing the amount of water.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、 (b)はこの発明の実施例に係わるM
ESFETの製造工程を工程順に示すいずれも断面図、
第2図は実施例にかかるMESFETを説明するための
上面図、第3図は従来例のMESFETの断面図、第4
図(a)、(b)は従来例のMESFETの製造工程を
工程順に示すいずれも断面図である。 13・・・オーミックメタル層、 14・・・Ti層(第一のメタル層)、15・・・pt
層(第二のメタル層)、17・・・パッド、101・・
・半絶縁性GaAs基板、102・・・動作層領域、1
06・・・ショットキーゲート電極。 15:PtJ!
FIGS. 1(a) and 1(b) show M according to an embodiment of the present invention.
Cross-sectional views showing the manufacturing process of ESFET in order of process,
FIG. 2 is a top view for explaining the MESFET according to the embodiment, FIG. 3 is a sectional view of the MESFET of the conventional example, and FIG.
Figures (a) and (b) are both cross-sectional views showing the manufacturing process of a conventional MESFET in order of process. 13... Ohmic metal layer, 14... Ti layer (first metal layer), 15... pt
layer (second metal layer), 17... pad, 101...
- Semi-insulating GaAs substrate, 102...active layer region, 1
06... Schottky gate electrode. 15:PtJ!

Claims (1)

【特許請求の範囲】[Claims] 一導電形の動作層が選択的に形成された高抵抗半導体基
板の表面にソース電極、ドレイン電極およびゲート電極
を有する電界効果トランジスタの製造にあたり、前記動
作層上にオーミック接触となるメタル層を形成する工程
と、前記半導体基板上の動作層以外の領域に前記メタル
層に重ならないように下地パッドとしてショットキー接
合となる第一のメタル層とこれに積層させてバリアメタ
ルとなる第二のメタル層をそれぞれ所望の厚さ形成する
工程と、熱処理を施す工程と、前記下地パッド上にソー
ス電極、ドレイン電極及びゲート電極に接続するパッド
を形成する工程を含むことを特徴とする電界効果トラン
ジスタの製造方法。
In manufacturing a field effect transistor having a source electrode, a drain electrode, and a gate electrode on the surface of a high-resistance semiconductor substrate on which an active layer of one conductivity type is selectively formed, a metal layer is formed to form an ohmic contact on the active layer. a first metal layer that serves as a Schottky junction as a base pad and a second metal layer that is laminated thereon to serve as a barrier metal so as not to overlap the metal layer in a region other than the active layer on the semiconductor substrate; A field effect transistor comprising the steps of forming each layer to a desired thickness, performing heat treatment, and forming pads connected to a source electrode, a drain electrode, and a gate electrode on the base pad. Production method.
JP3470290A 1990-02-15 1990-02-15 Manufacture of field effect transistor Pending JPH03238829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3470290A JPH03238829A (en) 1990-02-15 1990-02-15 Manufacture of field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3470290A JPH03238829A (en) 1990-02-15 1990-02-15 Manufacture of field effect transistor

Publications (1)

Publication Number Publication Date
JPH03238829A true JPH03238829A (en) 1991-10-24

Family

ID=12421693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3470290A Pending JPH03238829A (en) 1990-02-15 1990-02-15 Manufacture of field effect transistor

Country Status (1)

Country Link
JP (1) JPH03238829A (en)

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