JPH03227120A - Counter circuit - Google Patents

Abstract

PURPOSE:To surely propagate an asynchronous clock signal and to ensure a carry to a succeeding counter section by providing a delay inversion circuit and setting its delay time longer than the propagation delay time of an n-ary counter and an n-detection circuit. CONSTITUTION:When the asynchronous clock signal 2 is inputted to a delay inversion circuit 10A in an n-ary counter section 20, an N-channel MOS transistor(TR) QA in the circuit 10A is turned on and a voltage VA at a node A goes to an L level. When the signal 2 returns to an L level, the TR QA is turned off and the voltage VA goes gradually to H. Then the pulse width of an inverse signal 7a of clock is made wider than that of the signal 2 and the rise of a carrying signal 5a generated in an RS latch 11 is slower by the propagation delay time of the n-ary counter 3 and an n-detection circuit 4. Moreover, the delay time at the falling side is slower by the delayed time by the circuit 10A. Thus, the pulse width of the signal 2 is not made narrower by setting the delay time of the circuit 10A more than the propagation delay time of the counter 3 and the circuit 4 and sure carrying is attained to the succeeding counter section.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a counter circuit.

[Conventional technology]

To achieve this, for example, in a sexagesimal counter circuit that is not a power of 2, multiple n-ary counters are connected in series, and a one-shot clock signal is generated from an asynchronous signal other than the original clock signal by the propagation delay time of the element. In addition to the original clock, an asynchronous clock signal is also counted up.

FIG. 4 is a circuit diagram of an example of a conventional counter circuit.

The counter circuit has an n-ary counter section 20b and an m-ary counter section 21b connected in cascade.

The n-ary counter section 20b receives the clock signal l and the non-inverted signal 7.
BS latch 1 inputs detection signal S0 of a and n detection circuit 4 and outputs carry signal 5a and reset signal 6a
1.

Next, the operation of the circuit will be explained. When the value of the n-ary counter 3 of the counter section 2ob is (n-1) and the asynchronous clock signal 2 is input, the count is increased by nK from (n-1), and the n-detection circuit 4 detects it. S latch 1
0: Generates a reset signal 6a for the tn-adic counter 3I and a carry signal 5a to the next stage. The mQ counter section 21b also has the same configuration except for the input OR circuit 01'L of the n-ary counter section 20b, and counts m.

Therefore, if the value of m-adic counter 8 is (m-1),
First, the counter 3 of the n-ary counter section 2ob operates as described above and generates a carry signal 5a, so that the m-ary counter 8 similarly detects m, and the BS ratte 11 receives a reset signal 6b.
and a carry signal 5btl- is generated and sent to the next stage.

Here, for example, in the case of counting seconds on a clock, n.

m is 10 and 6, which corresponds to 60 seconds.

However, when simply displaying 60 seconds, use the m-ary counter section 2.
The carry signal 5b of 1b becomes unnecessary.

In the case of minutes, 10 and a hexadecimal counter section are further connected to correspond to 60 minutes.

Even when a plurality of counter sections are connected in series in this way, the reset signal 6□ and the carry signal 5 to the next counter section are generated in the same way as the operation described above.

Clock signal 2 is also asynchronous with clock signal 1, so a signal is created from the original signal using the propagation delay time of the element, and the counter is counted up using the same path as clock signal 1, and then the next counter section It was outputting carry signal 5 to

[Problem to be solved by the invention]

In the conventional counter circuit described above, a carry signal from one counter to the next counter section is transmitted from the width of the clock signal input to the counter to R8 after completing the carry of the counter and passing through the n detection circuit. The signal width becomes narrower by subtracting the sum of the propagation delay times of the elements passed before being input to the latch.

In other words, when counting asynchronously in addition to the original clock signal, the count signal width is calculated by subtracting the sum of the propagation delay times of each counter during carry propagation from the width of the asynchronous clock signal input to the first counter section. It will be output from the final counter section.

Therefore, in order to safely carry up to the final counter section, it is necessary to make the initial asynchronous clock signal width sufficiently long.

However, since the asynchronous clock signal width is determined by the propagation delay time of the elements, the effective signal width fluctuates due to variations in manufacturing and characteristics of the elements, and this has the disadvantage that there is a possibility that the digit will not propagate reliably.

[Means to solve the problem]

The counter circuit of the present invention inputs a clock signal and an OR signal of a clock signal asynchronous to the clock signal, and inputs a plurality of bit signals of an n-ary counter and an s# n-ary counter that are reset by a reset signal. an inverter circuit that outputs an inverted signal in response to the asynchronous clock signal; an inverter circuit that receives the detected signal and the inverted signal; In a counter circuit including an n-ary counter section having a BS latch that outputs a carry signal and the reset signal, the inverter circuit is provided with a delay circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The counter circuit includes counter sections 2ob and 21b in FIG.
This counter circuit is the same as the conventional counter circuit except that delay inverting circuits 1oA and 10B are provided in place of the inverter.

Here, the delay inversion circuit 10A includes a P-channel MO8) transistor QA which inputs the asynchronous clock signal 2 to its gate, an inverter I which inputs its output node A voltage
It has a detailed circuit. The delay inversion circuit 10B receives the digit signal 5.
Transistor Q inputs voltage VB of node B output from transistor QB to buffer A.

have.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of the circuit of FIG. 1.

First, we will look at the operation when the clock signal 1 is input when the n-ary counter 3 of the n-ary counter section 20 has the value (n-1).

When the clock signal 1 is input, the n-ary counter 3 counts up and reaches the count value n in the same way as explained in the conventional example.
becomes.

This is detected by the n detection circuit 4, and the counter 3 is reset by the reset signal 6a from the BS latch 11, and a signal 5a is output when the carry is to the next counter.

Next, assume that an asynchronous clock signal 2 is input when the count value is (n-1).

When input, the n-ary counter 3 counts up and reaches the count value n, and the n-detection circuit 4 detects this.

At the same time, when the clock signal 2 input to the delay inverting circuit 10A becomes @H, the N-channel MOS transistor QA in the circuit is turned on, and the voltage of the node becomes "L".

When clock signal 2 returns to “L”, the N-channel MOS
The transistor QA is turned off, and the voltage at the node A gradually becomes 1H'' due to the pulled-up resistor.

Therefore, the inverted clock signal 7a falls at almost the same time t□ as the clock signal 2, but rises at a later time t2, and the pulse width of the signal 7a becomes wider than that of the clock signal 2.

Therefore, the carry signal 5 generated by the BS latch 11
The rising edge Dllll is delayed by the propagation delay time τ□ of the n7-adic counter 3 t''/detection circuit 4 than the rising edge of the count signal 2, but the falling edge is delayed by the reaction delay circuit 10A. It becomes even slower by τ2.

Therefore, the delay time τ2 of the delay inversion circuit 10A is calculated by the n-ary counter 3. If the propagation delay time τ1 of the n detection circuit 4 is also set larger, the pulse width τ of the asynchronous clock signal 2 will not become narrower even if there is a signal propagation delay during carry, and the Carry over to section 21 can be carried out reliably.

For example, in the case of a 60 second counter circuit, n is 10
, set m to 6.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The counter circuit is the delay inversion circuit 10A shown in FIG.

The fish body is the same as the first embodiment except that 10B is replaced with a delay inversion circuit 10cK, and the same operation is performed.

〔Effect of the invention〕

As explained above, the present invention provides a delay inversion circuit that widens the pulse @ of the inverted signal of the asynchronous clock signal input to the BS latch that generates the counter reset signal and carry to the next counter section. By adding this, it is possible to reliably propagate the asynchronous clock signal to the next cascade section in a nine-counter circuit connected in a cascade of multiple sections.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a circuit diagram of an example of a conventional counter circuit. DESCRIPTION OF SYMBOLS 1... Clock signal, 2... Asynchronous clock signal, 3... N-ary counter, 4... N detection circuit, 5a,
5b--Carry to next stage is signal, 6a, 6b--Counter reset circuit, 11/f3.8 latch, 20.20
a, 21.21a --- Counter section.

Claims (1)

[Claims] An n-ary counter that is reset by a reset signal by inputting a logical sum signal of a clock signal and a clock signal asynchronous to the clock signal, and a value that is not a power of 2 by inputting multiple bit signals of the n-ary counter. an n detection circuit that detects n and outputs a detection signal; an inverter circuit that outputs an inverted signal in response to the asynchronous clock signal; and an inverter circuit that inputs the detection signal and the inverted signal to generate a carry signal and the reset. 1. A counter circuit including an n-ary counter section having a BS latch for outputting a signal, characterized in that the inverter circuit is provided with a delay circuit.