JPH0435409A - Logical circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a difference between delay time to the output of a TRUE signal and delay time to the output of a BAR signal by providing the buffer of CMOS for an opposite phase output circuit. CONSTITUTION:When an input signal S1 is inputted to an input terminal T1, the TRUE signal ST is outputted through the invertors I1 and I2 of a TRUE signal output circuit 1 and the BAR signal SB is outputted through the buffer 3 and the invertor I3 of a BAR signal output circuit 2. The number of logical stages from the input terminal T1 to the output of the TRUE signal and that to the output of the BAR signal are set to be same two stages and signal delay time is set to be similar. Thus, there is no difference between the output of the TRUE signal and that of the output of the BAR signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to logic circuits, and in particular, to TR processing from one input signal.
The present invention relates to a logic circuit that outputs two signals, a UE signal and a BAR signal.

[Conventional technology]

Conventionally, the configuration of this type of logic circuit is an inverter of a CMOS transistor in which the common gate CG of p-channel and n-channel MOS transistors Q, , Q2 is used as an input terminal, and the common drain CD is used as an output terminal, as shown in FIG. BAR signal output circuit with I3 2. It has a TRUE signal output circuit 1 in which inverters I, I2 having the same circuit configuration are connected in series, and the same human input signal S is input to the input terminal I+.

Therefore, the TRUE signal S which is in phase with the input signal S1
In order to output T and anti-phase BAR signal signals S, TRU E signal output circuit 1 and BAR signal output circuit 2 are required.
．． The number of inverter stages with the same circuit configuration inside is one stage different.

[Problem to be solved by the invention]

The conventional logic circuit described above has a different number of logic stages for outputting the TRUE signal and the BAR signal due to its configuration. There is a drawback that there is a difference between the delay time until the E signal is output and the delay time until the BAR signal is output.

An object of the present invention is to provide a logic circuit in which there is no difference between the delay time until the output of the TRLtE signal and the delay time until the output of the BAR signal.

[Means to solve the problem]

The logic circuit of the present invention inputs a common input signal and has an even number of C
an in-phase output signal circuit that outputs an output signal that is in phase with the input signal via a MOS inverter; and an anti-phase signal output circuit that has at least one stage of the CMOS inverter and outputs a signal that is in the opposite phase of the input signal. In a logic circuit with
The negative phase output circuit includes a CMOS buffer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The logic circuit is the same as the conventional logic circuit except that it has been replaced with a BAR signal output circuit 2 in which a CMOS transistor buffer 3 is inserted in the front stage of the inverter 3 of the BAR signal output circuit 26 in Fig. 2. It is.

That is, in contrast to the inverter shown in FIG. 2, only the buffer 3 in FIG. 1 connects the source of the n-channel transistor QN to the drain power supply vDD and the source of the p-channel transistor Qp to GND.

Next, the operation will be explained.

When the input signal Sl enters the input terminal T+, the TRUE signal S is inputted to the inverter of the TRUE signal output circuit 1 via I2, and then the TRUE signal S is input to the BAR via the buffer 3 and inverter 4 of the AR signal output circuit 2. Signal signal S pressure is applied.

For example, when a "H" level signal is input to the input terminal IN, the inverter 1 of the TRUE signal 1 is connected to the transistor Q
, , are off, and transistor Q is on, outputting an "L" level.

Therefore, the TRUE signal S is inverted by the inverter 2 and becomes the same "H" level as the input signal S1.

On the other hand, when the input signal S1 is at the "H" level, the buffer 3 of the BAR signal output circuit 2 does not invert and outputs the "H" level because the transistor Qp is turned on and the transistor Q is turned off.

Since inverter r3 inverts the signal, BAR signal S6 becomes "L" level.

When the input signal S is at the "'L" level, the TRUE signal S and the BAR signal SB are at the "'H" level and the TRUE signal is at the "'H" level by the same operation.

In the circuit of this embodiment, as described above, from the input terminal T1 to the TRU
The number of logic stages up to the E signal output and the number of logic stages up to the BAR signal output are the same, two stages, and the respective signal delay times are made the same.

〔Effect of the invention〕

As explained above, in the present invention, the delay time of the TRUE signal output and the BA
This has the effect of eliminating the difference in R signal output delay time.

1... TRUE signal output circuit, 2... BAR signal output circuit, 3... Buffer, CD... Common drain,
CG...Common gate, 1. ~I3...CMOS inverter, Q,...n channel MO5) transistor, Q
p...p channel MOS transistor, SR...B
A4 signal, S+...input signal, ST...TRUE signal, T1...input end.

Claims (1)

[Claims] an in-phase output signal circuit that receives a common input signal and outputs an output signal that is in phase with the input signal through an even number of CMOS inverters, and a signal that is in the opposite phase of the input signal, and includes at least one stage of the CMOS inverters; and a reverse phase signal output circuit that outputs C, the reverse phase output circuit outputs C.
A logic circuit characterized by having a MOS buffer.