JPH03160690A - Memory system - Google Patents

Abstract

PURPOSE:To attain the executing of an ordinary operation and the high-speed operation with an integrated hardware without being limited to a continuous region by executing the switching of the ordinary operation and the high-speed operation with an operation mode selecting part. CONSTITUTION:At the operation mode selecting part 24, whether the access destination of preceeding memory part and the access destination of this time as for row and column are in the same page or not is decided and when they are in the same page, the high-speed operation is commanded to a strobe signal generation part 18. On the contrary, when they are in the different pages, the ordinary operation is commanded. At the generation part 18, the setting of the RAS is held in response to the high-speed operation command, and the access of memory part is carried out with only the setting of the other strobe signal CAS. In other way, on the contrary of an ordinary operation command, the ordinary operation accessing the memory part is executed with the setting of the RAs and the CAS. Consequently, the high-speed operation and the ordinary operation are carried out properly by turns. And the high-speed operation state is released by a release command after a fixed time of post access from the selective part 24, and the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed operation control means for a memory system, particularly a memory system employing a dynamic random access memory (hereinafter referred to as DRAM).

[Prior Art] DRAM is one of the typical memory elements.
This is often used to configure memory systems.

Generally, when giving an address to a DRAM, a row address (ROW) and a column address (COLUMN) are given by time division, and a row strobe signal (Row address
ss strobe signal; R A S
) and the column strobe signal (Colu+*n addresses
s strobe s1gnal ; CAS) controls access by $1 (a normal operation mode).

Therefore, in order to give an address to the DRAM, address switching between ROW and COLUMN is required.

As a high-speed operation mode that ensures faster operation than the normal operation mode, a method using a DRAM page mode, a static column method, etc. have been known.

For example, when attempting to access the same row continuously, it is sufficient to set ROW first and then sequentially provide only COLUMN. In this way, compared to the normal operation mode, high-speed access is possible by eliminating address switching.

Also, the high-speed operation mode is executed by special hardware such as a dedicated controller.

Problems to be Solved by the Invention However, conventional high-speed operation is based on access to continuous areas of DRAM, which is inconvenient for completely random access.

Also, in high-speed operation mode, for example, RAS
must maintain active control over the
In this case, the DRAM will consume a lot of power.

The present invention was made with the aim of solving these problems, and aims to realize a high-speed operation mode and a normal operation mode with integrated hardware without being limited to continuous area access. shall be.

Another object of the present invention is to suppress power consumption in hardware that operates at high speed.

[Means for Solving the Problems] In order to achieve the above object, the memory system of the present invention determines whether the current access destination of a memory section including a DRAM is the same page as the previous access destination, and determines whether the same page In this case, the strobe signal generator is commanded to operate at high speed,
It has an operation mode selection section that commands normal operation when the page is different, and the strobe signal generation section holds one of the RAS settings and changes it according to the CAS settings when a high-speed operation command is issued from the operation mode selection section. It is characterized in that access is controlled, and when a normal operation command is issued, access control is performed by setting both RAS and CAS.

Further, the present invention provides that the operation mode selection section cancels the high-speed operation of the strobe signal generation section after a certain period of time has elapsed since the previous access to the memory section, or cancels the high-speed operation using a refresh signal that is periodically input. It is characterized by

[Operation] In the present invention, the operation mode selection section makes decisions regarding row and column addresses. This determination is a determination as to whether the previous access destination of the memory section and the current access destination are the same page. As a result of the determination, if the pages are the same, the operation mode selection section instructs the strobe signal generation section to operate at high speed. Conversely, if the page is different, normal operation is commanded. The strobe signal generation section is
The RAS setting is held in response to the high-speed operation command, and the memory section is accessed only by the other strobe signal, that is, the CAS setting. On the other hand, when receiving a normal operation command, the strobe signal generation section executes a normal operation of accessing the memory section with the settings of RAS and CAS. Therefore, high-speed operation and normal operation are executed while being alternated as appropriate.

Further, in the memory system according to claim (2) of the present invention, the operation mode selection section instructs the strobe signal generation section to cancel high-speed operation after a certain period of time has elapsed since the memory section was accessed. As a result, the memory section does not take a high-speed operating state that consumes a lot of power during non-access periods, and the power consumption when accessing the memory section is reduced.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a memory system according to an embodiment of the present invention.

The memory system shown in this figure has a predetermined number of DRAs.
A DRAM section 10 including M elements, an address control section 16 that takes in ROW and COLUMN from an address bus 12 and gives an address to the DRAM section 10 via a time division bus 14, and a RAS that issues RAS and CAS to the DRAM section 10. /CAS sitting part 18.

Historically, the RAS/CAS generation unit 1 arbitrates between external access requests and refresh requests to the DRAM unit 10.
an arbitration unit 20 that issues an access request reception success signal or a refresh request reception success signal to
The communication control unit 22 includes a communication control unit 22 that generates an access completion signal in response to an access request reception success signal.

In this example, a feature of the invention, ROW
An operation mode control section 24 is provided that issues a high-speed mode instruction signal to the RAS/CAS generation section 18 in accordance with the above.

Note that 26 in the figure is a data bus that supplies data to be written to the DRAM section 10 in response to access.

FIG. 2 shows the state transition of the RAS/CAS generating section 18 in this embodiment.

The operation of this embodiment will be explained below.

When the memory system according to this embodiment is started up by turning on the power, etc., the RAS/CAS generation unit 18 is in an idle state 100. What is IDNO1 state 100?
This is a so-called access waiting state.

When an access request is supplied to the arbitration unit 20, this access request is coordinated with a refresh request.

As a result of this stoppage, when the access request is accepted, the access request reception success f≦ is determined by the RAS/CAS generation unit 18.
is issued. Conversely, when a refresh request is accepted, a refresh request acceptance success signal is sent to RAS/CAS.
It is issued to the generating section 18.

The RAS/CAS generation unit 18 shifts to the normal operating state 200 in response to the access request acceptance signal (3 0 0
).

At this time, first, the RAS/CAS generation section 18 issues RAS to the DRAM section 10, and the address control section 16 sends RAS to the DRAM section 10.
OW is given to the DRAM section 10.

Next, the RAS/CAS generation section 18 issues an address switching signal to the address control section 16, and further sends the CAS to the DRAM section 1.
Emit at 0. At this time, the address control unit 16
O L UMN is provided to the DRAM section IO.

In this way, the DRAM section 10 is accessed.

The communication control unit 22 issues an access completion signal indicating that the access has been completed to an external device, for example, a memory access request unit, in response to the access request reception success signal, thereby enabling asynchronous communication.

The refresh request is accepted by the arbitration unit 20, and a refresh request acceptance signal is sent to the RAS.
/CAS is issued to the RAS/CAS generator 18, the RAS/CAS generator 18 transitions to the refresh state 400 (302).
, the DRAM section 10 (7) refresh cycle is executed.

After the refresh cycle is executed, the process returns to the idle state 100 (304). We also have normal operation status according to the required trade! ! 200 to completely fresh state 400 (3
06), conversely, a transition from the refresh state 400 to the normal operating state 200 (308) is also executed.

In this embodiment, there is a transition 310 from the normal operating state 200 to the high speed operating state 500 and a transition 31 in the opposite direction.
2 is performed according to the determination by the operation mode selection section 24.

High speed operation! ! 350o means D, which is a conventionally known operation.
This is the state of operation using the page mode of the RAM section 10.

The feature of the present invention is that the address bus 12
The operation mode control unit 24 determines whether the previous access destination and the current access destination are the same according to the ROW supplied from the ROW, and depending on this result, the normal operation state 200 and the high speed operation state 200 are selected. 500, transitions 310 and 312 are to take place.

This determination is a determination as to whether the previous and current access destinations are the same address.

As a result of the determination, if they are the same, the high-speed mode instruction signal issued from the operation mode # control unit 24 to the RAS/CAS generation unit 18 will have a value corresponding to transition 310, and if they are different, it will have a value corresponding to transition 312. become.

Further, the operation mode selection unit 24 returns the RAS/CAS generation unit 18 from the normal operation state 200 to the idle state 100 after a predetermined time has elapsed since the previous access (3 1 4).

This transition 314 releases the high power consumption high speed operating state 500.

Further, when the high-speed operation state 500 is present at the time of a refresh request, the high-speed operation state 500 is changed by transition 314 and transition 302.
Transition 316 for resetting 00 is executed.

In FIG. 2, 318, 320, and 322 indicate the idle state 100 and the normal operating state Ei!, respectively. 200, a self-transition loop in a fast operating state 500;

[Effects of the Invention] As explained above, according to the present invention, since the operation mode selection unit switches between normal operation and high-speed operation,
Normal operation and high-speed operation can be realized with integrated hardware without being limited to continuous area access.

Further, according to the present invention, high-speed operation is performed after a certain period of time has passed.
This allows for a power-saving memory system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a memory system according to an embodiment of the present invention, and Fig. 2 shows the state of the RAS/CAS management section in this embodiment. ! ! It is a diagram showing transition. 10... DRAM unit 16... Address control unit 18... RAS/CAS generation unit 24... Operation mode selection unit 200... Normal operating state 500... High speed operating state ROW... Row address

Claims (2)

[Claims] (1) A memory section including a dynamic, random, access memory and having a page mode; an address control section that provides row and column addresses to the memory section in a time-sharing manner; and a row and column address strobe signal that issues to the memory section. and a strobe signal generation unit that controls access to a memory unit by determining whether the current access destination of the memory unit is the same page as the previous access destination, and if it is the same page, the strobe signal generation unit controls access to the memory unit. an operation mode selection section that instructs the signal generation section to perform high-speed operation, and instructs the signal generation section to perform normal operation in the case of a different page; when the strobe signal generation section receives a high-speed operation instruction from the operation mode selection section, the strobe signal generation section selects the row address; A memory system characterized in that the setting of a strobe signal is held and the access is controlled by the setting of the other column address strobe signal, and when a normal operation command is issued, the access is controlled by the setting of both the row address strobe signal and the column address strobe signal. (2) The memory system according to claim (1), wherein the operation mode selection section cancels the high-speed operation of the strobe signal generation section after a certain period of time has elapsed since the previous access to the memory section. .