JPH0520253A - Data processor - Google Patents

Abstract

PURPOSE:To contract hardware and to reduce cost while attaining occasional access from a CPU to a memory in a data processor provided with a function block having a memory access function in addition to the CPU. CONSTITUTION:A RAM 7 is shared by the CPU and the 1st and 2nd function blocks 3, 4 through a data transfer control part 1 and the operation of the control part 1 is executed based upon a time division system consisting of a transfer mode and a CPU mode so that the CPU 5 can occasionally access the RAM 7. The control part 1 is provided with the 1st to 4th holding circuits 31 to 34 for holding data, and when a write request signal 101 or a read request signal 105 is received from the CPU 5 during the period of the transfer mode for transmitting an access from the 1st or 2nd function block 3 or 4 to the RAM 7, returns a wait signal 103 to the CPU 5 to wait the CPU 5 and transmits the access from the CPU 5 to the RAM 7 at the time of switching the transfer mode period to a CPU mode period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a functional block having a memory access function in addition to a central processing unit.

[0002]

2. Description of the Related Art Data including a central processing unit (hereinafter referred to as a CPU) for accessing a memory such as a RAM for executing a program, and data including a functional block having a memory access function in addition to the CPU. Processing devices are known.

FIG. 4 is a block diagram showing the configuration of a conventional data processing apparatus of this type. In the figure, the first RAM 2 is a memory for storing data, and the data transfer control unit 1 mediates each access of the first and second functional blocks 3 and 4 to the first RAM 2. It is a thing. The second RAM 6 is another memory for storing programs and data, and the CPU 5 is the second RAM 6
The program is executed while accessing.
However, the CPU 5 also controls the operations of the data transfer control unit 1 and the first and second functional blocks 3 and 4.

The operation of the conventional data processing apparatus having the above configuration will be briefly described. In the case of executing data transfer from the first functional block 3 to the first RAM 2, that is, writing of data to the first RAM 2. First, data is passed from the first functional block 3 to the data transfer control unit 1. The data transfer control unit 1, which has received the data from the first functional block 3, temporarily holds the data and outputs the held data while giving the write address to the first RAM 2 to output the first data to the first RAM 2. Write to a predetermined address in RAM2. From the second functional block 4 to the first RAM 2
The writing of data to is executed by the same procedure.

From the first RAM 2 to the first functional block 3
Or data transfer to the second function block 4, that is, the first
When the data of the RAM 2 is read, the data transfer control unit 1 first reads the data of the predetermined address of the first RAM 2 and temporarily holds the read data. The data transfer control unit 1 further stores the held data in the first
To the second functional block 4 or the second functional block 4.

On the other hand, the CPU 5 has the first functional block 3
Alternatively, even during data transfer between the second functional block 4 and the first RAM 2, the second RAM 6 can be accessed at any time regardless of the state of the data transfer control unit 1.

[0007]

SUMMARY OF THE INVENTION In the conventional data processing apparatus, the data storage memory (first RAM) accessed by the first functional block 3 or the second functional block 4 is used.
Since 2) and the memory (second RAM 6) for storing the program and data accessed by the CPU 5 are separate, there is a problem that the hardware of the memory becomes large and at the same time the cost becomes high. It was

An object of the present invention is to reduce the hardware and reduce the cost in a data processing device provided with a functional block having a memory access function in addition to the CPU, while realizing the occasional access to the memory by the CPU. It is in.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention allows a CPU and a functional block to share a memory via a data transfer control unit so that the CPU can access the memory at any time. The operation mode of the unit is a time division method.

More specifically, the invention of claim 1 is
A storage device for storing programs and data, a data transfer control unit for mediating access to the storage device, a CPU for accessing the storage device via the data transfer control unit, and the data transfer The data transfer control unit includes a functional block different from the CPU that accesses the storage device via the control unit, and the data transfer control unit sets one time division operation mode period for mediating access to the storage device by the functional block. When the access request signal is received from the CPU during the transfer mode period, the function of mediating access to the storage device by the CPU at the time of switching from the transfer mode period to the CPU mode period as another time division operation mode period It adopts a configuration having.

According to a second aspect of the present invention, in the first aspect of the present invention, the data transfer control section is composed of first to third holding circuits and a data transfer control circuit described below. That is, the first holding circuit holds the data read from the storage device for passing to the CPU or the functional block. The second holding circuit holds the data given from the CPU for writing to the storage device. The third holding circuit holds the data given from the functional block for writing to the storage device. The data transfer control circuit controls the operations of the first and second holding circuits to mediate access to the storage device by the CPU, and the first to mediate access to the storage device by the functional block. 1 and 3
Control the operation of the holding circuit, and when the write request signal is received as the access request signal from the CPU during the transfer mode, the data held by the CPU is held in the second holding circuit. At the same time, a wait signal is returned to the CPU in order to prohibit the CPU from re-outputting the write request signal.
When a read request signal is received from the CPU as an access request signal during the transfer mode, it has a function of writing the data held in the second holding circuit to the storage device after waiting for switching to the mode period. A wait signal is returned to the CPU in order to prohibit re-output of the read request signal by the CPU, data is read from the storage device after waiting for switching from the transfer mode period to the CPU mode period, and the read data is read as the first data. The holding circuit holds the data and the data held in the first holding circuit is transferred to the CPU.

[0012]

According to the invention of claim 1, a CPU and the CPU
Another storage device and a functional block having a memory access function share one storage device via the data transfer control unit.
However, the access to the storage device by the functional block is limited to the transfer mode period of the entire operation period of the data transfer control unit, and the data transfer control unit may operate during the transfer mode period.
When the access request signal is received from U, the access to the storage device by the CPU is mediated when the transfer mode period is switched to the CPU mode period. As a result, even when a large amount of data is continuously transferred between the functional block and the storage device and the data transfer requires a long time, the CPU can access the storage device at any time.

According to the second aspect of the invention, when the data transfer from the functional block to the storage device, that is, the writing of the data to the storage device is executed, the data given from the functional block is the third data. It is temporarily held in the holding circuit. Under the control of the data transfer control circuit, the held data is transferred from the third holding circuit to the storage device and written in the storage device within the transfer mode period.

When data transfer from the storage device to the functional block, that is, reading of data from the storage device is executed, data is read from the storage device within the transfer mode period, and the read data is stored in the first holding circuit. The data is temporarily held, and the held data is passed from the first holding circuit to the functional block under the control of the data transfer control circuit.

On the other hand, when the data transfer control circuit receives the write request signal for the storage device from the CPU during the transfer mode, the data transfer control circuit first holds the data given from the CPU in the second holding circuit, and In order to prevent loss of stored data, a wait signal is returned to the CPU to put the CPU in a standby state, and re-output of the write request signal by the CPU is prohibited. Then, after waiting for switching from the transfer mode period to the CPU mode period, the data held in the second holding circuit is written in the storage device.

Further, when the data transfer control circuit receives a read request signal for the storage device from the CPU during the transfer mode period, it first returns a wait signal to the CPU to prohibit re-output of the read request signal by the CPU. Keep it. Then, after waiting for the switching from the transfer mode period to the CPU mode period, the data is read from the storage device, and the read data is held in the first holding circuit,
The data held in the first holding circuit is passed to the CPU.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an outline of the configuration of a data processing device in an embodiment of the present invention. In the figure, a RAM 7 is a memory for storing programs and data, and includes first and second functional blocks 3 and 4.
In addition, the CPU 5 can be accessed via the data transfer control unit 1. However, even while data transfer is being performed between the first functional block 3 or the second functional block 4 and the RAM 7, the CPU 5 promptly operates the RAM.
7, the operation mode of the data transfer control unit 1 is the transfer mode for mediating access to the RAM 7 by the first functional block 3 or the second functional block 4 as shown in FIG. RAM7 by CPU5
It is divided into two time division modes, a CPU mode for mediating access to the. The data transfer control unit 1 and the first and second functional blocks 3 and 4 are
Under the control of U5.

The operation of the data processing apparatus of this embodiment having the above configuration will be described below. The first functional block 3 to the RAM 7
When data is transferred to the RAM 7, that is, data is written to the RAM 7, the data is first passed from the first functional block 3 to the data transfer control unit 1. By receiving the data from the first functional block 3, the data transfer control unit 1 temporarily holds the data, waits for switching to the transfer mode period, and outputs the held data while giving the write address to the RAM 7. The data is written in a predetermined address of RAM 7. RA from the second functional block 4
The writing of data to M7 is executed in the same procedure.

When the data transfer from the RAM 7 to the first functional block 3 or the second functional block 4, that is, the reading of the data of the RAM 7 is executed, the data transfer control unit 1 first determines the predetermined value of the RAM 7 within the transfer mode period. The data of the address is read, the read data is temporarily held, and the held data is transferred to the first functional block 3 or the second functional block 4.

On the other hand, when the data transfer control unit 1 receives an access request signal from the CPU 5 during the transfer mode period, it mediates access to the RAM 7 by the CPU 5 at the time of switching to the CPU mode period. That is, CPU
5 is the first functional block 3 or the second functional block 4
Even during the data transfer between the RAM 7 and the RAM 7, the RAM 7 can be accessed when the operation mode of the data transfer control unit 1 is switched to the CPU mode.

FIG. 3 shows the detailed internal structure of the data transfer control unit 1 as first and second functional blocks 3 and 4, the CPU 5 and the RAM 7, which are other components of the data processing apparatus.
It is the block diagram shown together with. However, illustration of control lines from the CPU 5 to the first and second functional blocks 3 and 4 is omitted.

In the data transfer control unit 1 shown in FIG.
Reference numeral 1 is a first holding circuit for holding the data read from the RAM 7, and the data held in the first holding circuit 31 is the first functional block 3 selected by the first control signal 100. , Second functional block 4 or CPU
Passed to any of the five. 32 is a second holding circuit for holding the data given from the CPU 5 for writing to the RAM 7, 33 is a third holding circuit for holding the data given from the first functional block 3, 3
Reference numeral 4 is a fourth holding circuit for holding the data given from the second functional block 4. 35 is a RAM control circuit for controlling writing and reading of the RAM 7,
Reference numeral 36 is a flag circuit for storing that there is a write request from the CPU 5 to the RAM 7, and 37 is a wait control circuit for timing adjustment. The RAM control circuit 35, the flag circuit 36, and the wait control circuit 37 are
A data transfer control circuit 3 for coordinating access to the RAM 7 by the first function block 3 or the second function block 4 and access by the CPU 5 to the RAM 7.
Make up 8.

The internal operation of the data transfer control unit 1 described above will be described. From the first functional block 3 to the RAM 7
When the data transfer to the RAM 7, that is, the writing of the data to the RAM 7 is executed, the data given from the first functional block 3 is temporarily held in the third holding circuit 33.
Since the third holding circuit 33 is not shared with the CPU 5 but dedicated to the first functional block 3, it is possible to immediately hold data even during the CPU mode period. Then, the data held in the third holding circuit 33 waits for switching to the transfer mode period in the CPU mode immediately during the transfer mode period, and then the RAM control circuit 3
RAM 7 by the first control signal 100 output from
To the RAM 7 by the write signal 104 which is also output from the RAM control circuit 35. The writing of data from the second functional block 4 to the RAM 7 is executed by the same procedure using the fourth holding circuit 34.

When data transfer from the RAM 7 to the first functional block 3, that is, reading of data from the RAM 7 is executed, data is first read from the RAM 7 by the read signal 107 output from the RAM control circuit 35, and the RAM 7 is read. The data read from the
It is temporarily held in the first holding circuit 31 by the first control signal 100 output from the M control circuit 35. However, since the first holding circuit 31 is shared by the CPU 5 and the first and second functional blocks 3 and 4, the reading and holding of the data of the RAM 7 is executed immediately during the transfer mode period. In the CPU mode, it is executed after waiting for switching to the transfer mode period. The data held in the first holding circuit 31 in this manner is passed to the first functional block 3 which is also selected by the first control signal 100. The reading of data from the RAM 7 to the second functional block 4 is also executed in the same procedure via the first holding circuit 31.

On the other hand, during the transfer mode period, the CPU 5 sends R
When the write request signal 101 for the AM 7 is output, first, the data given from the CPU 5 is temporarily held in the second holding circuit 32 by the write request signal 101. Since the second holding circuit 32 is not shared with the first and second functional blocks 3 and 4 but dedicated to the CPU 5, it is possible to immediately hold data even during the transfer mode period. . The write request signal 101 is also given to the flag circuit 36, and the flag circuit 36 outputs the CPU
The fact that there is a write request from 5 is stored. As a result, the flag signal 102 which is the output of the flag circuit 36 is set. The wait control circuit 37 that has received the flag signal 102 that has been set informs the RAM control circuit 35 that it has received the flag signal 102 through the second control signal 106.
In addition, the wait signal 103 is returned to the CPU 5 until the flag signal 102 is reset in order to prevent the loss of the data held in the second holding circuit 32, and the re-output of the write request signal 101 by the CPU 5 is performed. Prohibit. On the other hand, the data held in the second holding circuit 32 is output from the second holding circuit 32 by the first control signal 100 output from the RAM control circuit 35 after waiting for switching from the CPU mode period to the transfer mode period. The data is output to the RAM 7, and the RAM control circuit 35 is also provided.
It is written in the RAM 7 by the write signal 104 output from. The write signal 104 is the flag circuit 36.
Is also given to reset the flag signal 102. As a result, the wait signal 103 is released and the standby state of the CPU 5 ends.

The read request signal 105 of the CPU 5 is given to the wait control circuit 37. Read request signal 105 from CPU 5 to RAM 7 during the transfer mode period
Is output, the data cannot be passed to the CPU 5 immediately, so that the wait signal 103 is first returned to the CPU 5 to continue the output of the read request signal 105 to the CPU 5, and the re-output is prohibited. Keep it. The wait control circuit 37 notifies the RAM control circuit 35 through the second control signal 106 that the read request signal 105 has been received from the CPU 5. On the other hand, wait for the transfer mode period to switch to the CPU mode period
Data is read from the RAM 7 by the read signal 107 output from the control circuit 35, and the data read from the RAM 7 is stored in the first holding circuit by the first control signal 100 also output from the RAM control circuit 35. 31
Temporarily held in. In this way, the first holding circuit 31
The data held in the same is passed to the CPU 5 similarly selected by the first control signal 100. However, the wait control circuit 37 releases the wait signal 103 when the operation mode is switched to the CPU mode.

When the CPU 5 outputs the write request signal 101 to the RAM 7 during the CPU mode period, the data supplied from the CPU 5 is temporarily held in the second holding circuit 32 by the write request signal 101. In addition to the data held in the second holding circuit 32, R data is generated by the first control signal 100 and the write signal 104 immediately output from the RAM control circuit 35.
Immediately written to AM7. Further, during the CPU mode period, the read request signal 1 from the CPU 5 to the RAM 7
If 05 is output, the wait control circuit 37 sends CP
The wait signal 103 is not returned to U5, and the read signal 107 output immediately from the RAM control circuit 35 and the first control signal 100 cause the read data of the RAM 7 to be immediately passed to the CPU 5 via the first holding circuit 31. Be done.

[0029]

As described above, according to the first aspect of the invention, in the data processing device having the functional block having the memory access function in addition to the CPU, the CPU and the functional block are connected via the data transfer control unit. Since the memory is shared by and, the operation mode of the data transfer control unit is a time-division system of a CPU mode for mediating access by the CPU and a transfer mode for mediating access by the functional block. The hardware can be reduced and the cost can be reduced while realizing the memory access by the CPU at any time.

According to the second aspect of the present invention, the first to third holding circuits for holding data, and when the access request signal is received from the CPU during the transfer mode period, the CPU is put on standby while the CPU is waiting. Since the structure of the data transfer control unit provided with the data transfer control circuit for controlling the operation of the three holding circuits so as to mediate the access by the CPU at the time of switching to the mode period is adopted, the memory of the functional block is adopted. A good coordination between the access and the memory access of the CPU can be achieved. Moreover, since the first holding circuit used when reading the memory data is shared by the CPU and the functional block, the hardware of the data transfer control unit can be downsized and the cost can be reduced. In addition, since the second holding circuit and the third holding circuit used when writing data to the memory are separately provided for the CPU and the functional block, even if they are provided from the CPU even during the transfer mode period. The stored data can be held in the second holding circuit in advance before being switched to the CPU mode, so that data writing to the memory can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a data processing device according to an embodiment of the present invention.

2 is a timing chart showing an operation mode of a data transfer control unit in FIG.

FIG. 3 is a block diagram showing an internal detailed configuration of a data transfer control unit in FIG. 1 together with other components of the data processing device.

FIG. 4 is a block diagram showing a configuration of a conventional data processing device.

[Explanation of symbols]

1 ... Data transfer control unit 2 ... First RAM 3 ... First functional block 4 ... Second functional block 5 ... CPU (central processing unit) 6 ... second RAM 7 ... RAM (storage device) 31 ... First holding circuit 32 ... Second holding circuit 33 ... Third holding circuit 34 ... Fourth holding circuit 35 ... RAM control circuit 36 ... Flag circuit 37 ... Weight control circuit 38 ... Data transfer control circuit 100 ... First control signal 101 ... Write request signal (access request signal) 102 ... Flag signal 103 ... Wait signal 104 ... Write signal 105 ... Read request signal (access request signal) 106 ... Second control signal 107 ... Read signal

Claims (2)

[Claims] 1. A storage device for storing programs and data, a data transfer control unit for mediating access to the storage device, and a central processing for accessing the storage device via the data transfer control unit. An apparatus and a functional block different from the central processing unit that accesses the storage device via the data transfer control unit, wherein the data transfer control unit mediates access to the storage device by the functional block. In the case where an access request signal is received from the central processing unit during the transfer mode period as one time division operation mode period, the transfer mode period is switched to another CPU mode period as the time division operation mode period. A data processing device having a function of mediating access to the storage device by the central processing unit at a point of time. 2. The data processing device according to claim 1, wherein the data transfer control unit holds data read from the storage device for passing to the central processing unit or the functional block.
Holding circuit, a second holding circuit for holding data given from the central processing unit for writing to the storage device, and holding data given from the functional block for writing to the storage device A third holding circuit for controlling the operation of the first and second holding circuits to mediate access to the storage device by the central processing unit, and to the storage device by the functional block. A data transfer control circuit for controlling the operations of the first and third holding circuits to mediate the access of the data transfer control circuit from the central processing unit during the transfer mode period. When the write request signal is received as the access request signal, the data given from the central processing unit is held in the second holding circuit and Processor advance returns a wait signal to the central processing unit in order to prohibit the re-output of the write request signal by the C from the transfer mode period
When the data held in the second holding circuit is written to the storage device after waiting for switching to the PU mode period and a read request signal is received as an access request signal from the central processing unit during the transfer mode period Returns a wait signal to the central processing unit in order to prohibit re-output of the read request signal by the central processing unit,
Waiting for switching from the transfer mode period to the CPU mode period, data is read from the storage device, the read data is held in the first holding circuit, and the data held in the first holding circuit is read. A data processing device having a function of passing the data to the central processing unit.