JPH0314718Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Industrial Field of Application] This invention relates to an automatic rhythm performance device, and more particularly to an automatic rhythm performance device that can arbitrarily move the sound image position of generated sound. [Prior Art] Automatic rhythm performance devices that synchronize a plurality of percussive sound sources with a predetermined rhythm pattern and generate sounds are incorporated into, for example, electronic organs, or are used in conjunction with the performance of various musical instruments. This contributes to improving the performance effect. [Problems to be solved by the invention] By the way, in conventional automatic rhythm performance devices, the sound image of the generated musical tones is fixed;
The problem was that the generated sound did not have a spatial spread, and as a result, the rhythm lacked a sense of dynamism. This idea was made in view of the above-mentioned circumstances, and allows the sound image position of a desired sound source of the generated musical tones to be moved appropriately in synchronization with the rhythm pattern, thereby achieving spatial expansion of the generated musical tones. The purpose of the present invention is to provide an automatic rhythm performance device that can perform the following functions. [Means for Solving the Problems] In order to solve the above problems, this invention appropriately reads out a plurality of types of musical tone data stored in advance based on a predetermined rhythm signal, and generates rhythm musical tones using the read musical tone data. An automatic rhythm playing device that forms signals, the musical sound signal forming means forming a musical sound signal corresponding to the musical sound data to a plurality of musical sound generating sections provided spatially apart, and a sound image of each of the musical sound data. a control data storage means storing control data specifying a position; and a control data storage means for reading out the control data corresponding to a musical tone based on the predetermined rhythm signal, and determining a volume ratio of each musical tone generating section based on the control data. It is characterized by comprising a sound image position control means for controlling the sound image position. [Function] According to the above configuration, the volume ratio in each musical tone generating section is controlled based on the control data corresponding to the musical tone, and the position of the sound image is controlled. Therefore, it is possible to obtain a spatial spread of the generated musical tones. [Example] Hereinafter, an example of this invention will be described with reference to the drawings.

[Configuration of Example]

FIG. 1 is a block diagram showing the structure of an embodiment of this invention. In the embodiment shown in this figure, multiple types of percussive musical tone data are stored in advance.
This musical sound data is read out as appropriate to generate rhythm sounds made up of a plurality of musical instrument sounds, and the rhythm sounds are transmitted through speakers 1L and 1R provided spaced apart on the left and right.
This allows the sound image of a specific instrument to be moved left or right,
Or they put on an accent. Also,
The formation of each instrument sound in this embodiment is performed by time-sharing processing within one cycle of a channel signal CH (described later) with a constant cycle, so that each instrument sound formed within the same cycle is sounded at the same time. It's getting old. Now, in FIG. 1, channel counter 2 is an octal up counter that counts clock pulse _φ1 , and its count output is "0" to
"7" is output to each part of the circuit as a channel signal CH. In this case, channel signal CH “0”
The formation timing of various musical instrument sounds (including the position of the sound image and accent) is assigned to each of the 7. For example, 0: Bass drum (strong) 1: Bass drum (weak) 2: Clap hand ( 3: Left sound image of the clap hand 4: Right sound image of the clap hand 5: Cowbell 6: Snare drum 7: High hat cymbal. Note that the above-mentioned allocation can be changed as appropriate by the configuration described later. Next, the waveform memory RAM (random access memory) 3 is, for example, a RAM configured with eight memory blocks 3a to 3h as shown in FIG.
Eight types of musical sound waveforms are stored in advance in each memory block. In this case, the musical sound waveforms stored in each memory block 3a to 3h are:
Each waveform is a waveform from rising to attenuation to silencing, and this waveform data is stored sequentially from the start address (hereinafter referred to as start address STAD) of each storage block. The waveform ROM (read-on memory) 4 is a memory that supplies waveform data to the waveform RAM 3, and each waveform data in the waveform RAM 3 described above is the same as the data in this waveform ROM 4. Further, the waveform ROM 4 is configured to be replaceable, and if the waveform ROM 4 is replaced with a waveform ROM having different contents, the contents of the waveform RAM 3 will also be different. In this case, data transfer from the waveform ROM 4 to the waveform RAM 3 is performed by the read/write control circuit 5,
In addition, _S1 in the figure is a read/write control signal,
RWAd is address data. Next, the address RAM 6 consists of an end address table 7, a start address table 8, and a control data table 9. in this case,
The end address table 7 is a table in which relative end addresses ENADa' to ENADh' of eight types of tone waveforms stored in the waveform RAM 3 are stored. Here, the relative end address
ENADa' to ENADh' are the values obtained by subtracting the respective start addresses STADa to STADh from the actual end addresses ENADa to ENADh (see FIG. 2) of each tone waveform. This end address table 7 contains the relative end addresses ENADa'~ of the musical sound waveform specified by the channel signal CH.
ENADh' is outputted to the input terminal A of the comparator circuit 11.
In this case, when the channel signal CH is "0" or "1", the relative end address ENADa' of the bass drum is selected, and when it is "2", "3", or "4", the relative end address ENADb' of the clap hand is selected. is selected,
Also, when "5" to "7", the relative end address of the cowbell, snare drum, and high hat cymbal.
ENADc′ to ENADe′ are each selected. The start address table 8 contains the start addresses STADa~ of each musical tone waveform in the waveform RAM 3.
This table stores STADh, and outputs the start addresses STADa to STADh of the musical sound waveform specified by the channel signal CH to the input terminal A of the adder circuit 12. In this case, as in the case of end address 7 mentioned above, when the channel signal CH is "0" or "1", the start address
When STADa is selected and "2", "3", and "4", the start address STADb is selected, and when it is "5" to "7", the start address STADc is selected.
~STADe are each selected. This is because the waveform data is determined only by the type of musical tone (type of musical instrument), and the sound image position and accent of the musical tone are not related to the waveform data. The control data table 9 is as shown in FIG.
It consists of 1-byte storage areas 9a to 9h, each selected by channel signals CH "0" to CH7, and 2-bit control data is stored in the 0th and 1st bits of each storage area 9a to 9h. is memorized. When this control data "D ₁ D ₀ " is "11", the sound image position is at the center, when it is "01" and "10", the sound image position is on the left and right, respectively, and when it is "00", the sound image position is at the center.
When , the position of the sound image is controlled so that it is in the center and has a strong beat. And these bit outputs D ₀ ,
D ₁ is output as signals Q ₁ and Q ₂ , respectively. Next, the address ROM 14 is a memory for supplying address data and control data to each of the tables 7 to 9 described above.
A plurality of combinations of address data and control data to be supplied to the controller are stored. Then, one of these data combinations is selected by the output signal of the rhythm selection switch 15, and this selected set of data is stored in the address RAM 6 under the control of the read/write control circuit 5. Transferred to each table 7-9. The change detection circuit 16 is a circuit that detects whether or not the output signal of the rhythm selection switch 15 has changed. When the change detection circuit 16 outputs a change detection signal, the read/write control circuit 5 is a circuit that detects whether or not the output signal of the rhythm selection switch 15 has changed. The data set in the address ROM is transferred to each table 7 to 9 in the address RAM 6. In this way, when the rhythm is changed using the rhythm selection switch 15, the contents of the address RAM 6 change.
As a result, the selected musical tone data (see Figure 2)
It will also be different. That is, the channel signal CH
The musical tones assigned to each of "0" to "7" are changed. The address ROM 14 is configured to be replaceable, and by replacing the address ROM with a different content, the channel signal CH "0" can be changed.
The degree of freedom in allocating musical tones to "7" can be greatly expanded. The rhythm pattern generation circuit 18 is a circuit that generates eight types of rhythm pulses corresponding to each rhythm, and each rhythm pulse pattern (rhythm pattern) is determined by the type of rhythm selected by the rhythm selection switch 15 (e.g. , Disco, Rock,
(swing, etc.), and generation/stop of each rhythm pulse is controlled by turning on/off the start switch 19. Then, each generated rhythm pulse is output in a time-division manner according to the channel signal CH. i.e. the channel signal
When CH is "0", the rhythm pulse of the bass drum (strong) is used, when it is "1", the rhythm pulse of the bass drum (weak) is used, and when it is "8", the rhythm pulse of the high hat cymbal is used. Each is output. Next, the address data generation circuit 20 has a configuration shown in FIG. In the figure, 21 is an adder circuit, 22 is a gate that opens when a "0" signal is supplied to the terminal DIS, and closes when a "1" signal is supplied (all output terminals are gates that output "0" signals, and 23 is a gate that has multiple output terminals) A bit (for example, about 15 bits) 8-stage shift register, 24 is a 1-bit 8-stage shift register, 25 to 27 are OR gates, and 28 is an AND gate.The above-mentioned shift register 23,
24 sequentially shift the signals supplied to the input terminals in synchronization with the clock signal _φ1 . Also,
The output signal of the shift register 23 is supplied to the input terminal B of the adder circuit 12 as address data ADD. Comparison circuit 11 receives relative end address ENADa'~
ENADh′ and address data ADD are compared, and when they match, a match signal EQ (“1” signal) is output to terminal T ₃ of address data generation circuit 20.
The adder circuit 12 adds the address data ADD and the data of the start addresses STADa to STADh,
This addition result is waveformed as address data AD.
Output to address terminal of RAM3. Next, when the "0" signal is supplied to the terminal EN, the shifter 30 shown in FIG. 1 outputs the output signal of the waveform RAM 3 as it is to the accumulators 31 and 32,
When a “1” signal is supplied to EN, the waveform RAM3
The output signal of is lowered by one digit (one binary digit) and the accumulator 3
This is a circuit that outputs to terminals 1 and 32. Therefore, when the output of the AND gate 33 becomes "1", the waveform
The output signal of the RAM 3 becomes 1/2 the value when passing through the shifter 30. The accumulators 31 and 32 sequentially accumulate the output of the shifter 30 while the channel signal CH is between "0" and "7", and then latches the accumulated results and converts the latched data into digital-to-analog conversion. The accumulated results are output to the DACs (hereinafter referred to as DACs) 35 and 36 to clear the accumulated results. The accumulators 31 and 32 then repeat the above-described operations.
However, when a "0" signal is supplied to the terminal EN, the accumulators 31 and 32 do not take in the output of the shifter 30 while this "0" signal is supplied. Both or one of the accumulators 31 and 32 is selected by a selection circuit 38 consisting of two OR gates and one NOR gate, and as a result, the output of the shifter 30 is output from the accumulator. 31 and 32, or only one of them.

[Operation of the example]

Next, the operation of this embodiment with the above-described configuration will be explained. First, when the power is turned on, a clock pulse φ ₁ is supplied to each part of the circuit, and a clock pulse φ ₁ is also supplied from an initial clear circuit (not shown).
An initial clear signal (“1” signal) having a pulse width longer than 16 cycles is output. and,
When this initial clear signal IC is output,
The output signal of the OR gate 27 shown in FIG. 4 is "1"
Then, each stage of the shift register 24 becomes "1". When all stages of the shift register 24 become "1", a "1" signal is output from the OR gate 25, the gate 22 is closed, and all stages of the shift register 23 are cleared. On the other hand, if the start switch 19 (FIG. 1) is in the off state, the rhythm pattern generation circuit 1
Since the output signal of inverter 8 is "0", inverter 4
A "1" signal is output from the address data generator 3 and supplied to the terminal T ₅ of the address data generation circuit 20 via the OR gate 42 . As a result, shift register 24 → OR gate 2
6→AND gate 28→OR gate 27, "1" in each stage in the shift register 24 is held, and the gate 22 continues to remain closed. According to the above-described operation, data "0" is always supplied to the input terminal B of the adder circuit 12, and as a result, the address data outputted by the adder circuit 12 is the channel signal CH "0" to CH "7". Start address STADa ~ selected as appropriate by
Return STADe. In this case, only the start address of the waveform RAM 3 is accessed, and a series of musical waveform data is not read out, so that no musical tone is formed at all. Next, when the operator turns on the start switch 19, the rhythm pattern generation circuit 18 generates rhythm pulses, and the rhythm pulses corresponding to each musical tone are sequentially output in a time-division manner based on the channel signal CH. FIG. 5 is a diagram showing the correspondence between the generation timing of the clock signal _φ1 and the channel signal CH.
Here, the description will focus on channel signal CH "0" (as mentioned above, the channel assigned to the bass drum (strong)). Now, between time t00 and t01, the output signal of the rhythm pattern generation circuit 18 becomes "1",
Subsequent times t00-t11, t20-t2
1, t30-t31, tK10-tK11, . . . , the output signal of the rhythm pattern generation circuit 18 becomes “0”. In this case, at time t00-t01, the terminal
A "0" signal is supplied to T ₅ (FIG. 4), and as a result, the signal read into the stage corresponding to the channel signal "0" of the shift register 24 at time t01 becomes "0". This read “0” signal is then used as the channel signal CH
At time t10-t11 when becomes "0", the signal is outputted from the shift register 24 to the terminal DIS of the gate 22 via the OR gate 25. As a result, the gate 22 is opened and the output signal of the adder circuit 21 is output to the shift register 23. At this time, since address data ADD "0" is output from the shift register 23 as described above, the adder 2
The output of 1 becomes a signal obtained by adding "1" to the least significant bit of this address data ADD, that is, a signal "1" (decimal). Then, this signal "1" is read into the shift register 23 at time t11, and then at time t when the channel signal becomes "0".
At 20-t21, address data ADD is output from the shift register 23. At this time,
The input terminal A of the adder circuit 12 receives a channel signal.
Start address selected by CH “0”
Since TADa is supplied, the address data AD output by the adder circuit 12 becomes AD=STADa+1 (1), and the address next to the first address STADa of the memory block 3a shown in FIG. 2 is accessed. Then, data within the same address is supplied to the shifter 30. On the other hand, in the control data table 9 shown in FIG. 1, the area 9a is selected by the channel signal CH "0", and as a result, the signals Q ₁ and Q ₂ shown in the same figure are both "0". . this signal
When Q ₁ and Q ₂ are both "0", a "0" signal is supplied to the terminal EN of the shifter 30, and a "1" signal is supplied to both the terminals EN of the accumulators 31 and 32. Ru. As a result, the data within the start address of the bass drum waveform output from the waveform RAM 3 passes through the shifter 30 as is and is supplied to both accumulators 31 and 32. Thereafter, in the same way as described above, the address accessed in the memory block 3a is incremented every time the channel signal CH becomes "0", and as a result, the waveform data of the bass drum is sequentially transferred to the accumulator 31, 32, and each of the accumulators 31 and 32 receives the channel signal CH
At the end of each cycle, the accumulated data is sequentially
Supplies to DAC35,36. As a result, the bass drum sound is output from the left and right speakers 1L and 1R. Then, when the output signal of the adder circuit 12 in which "1" is added to the address data ADD which is sequentially incremented matches the relative end address ENADa' selected by the channel signal CH "0", the comparator circuit 11 When the comparison circuit 11 detects a match signal EQ,
(“1” signal) is output. This signal EQ is the fourth
It is supplied to the terminal DIS of the gate 22 via the terminal T ₃ and the OR gate 25 shown in the figure. As a result,
The gate 22 is closed and a “0” signal is output to the shift register 23. Then, at the next time when the channel signal CH becomes "0", the address data is output from the shift register 23.
ADD becomes "0" again. And match signal EQ
is output, a "1" signal is written in the table corresponding to the channel signal "0" of the shift register 24, but from then on, the output signal of the rhythm pattern generation circuit 18 remains "0" as described above. Therefore, the “1” signal with this table is from shift register 24 → OR gate 26 → AND gate 2.
8→OR gate 27, and as a result, the address data ADD maintains "0". Therefore, the rhythm pattern generation circuit 1
The address data ADD remains at "0" until the output signal of No. 8 becomes "1" again. Furthermore, as is clear from the above explanation, the memory block 3a
The data read operation from the address ends one place before the end address. In the above manner, the channel signal CH "0"
The formation of musical tones takes place. And also for other channel signals CH "1" to "7",
The same musical tone formation as in the case described above takes place, but
The control data for the other channel signals CH "1" to "CH7" is different as shown in FIG. 3, and therefore the position and volume of the sound images emitted from the speakers 1L and 1R are different. This point will be explained below. First, if the channel signal CH is "1",
The control data "D ₁ D ₀ " is "11", and as a result,
Signals Q ₂ and Q ₁ shown in FIG. 1 both become "1" signals. When both the signals Q ₁ and Q ₂ become “1” signals, a “1” signal is supplied to the terminal EN of the shifter 30, and as a result, the data read from the waveform RAM 3 is changed as it passes through the shifter 30. The value becomes 1/2. Furthermore, when the signals Q ₁ and Q ₂ both become "1" signals, "1" signals are supplied to both terminals EN of the accumulators 31 and 32, and as a result, the output signal of the shifter 30 becomes the "1" signal. , 32. In this case, the channel signal CH "1" is assigned to the bass drum (weak) as described above, and the waveform data to be read out is stored in the memory block 3a (Fig. 2) as in the case of the channel signal "0".
This is the waveform data of the bass drum. Therefore, the bass drum sound is output from the speakers 1L and 1R. However, in the case of this channel signal "1", the value of the waveform data is reduced to 1/2 due to the downshifting operation of the shifter 30.
As a result, the volume is half that of the case where the channel signal is "0". Here, FIG. 6 is a musical score showing the disco rhythm pattern in this embodiment, and the bass drum part is shown in the first interval of the first row of this musical score. In this embodiment, in the channel signal CH "0" at the timing corresponding to the note to which the accent signal is added,
The output of the rhythm pattern generation circuit 18 becomes "1" so that the output of the rhythm pattern generation circuit 18 becomes "1", and the output of the rhythm pattern generation circuit 18 becomes "1" at the channel signal CH "1" at a timing corresponding to a note without an accent symbol. That's what I do. Therefore, as indicated by the same notes, the bass drum sound is outputted alternately in a strong, weak, strong, and weak manner, making it possible to play a bass drum part with an extremely high sense of realism. Next, when the channel signals are "2", "3", and "4", the control data "D ₁ , D ₀ " are "11", "10", "01", respectively, as shown in FIG. ”
Further, the waveform data to be selected is the waveform of the clap hand in the storage block 3b (FIG. 2) in any case. Then, when the control data "D ₁ , D ₀ " is "1, 1", the above-mentioned channel signal CH
As in the case of "1", the data read from the waveform RAM 3 is changed to 1/2 by the shifter 30.
After that, it is supplied to both accumulators 31 and 32. Therefore, channel signal CH "2"
In the case of , clapping sounds are emitted from both speakers 1L and 1R (however, they are not strong beats), and the position of the sound image is at the center. On the other hand, if the channel signal CH is "3",
Since the control data “D ₁ , D ₀ ” is “1, 0”,
The signals Q ₂ and Q ₁ become "1" and "0", respectively, and as a result, a "0" signal is supplied to the terminal EN of the shifter 33, and a "0" signal is supplied to the terminal EN of the accumulator 32, causing the accumulation A “1” signal is supplied to the terminal EN of the device 31, respectively. As a result, channel signal CH “3”
In this case, the data read from the waveform RAM 3 passes through the shifter 30 as is and is supplied only to the accumulator 31. Therefore, the channel signal
In the case of CH "3", the clapping sound is emitted only from the left speaker 1L. Also, if the channel signal CH is "4",
Since the control data “D ₁ , D ₀ ” is “0, 1”,
The signals Q ₂ and Q ₁ become "0" and "1", respectively, and as a result, contrary to the above case, clapping sound is emitted only from the right speaker 1R. Now, if we consider the volume of the clapping sound in channel signals CH "2" to "CH4", in the case of channel signal "2", although the clapping sound is emitted from both the left and right speakers 1L and 1R, Since the volume at the speaker is attenuated to 1/2, the total volume is equal to that for channel signals "3" and "4". In this way, the volumes of the clapping sounds emitted in channel signals "2" to "4" are all equal;
However, the volume positions are different: in the center, on the left, and on the right. Now, the third row of the musical score shown in Figure 6 shows the clap hand part, and the first to third notes (all quarter notes) are specified with the sound image position at the center, and the sound image position is specified as the center. The sound image positions of the fourth and fifth notes (both eighth notes) are designated as left and right, respectively (note that no accent marks are attached to these notes). In the case of such a performance part, the channel signal CH "2" at the timing corresponding to the first to third notes is
The output of the rhythm pattern generation circuit 18 is set to "1" at the channel signal CH "3" and "4" at the timing corresponding to each of the fourth and fifth notes. The output of 18 may be "1". In this way, musical tones as shown in the third row of FIG. 6 are produced. That is, after the applause sounds corresponding to the first to third notes are emitted from the center of the speakers 1L and 1R, the fifth and sixth notes are emitted from the left speaker 1L and the right speaker 1R in that order. It will be done. In this way, the sound image of the applause moves from the center to the left in synchronization with the predetermined rhythm,
Then, as it moves from left to right, the listener can sense a rhythmic movement that was unprecedented. Next, when the channel signal CH is "5" to "7", the respective control data "D ₁ , D ₀ " are both "1, 1".
Therefore, both signals Q ₂ and Q ₁ become “1” signals, and as a result, channel signals CH “1” and “2”
In the same way as in the case of , speakers 1L and 1R each output a cowbell sound, a snare drum sound, and a snare drum sound at 1/2 volume.
A high-hat cymbal sound is output. The second row of musical scores in Figure 6 shows the cowbell sound part in the aforementioned disco rhythm, and therefore,
When playing this part, use the channel signal CH “5” at the timing corresponding to the note shown.
In this case, the output of the rhythm pattern generation circuit 18 may be set to "1". In addition, SD and HH in the first row of musical scores in Figure 6 indicate the snare drum sound and high-hat sound parts, respectively, and in this case, the channel signals CH "6" and "7" at the timing corresponding to each note are also used. In this case, the output of the rhythm pattern generation circuit 18 may be set to "1". Note that HHC and HHO in the first row of notes indicate the part of the sound when the high hat cymbal is closed and opened, respectively, and when there are many types of sounds like this, the timing signal channel All you need to do is increase the number of channels and allocate the above-mentioned sounds to the added channels. Further, in this embodiment, a shifter 30 is provided, and this shifter 30 converts the waveform data into one part as appropriate.
Since the digits are lowered, it is possible to control whether or not a desired note is accented. In addition, although the above-mentioned embodiment is an example in which this invention is applied to an automatic rhythm performance device using a time division sounding method, this invention can of course also be applied to an automatic rhythm playing device using a parallel sounding method. .
In this case, as in the above-described embodiment, data specifying the position and accent of the sound image may be read out in synchronization with the rhythm pulse of each musical tone, and the sound generation position and volume may be controlled thereby. In addition, in the above embodiment, for the sake of simplicity of explanation, the positions of the sound images to be selected are three positions: left, center, and right (the volume ratios of speakers 1L and 1R are 1:0 and 1:1, respectively). , 0:1), but the position of the sound image is not limited to this, and may be configured to select any position between the left and right sides. That is, the number of bits of the control data that controls the position of the sound image is increased, and this control data is used to specify a detailed sound image position, so that the sound image position is as specified.
What is necessary is to control the volume ratio of the speakers 1L and 1R. Further, in the above embodiment, there are two musical sound generation systems capable of volume control, but the number may be increased to perform volume position control. [Effects of the invention] As explained above, this invention is an automatic system that reads multiple types of musical tone data stored in advance as appropriate based on a predetermined rhythm signal, and forms a rhythm musical tone signal using the read musical tone data. The rhythm performance device includes a musical tone signal forming means for forming a musical tone signal corresponding to the musical tone data to a plurality of spatially separated musical tone generators, and control for specifying a sound image position of each of the musical tone data. control data storage means for storing data; and sound image position control for reading out the control data corresponding to musical tones based on the predetermined rhythm signal and controlling the ratio of volume in each of the musical tone generating sections based on this control data. Since the sound image position of the desired sound source can be appropriately moved in synchronization with the rhythm pattern. Therefore, it is possible to obtain the spatial expansion of the generated sound, and also to enrich the sense of rhythmic dynamism.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, FIG. 2 is a schematic diagram showing the storage contents of the waveform RAM 3, FIG. 3 is a diagram showing control data in the control data table 9, and FIG. 5 is a block diagram showing a configuration example of the address data generation circuit 20, FIG. 5 is a timing chart showing the correspondence between the clock _φ1 and the channel signal CH in the same embodiment, and FIG. 6 is an example of the rhythm pattern in the same embodiment. This is the musical score shown. 1L, 1R... Sound generation section (speaker), 39, 4
0...Amplifier, 35, 36...Digital-to-analog converter (1L, 1R, 39, 40, 3
5 and 36 are first and second musical tone generating sections, respectively), 9...
...Control data table (control data memory), 3
1, 32... accumulator, 38... selection circuit (sound image position selection means).

Claims (1)

[Claims for Utility Model Registration] An automatic rhythm performance device that reads plural types of pre-stored musical tone data as appropriate based on a predetermined rhythm signal, and forms a rhythm musical tone signal using the read musical tone data, musical tone signal forming means for forming a musical tone signal corresponding to the musical tone data to a plurality of spatially separated musical tone generators; and control data storing control data specifying a sound image position of each of the musical tone data. and a sound image position control means for reading out the control data corresponding to a musical tone based on the predetermined rhythm signal and controlling the volume ratio in each of the musical tone generating sections based on this control data. Features an automatic rhythm performance device.