JPH03131125A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To attain pulse width modulation with fidelity by forming a pulse signal with a rough time width based on a high-order n-bit, sloping its leading or trailing edge, forming an analog signal based on a low-order (N-n) bits and combining the analog signals. CONSTITUTION:High-order 6 bits of an 8-bit multi-value picture density data (c) are inputted to a counter 1 and low-order 2 bits are inputted to a decoder 7 respectively. The rise of Q output of a JK flip-flop 3 sets a JK flip-flop 6 to bring its output Q(j) to a high level. The decoder 7 decodes the low-order 2-bit of a multi-value picture data and outputs the decode signal of a high level in response to the input data whose values are 0-3 to any of terminals Yo-Y3 respectively. Thus, a signal with fidelity to the input 8-bit multi-value picture data is obtained as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse width modulation circuit, and more particularly to a pulse width modulation circuit that modulates N-bit digital data into a pulse signal having a corresponding pulse width.

[Prior Art] This type of circuit is used in image forming apparatuses such as laser beam printers and LED printers.

FIG. 5 is a circuit diagram of a pulse width modulation circuit of a conventional image forming apparatus, and FIG. 6 is an operation timing chart of the circuit shown in FIG.

4-bit multivalued image data sent from an external device such as a host computer or scanner (not shown) is loaded into the counter 11 at the rising edge of the image clock signal. The counter 11 sequentially counts down based on the counting clock signal output from the counting clock generator 12, and when the counter output reaches O, a carry signal is output.

As a result, the Q output of the JK flip-flop 13 becomes a pulse width modulation signal that is set at the rising edge of the image clock signal and reset when the carry signal is generated.

This pulse width modulation signal is input to a laser driver circuit (not shown), and by blinking a laser element, a photosensitive drum (not shown) is exposed to light, and halftone density printing is performed using electrophotography.

[Problems to be Solved by the Invention] However, in order to express n gradation densities using the above conventional method, a counting clock signal with a frequency n times that of the image clock signal is required. For example, if the image clock signal is IMH2, a counting clock signal of 256MH2 is required to express 256 gradations with an 8-bit multivalued image signal. For this reason, expensive E CL (Emitt
It is necessary to use a high-speed device such as erCoupledLogic), and there is also a problem that radiation noise is likely to be generated due to the high speed.

The present invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is to provide a pulse width modulation circuit that can perform faithful pulse width modulation without using a high frequency counting clock signal. be.

[Means and effects for solving the problem] In order to achieve the above object, the pulse width modulation circuit of the present invention modulates N-bit digital data into a pulse signal with a corresponding pulse width. By counting clock signals of a predetermined frequency, the top n of the digital data is
A timing signal generation circuit that generates a timing signal with a time width based on bit data, and a timing signal on the front or rear side of the output of the timing signal generation circuit that is delayed by a time based on the lower (N-n) bit data of the digital data. The general outline of the present invention is to include a delay circuit that causes a delay to occur, and a flip-flop circuit or a latch circuit that is set/reset by each timing signal of the output of the timing signal generation circuit and the output of the delay circuit.

As a result, a timing signal with a coarse time width based on the upper n bits is formed, and a timing signal with a fine time width based on the lower (N-n) bits is formed, and the combination of these timing signals is used to control the flip-flop circuit. Or set/reset the latch circuit.

Further, in order to achieve the above object, the pulse width modulation circuit of the present invention counts clock signals of a predetermined frequency in a pulse width modulation circuit that modulates N-bit digital data into a pulse signal of a corresponding pulse width. a pulse signal generation circuit that generates a pulse signal with a time width based on the upper n-bit data of the digital data; a slope converting circuit that slopes the trailing edge or leading edge of the pulse signal output from the pulse signal generation circuit; a D/A conversion circuit that converts a value based on lower (N-n) bit data of digital data into an analog signal;
The outline thereof is to include a comparator circuit that compares each output signal of the D/A conversion circuit and the slope conversion circuit.

This forms a pulse signal with a coarse time width based on the upper n bits, and slopes its leading or trailing edge. An analog signal based on the lower (N-n) bits is also formed, and these are compared by a comparator.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[First Example] The first example relates to a case where a delay line circuit is used as a delay circuit.

FIG. 1 is a circuit diagram of a pulse width modulation circuit according to a first embodiment employed in an image forming apparatus, and FIG. 2 is an operation timing chart of the configuration shown in FIG.

In the figure, the upper 6 bits of the 8-bit multivalued image density data ◎ are sent to the counter 1, and the lower 2 bits are sent to the decoder 7.
Enter each. When the image clock signal ■ rises,
The upper 6-bit data is loaded into the counter 1, and the JK flip-flop 3 is set so that its Q output 2 becomes HIGH level. Thereafter, the counter 1 counts down by the counting clock signal 2 outputted from the counting clock generator 2. Here, the clock frequency of the counting clock signal (2) may be 64 times that of the image clock signal (2), and both are synchronized. When the counter value (2) of the counter 1 becomes "0", a carry signal (2) is output, and with the generation of the carry signal (2), the JK flip-flop 3 is cleared and its Q output becomes LOW level. In this way, the time when the Q output 0 of the JK flip-flop 3 is at the HIGH level is longer as the content of the upper 6 bits of the multivalued image data is larger.

Further, when the Q output 0 of the JK flip-flop 3 rises, it sets the JK flip-flop 6 and makes its output Q■ a HIGH level. In addition, the Q output (■) of the JK flip-flop 3 is input to the delay generating section 4, and is delayed by a predetermined time by three buffer circuits ic1 to ic3 that are chained inside, so that three Pulse signal 0,0. ■ is taken out.

On the other hand, the decoder 7 decodes the lower two bits of the multivalued image data, and outputs a HIGH level decode signal corresponding to the input data having a value of 0 to 3 to one of the terminals Y, -Y3, respectively. These decoded signals are sent to the delay selection section 5.
, and the output of the decoder 7 corresponds to the HIGH level. ic5. Only IC6 or IC7 is made conductive. That is, when input data = O, ic4
, when input data = 1, IC5 conducts, when input data = 2, IC6 conducts, and when input data = 3, only IC7 conducts.

As a result, the timing of the falling edge of the clock input for resetting the JK flip-flop 6 changes according to the size of the lower 2-bit data, and therefore the pulse width of the Q output (■) of the JK flip-flop 6 also changes. As a whole, the image becomes faithful to the input 8-bit multivalued image data. These are shown as waveforms for cases 1 to 4 in FIG.

Furthermore. The Q output 0 of the JK flip-flop 6 is input to a laser driver (not shown), which flashes a laser beam to expose a photosensitive drum (not shown), and further performs halftone density printing using electrophotography.

The buffer circuits icl to ic3 of the delay generating section 4 may be, for example, general-purpose logic ICs 74 with a large delay time.
LS07 etc. are used, and the delay selection section 5 and J
For the K flip-flop 6, 74ASO8, 74AS32, or the like, which has a sufficiently smaller delay time than the above-mentioned 74LSO7, is used.

Incidentally, delay line elements may be used in place of the buffer circuits ic1 to ic3 in FIG. 1.

This reduces the variation in delay between elements (and improves accuracy).

[Second Embodiment] The second embodiment relates to a case where a slope circuit is used as a delay circuit.

FIG. 3 is a circuit diagram of a pulse width modulation circuit according to a second embodiment employed in an image forming apparatus, and FIG. 4 is an operation timing chart of the configuration shown in FIG. 3.

Incidentally, the same parts as in the first embodiment are given the same reference numerals and the explanation thereof will be omitted.

In the figure, 9 is a CR (integrator) circuit, which blunts the falling part of the pulse signal (2) to create a slope. That is, when the pulse signal rises, diode D is bypassed and capacitor C is rapidly charged, but when the pulse signal falls, diode D is cut off, and the charge on capacitor C gradually passes through resistor R. discharge to. Therefore, the output of the CR circuit 9 becomes a signal (2).

On the other hand, the lower 2-bit data is input to the D/A converter 8, where it is converted into a signal whose voltage level decreases in order according to the value O to 3 of the lower 2-bit data. 10 is a high-speed analog comparator circuit, and by comparing the signal ■ and the signal ■, the pulse signal O is output only between ■>■.
Output.

As a result, the pulse width of the output [phase] of the comparator circuit 10 as a whole becomes faithful to the input 8-bit multivalued image data. These are cases 1 to 4 in Figure 4.
is shown as the waveform of

Incidentally, in the above embodiment, a case has been described in which the trailing edge of the pulse signal O formed by clock counting is extended, but the present invention is not limited to this. For example, the pulse width may be reduced by forming a pulse signal O' that is one count larger by clock counting and delaying the leading edge of the signal O'. For example, referring to FIG. 3, the polarity of the diode D may be reversed. The same can be said for FIG.

[Effects of the Invention] As described above (according to the present invention), the frequency of the counting clock signal can be lowered, the cost of the device used can be lowered, and the radiation noise can also be reduced. It is extremely effective when adopted in image forming devices such as printers.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the pulse width modulation circuit of the first embodiment adopted in the image forming apparatus, Fig. 2 is an operation timing chart of the circuit of Fig. 1, and Fig. 3 is a circuit diagram of the pulse width modulation circuit of the first embodiment adopted in the image forming apparatus. A circuit diagram of an example pulse width modulation circuit. FIG. 4 is an operation timing chart of the configuration shown in FIG. 3. FIG. 5 is a circuit diagram of a pulse width modulation circuit of a conventional image forming apparatus. 3 is an operation timing chart of the circuit. In the figure, 1...counter, 2...counting clock generator, 3...JK flip-flop, 4...delay generation section, 5...delay selection section, 6...JK flip-flop, 7... Decoder, 8... D/A converter,
9...CR circuit, 10...High speed analog comparator.

Claims (4)

[Claims] (1) In a pulse width modulation circuit that modulates N-bit digital data into a pulse signal with a corresponding pulse width, a timing signal with a time width based on the upper n-bit data of the digital data is generated by counting clock signals of a predetermined frequency. a timing signal generation circuit that generates a timing signal; a delay circuit that delays a timing signal on the front side or the rear side of the output of the timing signal generation circuit by a time based on the lower (N-n) bit data of the digital data; and the timing signal generation circuit. A pulse width modulation circuit comprising a flip-flop circuit or a latch circuit that is set/reset by each timing signal of a circuit output and the delay circuit output. (2) The pulse width modulation circuit according to claim 1, wherein the timing signal generation circuit includes a counter circuit, a shift register circuit, or a combination of these and a digital comparator circuit. (3) The delay circuit includes a delay line circuit that delays the propagation of the timing signal, a decoder circuit that decodes lower (N-n) bit data, and an output from the decoder circuit that outputs each intermediate output on the delay line circuit. Claim 1 comprising a selector circuit for selecting a signal.
The pulse width modulation circuit described in Section 1. (4) In a pulse width modulation circuit that modulates N-bit digital data into a pulse signal with a corresponding pulse width, a pulse signal with a time width based on the upper n-bit data of the digital data is generated by counting clock signals of a predetermined frequency. a pulse signal generation circuit that generates a pulse signal; a slope conversion circuit that slopes a trailing edge or a leading edge of a pulse signal output from the pulse signal generation circuit; A pulse width modulation circuit comprising: a D/A conversion circuit that converts into an analog signal; and a comparator circuit that compares each output signal of the D/A conversion circuit and the slope conversion circuit.