JPH03137775A - Picture processing device - Google Patents

Abstract

PURPOSE:To reduce the memory size and to increase the data transfer speed by outputting one-page components of output data based on two kinds of picture data stored in a storage means. CONSTITUTION:Picture data stored in a system memory 2 is generated by a CPU 1, and data to be stored is discriminated. In the case of multilevel data, it is discriminated whether an information table is formed or not. If the information table is not formed, block start coordinates and end coordinates are stored in a memory in a multilevel data control circuit 6 to form the information table of one block. Thereafter, picture data is outputted to a memory address where it should be stored, and simultaneously, a multilevel/binary signal is outputted. When printing is possible, a print signal is outputted from the CPU 1 to a picture memory control circuit 5 and the occupation right of a data bus is transferred.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, for example, converting text data or image data output from a host computer, word processor, etc. into bitmap image output data, and converting the data to a printer. The present invention relates to an image processing device that outputs to an output device such as a computer or CRT display.

[Prior Art] Conventionally, an image processing device (
As shown in FIG. 11, the controller unit stores data such as text and images outputted from a host computer, word processor, etc. in the work memory 102 through the input interface controller 104 using a page description language or the like. Later, CPU10
0 expands the data stored in the work memory 102 into bitmap data to be printed using the control program and font data in the ROM 101. The expansion is performed in the image memory 103. Work memory 1
After all the data in 02 has been expanded into bitmap data by the CPU 100, the output interface controller 105 sequentially reads the bitmap data in the image memory 103 and outputs the data in synchronization with the image clock. Printing occurs on the output device.

The above-mentioned controller section originally handles data output from a host computer, etc., and bitmap data to be output to an output device, depending on whether each type handles only binary data or multi-value data. It was designed differently. In the former case, the image memory 10
3 is stored so that 1 dot is 1 bit. For example, if the image quality is 300 dpi on A4 paper size, approximately 1 Mbyte of memory is required, and the data output from the output interface controller 105 is The transfer consists of two lines: an image clock line and a data line. In the latter case, the memory capacity is eight times that of the former (approximately 8M
The data transfer output from the output interface controller 105 consists of nine lines consisting of an image clock line and eight data lines. Also, when handling binary data such as text data with multi-value data, white data should be set to 0OH.
EX (HEX: l hexadecimal representation) is expressed as a black data FF, □8.

[Problems to be Solved by the Invention] However, in the controller unit in the above conventional example, if the data output from the host computer side is a mixture of binary data and multi-value data, the latter multi-value data You should choose the one that handles. In this case, there is a drawback that a large capacity memory is required and the cost of the controller section increases significantly. In addition, the image memory 10
3 is configured to store 1 dot in 1 byte units, so if only binary data is output to the host computer side, the efficiency of the storage method in memory will deteriorate,
Furthermore, data transfer between the CPU 100 and the image memory 103 is performed dot by dot, and bit-type/bait-type data conversion is required, resulting in a disadvantage that high-speed data transfer cannot be performed.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and its purpose is to efficiently utilize memory and to enable high-speed data transfer between a CPU and an image memory. The object of the present invention is to provide an image processing device.

[Means for Solving the Problems] In order to solve the above-mentioned problems and achieve the purpose, an image processing device according to the present invention forms output data of an image in which a binary image and a multivalued image are mixed, In an image processing device that outputs to a subsequent output device, an input means for inputting binary image data and multivalued image data, and generation of identification information for identifying two types of image data inputted by the input means. storage means for separately storing two types of image data inputted by the input means based on the identification information generated by the generation means;
The present invention is characterized by comprising an output means for outputting one page's worth of output data based on the type of image data.

[Operation] According to this configuration, the input means inputs binary image data and multi-value image data, and the generation means generates identification information for identifying the two types of image data input by the input means. , the storage means separately stores two types of image data inputted by the input means based on the identification information generated by the generation means, and the output means separately stores two types of image data inputted by the input means based on the identification information generated by the generation means, and the output means separately stores two types of image data inputted by the input means based on the identification information generated by the generation means. Output output data for pages.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, reference numeral 1 denotes a CPU that generates bitmap image output data from text or image source data or programs, and performs overall communication control with output devices such as post computers and printer engines. Reference numeral 2 indicates a system memory composed of a ROM 2a that stores control programs for the CPU 1 and character fonts, and a RAM 2b that stores source data such as text and images. Reference numerals 3 and 4 indicate image memories that store binary data (page memory) or multi-value data, and 5 controls access to the image memories 3 and 4 using binary data and multi-value data, and controls access during printing. This figure shows an image memory control circuit that generates a memory address from an image data read clock (MCLK). 6 has a memory for storing print (display) position data of multi-value data, and counts MCLK during printing and outputs a multi-value data output signal (GRAY) to the image memory control circuit 5 and output device. Data control circuit 7 communicates with an output device (not shown) and outputs a horizontal synchronization signal (H3YNC), image enable signal (lower ■), MCLK and image clock (VCLK) during printing, and an output interface controller 8 1A and 1B respectively show data conversion circuits that convert image data to be outputted into multi-value data when it is binary data.

FIG. 2 is a diagram showing the memory map configuration of the image processing apparatus in FIG. 1. In the figure, the memory is allocated in order from the lowest address to a system memory, a position information table for multi-value data, an image memory (page memory) for binary data, and an image memory for multi-value data.

FIG. 3 is a flowchart explaining the operation of the CPU 1 of this embodiment. In the first stage of print processing, first
Bitmap image data such as text and images to be output is sequentially generated by the PU I from the control program and font data stored in the system memory 2 (steps S1 and S2). From then on, C
Processing by the PUI continues. Next, it is determined whether the data to be stored in the image memory is a binary type or a multivalued type (step S3). If the result of the determination is multivalued data, specify the range of data blocks to be stored (
(indicates block start and end coordinates on the same line)
A determination is made as to whether an information table in which the information is written has been formed (step S4). If it is determined that an information table has not been formed, the block start coordinates and end coordinates (hereinafter, the start coordinates are referred to as left data and the end coordinates as right data) are stored in the memory in the multi-value data control circuit 6. and an information table of l block is formed (
Step S5). Thereafter, the image data is output to the memory address to be stored, and at the same time, a multi-value/binary signal indicating the type of image data is also output (step S6). This multi-value/binary signal is at "H" level when it is multi-valued, and is at "Lo" level when it is binary. In a laser printer, etc., the CPU performs the above operations (step 3.1 to step S6).
) is repeated until one page can be outputted, and it is determined in step St that the formation of the bitmap image data is complete, that is, that printing is possible. When it becomes possible to print, press C.
A PRINT signal is output from the PUI to the image memory control circuit 5, and ownership of the data bus is transferred to the image memory control circuit 5 (step S7). Thereafter, when the CPU 1 receives a print end signal from the image memory control circuit 5 (step S8), the exclusive right to the data bus is acquired again, and the series of operations ends (step S9). In this way, the process returns to its initial state.

FIG. 4 is a block diagram showing the configuration of the image memory control circuit 5 of this embodiment. In the figure, reference numeral 9 indicates a bus control unit that mediates the occupation of the data bus between the CPU i and the image memory control circuit 5. Here, a bus request signal (BR) is set by the output of the print signal from CFull, and the bus request signal (BR) is set by the output of the print signal from CFull. The print end signal (PEN
BR is reset by D). Reference numeral 10 includes an address selector that controls the connection of the address bus from the CPUI using a bus occupancy signal (BOC).

11 is the MC from the output interface controller 7
This figure shows a counter section for generating storage addresses for binary data and multivalued data in the image memory using LK. This counter section 11 consists of a binary counter and a multi-value counter. Both counters are initialized by the BOC from the CPU, and one of the binary counters becomes ready to count by the VE from the output interface controller 7, and the multi-value data is The GRAM from the control circuit 6 causes the other multi-value counter to become ready for counting. Reference numerals 12 and 13 indicate address buffers that output storage addresses for binary data and multi-value data, respectively. When the multi-value/binary signal output from the CPU 1 or the multi-value data enable signal (GRAY) output from the multi-value data control circuit 6 is at "H" level, the address buffer 13 is selected. , In this state, multi-level address data is valid, and “L”
” level, the address buffer 12 is selected, and in this state binary address data is valid.

Reference numeral 14 indicates a timing signal generation unit that generates a memory control signal during printing in synchronization with MCLK, and 15 indicates a CPU.
1 shows a selector that selects a memory control signal from the timing signal generator 14 and the timing signal generator 14 by means of a BCO.

Further, 50 indicates an OR gate that takes the logical sum of the multi-value/binary signal output from the CPU 1 and the GRAY output from the multi-value data control circuit 6.
The output from is sent to address buffer 12.13.

FIG. 5 is a flowchart illustrating the operation sequence of the image memory control circuit 5 of this embodiment.

In the image memory control circuit 5, PRIN from CPU i
The output of the T signal is monitored (step 521) and the PRIN
If the T signal is not output and BOC is in the ON state, CPLI 1 occupies the data bus and accesses the image memory 3.4 (step 522). Also,
When the PRINT signal is output (ON), the bus control unit 9
sets BR to request the CPU to occupy the data bus (step 323).
U1 sets BOC to OFF by setting BR. In this way, possession of the data bus is transferred to the image memory control circuit 5 (step 524), and the process enters a print ready state. Thereafter, the data in the image memory 3.4 is read out using VE and MCLK from the output interface controller 7 and GRAY from the multi-value data control circuit 6.

When the counter unit 11 confirms that VE is turned on,
Set the binary power counter to enable counting operation (step 525), count the MCLK pulses,
Output the count value onto the address bus (step 82)
6). In this case, the count state of the multi-value counter is determined by 0N10FF of GRAY output from the multi-value data control circuit 6, and the address buffer 12.1
3 is selected (step 527)
. When GRAY is ON (step 527), the multivalue counter is counted up (step 528), and the address buffer 13 is selected. However, this address buffer 13 stores the lower 3 bits of the input as “L”.
By inputting the address data from the counter section 11 to the fourth bit or higher from the lower bit (the lowest bit output from the counter section 11 corresponds to the fourth input bit of the address counter 13), a binary value is generated. Address data eight times the size of the data address, ie, multivalued address data, is generated (step 529). At the same time, the memory control signal generated by the timing signal generator 14 is output (step 530). Also, GRAY
is OFF (step 527), the multivalue counter stops counting, and the address buffer 12 is selected (step S31), except for the lower 3 bits from the counter section 11 (the lower 3 bits of the output are set to ``L''). The count value at the time (°° level) becomes the memory address of the binary data (step 532), and is output together with the memory control signal in the same way as above (step 533). The above-mentioned operations (steps 326 to 533) are repeated while V lower is in the ON state (step 534), and V
When E is OFF, it is determined whether the count value of MCLK of the counter section 11 is equal to the set value (step 53).
5) If the result is "not equal", the operations of steps S25 to S34 are repeated; however, if the result is "equal", the counter section 11
By setting D, the bus control unit 9 is notified of the end of the print operation, and the bus control unit 9 resets BR and transfers the exclusive right of the data bus to the CPU 1 (step 8
36). Since CPU 1 has reset BR, CPU 1 turns on BOC and regains possession of the bus, but
The counter section 11 is initialized by turning on the OC.

FIG. 6 is a block diagram showing the configuration of the multilevel data control circuit 6 of this embodiment. In the figure, 16 is an address decoder that decodes the address output from CPtJ and generates the address of information table 17, which will be described later. Information table to store, 18
1 shows an initialization signal generating section that outputs a counter reset signal (RESET), signals (LINT, RINT) for loading the first left data and right data into the column address counters 21 and 22, respectively, in response to the PRINT output from the CPU 1. There is. Reference numeral 19 indicates a timing signal generation unit that generates a control signal for reading left data and right data from the information table 17 during printing, and 20 indicates a coincidence signal (LEQU, RE) from the column address counters 21 and 22.
QU) and initialization signals (LINIT, RINIT
) is shown to generate the address of the information table 17. Reference numerals 21 and 22 indicate column address counters for left data and right data that count MCLK while VE is ON and output a match signal (LEQU, REQU) when it becomes equal to a preset value. 23, the left data read from the information table 17 is sent to the column address counter 21 by LEQU or LINT, and the right data is sent to the column address counter 21 by REQ.
A selector for loading column address counter 22 by U or RINIT is shown. 24 is LEQ
Reset GRAY by U and )ISYNCJ
/ shows flip frozzo. Further, 52 is LEQU output from the column address counters 21 and 22.
An OR gate 51 calculates the logical sum of REQU, and an OR gate 51 calculates the logical sum of the output of the OR gate 102 and LINIT and RINIT output from the initialization signal generating section 18.

FIG. 7 is a timing chart showing the timing when binary data and multi-value data are mixed. In the figure, the area excluding the images 200 to 202 is binary data, and the shaded area indicating images 200 to 202 is multivalued data.

The dash-dotted line in FIG. 7 indicates a specific printing line,
One page includes three images 200 to 202, that is, a multivalued data block. First, GRAY is reset by H3YNC, and after VE is turned ON, MCLK is input by column address counter 21.22.
starts counting. The count value of the column address counter 21 becomes equal to the set value (left data) at the part marked ■ shown at the timing of GRAY, and the column address counter 21 outputs LEQU at this point to read GRAY.
At the same time, the column address counter 21 loads the next left data (the data in the part marked with ■). Also,
At the part (3), the count value of the column address counter 22 becomes equal to the set value (write data), and the column address counter 22 resets GRAY by outputting REQU, and at the same time, the column address counter 22 outputs the next write data. Load (the data in the ■ part). In this way, only the periods from ■ to ■°1, from ■ to ■, and from ■ to ■, that is, only the part of the multivalued data block, are GRAY
is set.

FIG. 8 is a flowchart illustrating the operation of the multivalued data control circuit 6 of this embodiment. First, bitmap image data is created by the CPU i, but if the data type is multi-value data, an information table 17 of left data and right data indicating the range specification of the multi-value data block to be stored is generated. (step 540), and the image data is stored in the image memory 4. After storing the image data in the image memory and forming the multivalued data information table, the initialization signal generation unit 18 receives the P from the CPU 1.
The output of RINT is monitored (step 541), and if PRINT is output during this monitoring, RESET is output and the address counter 20 and column address counter 21 .
22 is reset (step 542). After that,
LINIT is output, whereby the address counter generates and outputs a memory address indicating the first left data of the information table 17, and the dimming signal generator 1
At 9, the left data is read by generating and outputting a memory read control signal. At this time, the selector 23 outputs this left data to the column address counter 21 using LINIT (step 843). Similarly, RINIT is output and the first write data is output to the column address counter 22 (step 544).
. After that, the print period begins, and H3YNC from the output interface controller 7 is turned ON (step 545), and GRAY, which is the Q output of the flip-flop 24, is reset to J/ (step 846), and VE is turned ON. (step 547),
Column address counters 21 and 22 count MCLK (step 548). After this, when the count value of the column address counter 21 becomes equal to the set value (left data), LEQU is output and GRAY is set, and at the same time the next left data is loaded (step S
49. step 550). Also, column address counter 2
2 outputs REQU to reset GRAY when the count value becomes equal to the set value (write data), and at the same time loads the next write data (step S51 and step 552). Column address counters 21 and 22 are VE
The steps S48 to S are performed only during the period when is ON.
The operation of step 12 is repeated, and the counting operation is stopped when VE turns OFF (step 553).

FIG. 9 is a block diagram showing the configuration of the data conversion circuit 8 of this embodiment. In the figure, 25 is binary data (Do) that is read out from the image memory 3 by counting MCLK.
-D7), this pit encoder 25 outputs a select signal (SO to S7) for validating only an arbitrary bit, and this pit encoder 25 is initialized by HSYNC, and during the period when VE is ON, MCL
Count K, SO, SL...S7. So, SL,
S7. The select signals are output in the order of So, . . . 2
6 indicates a selector that enables only an arbitrary bit on the data bus from the above select signal, and 27 indicates that GRAY is O.
28 indicates a binary data buffer that outputs input data to the image data bus when it is FF (in the case of binary data), and 28 outputs the data on the data bus to the image data bus when GRAY is ON (in the case of multi-value data). This shows a multi-level data buffer that is output to

As explained above, according to this embodiment, in the process of generating bitmap data from data written in a page description language or the like output from the host computer, binary data and multivalued data are each converted into bitmap data. In particular, in the case of multivalued data, only the data to be printed is specified and stored in the image memory, so memory can be used efficiently and the memory size can be reduced. Furthermore, data conversion is not required within the CPU when storing binary data and multi-value data in each image memory, so data can be transferred at high speed between the CPU and the image memory.

Now, in the above-mentioned embodiment, the data conversion circuit 8 outputs binary data and multi-value data through one bus, but the present invention is not limited to this, and the binary data bus ( By providing a 1-bit data bus and a multi-value data bus (8-bit), the output buses may be separated for each type of data.

FIG. 1O is a block diagram showing the configuration of a modified example of the data conversion circuit.

In this modified example, as shown in FIG. 10, the output data of the selector 26 is used instead of the binary data buffer 27 which distributes 1 bit output from the selector 26 shown in FIG. 9 into 8 bits and inputs it. It consists of one buffer 54 that outputs only when GRAY is at "L" level.

Needless to say, even in this case, effects similar to those of the above-mentioned embodiment can be obtained.

Now, in the embodiments and modifications described above, the output device (not shown) is a display device or a recording device, but the present invention is not limited to this, and may be applied to a communication device such as a facsimile. .

[Effects of the Invention] As explained above, according to the present invention, memory can be used efficiently and memory size can be reduced, and data transfer between the CPU and image memory can be performed at high speed. It can be carried out.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the memory map configuration of the image processing device in FIG. 1, and FIG. 3 explains the operation of the CPU 1 of this embodiment. FIG. 4 is a block diagram showing the configuration of the image memory control circuit 5 of this embodiment. FIG. 5 is a flow chart explaining the operation sequence of the image memory control circuit 5 of this embodiment. A block diagram showing the configuration of the example multi-value data control circuit 6, FIG. 7 is a timing chart showing the timing when binary data and multi-value data are mixed, and FIG. 8 is a multi-value data control circuit according to the present embodiment. 9 is a block diagram showing the configuration of the data conversion circuit 8 of this embodiment. FIG. 1O is a block diagram showing the configuration of a modified example of the data conversion circuit. FIG. 11 is the conventional example. FIG. 2 is a block diagram showing the configuration of an image processing device of FIG. In the figure, 1. too...CPU, 2...System memo, 2a, 101...ROM,
2b, 102-... RAM, 3, 4, 10
3... Image memory, 5... Image memory system (sum circuit,
6... Multi-value data control circuit, 7... Output interface controller, 8... Data conversion circuit, 9...
...Bus control unit, 10...Address selector, 11.
...Counter section, 12.13...Address buffer,
14...timing signal generation section, 15, 23.26.
...Selector, 16...Address decoder, 17...
- Information table, 18... Initialization signal generation section, 19... Timing signal generation section, 20... Address counter, 21, 22... Column address counter, 2
4...Flip-flop in J/, 25...Pit encoder, 27.28...Data buffer, 50.5
1.52...OR gate, 54...buffer, 10
4... Input interface controller, 105.
...It is an output interface controller.

Claims (4)

[Claims] (1) In an image processing device that forms output data of a mixed image of a binary image and a multivalued image and outputs it to a subsequent output device, an input means for inputting the binary image data and the multivalued image data. and generating means for generating identification information for identifying the two types of image data inputted by the inputting means, and generating means for generating identification information for identifying the two types of image data inputted by the inputting means based on the identification information generated by the generating means An image processing device comprising: storage means for separately storing image data; and output means for outputting one page of output data based on two types of image data stored in the storage means. (2) The output means configures the image data lines for outputting the output data with the same number as the bit width constituting the pixels of the multi-valued image data, and when outputting the binary image data, data converting means for outputting all bits of the image data line as 0 or 1 based on the value of binary image data; and when outputting the output data to the output device, the type of the output data is 2. The image processing apparatus according to claim 1, further comprising instruction means for issuing an instruction based on the identification information generated by the generation means. (3) The output means configures an image data line for outputting the output data into two types of data lines that separately output the binary image data and the multi-value image data, and The image processing apparatus according to claim 2, further comprising instruction means for instructing the type of the output data based on the identification information generated by the generation means when outputting the output data to the apparatus. . (4) The image processing apparatus according to claim 1, wherein the output device is a recording device or a display device.