JPH03134894A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile semiconductor memory device having a large the potential difference appearing in a bit line by carring out the differential amplification of potential difference of the bit lines pair after connecting be tween an EEPROM cell of selective memory element and the bit line. CONSTITUTION:When data are transmitted to a DRAM cell, the paired bit lines Bj, the inverse of Bj, an EEPROM cell is set to the middle potential 1/2 Vcc in a precharging time and in the case of connecting a selecting memory element, a source is connected to the bit line Bj. A MOS transistor TR4 where the drain is connected to the Vcc (electric power source potential) is turned on, after allowing potential of bit line Bj to be boosted up to the nearby poten tial of power source potential, the transistor is turned off. Then, the transistor TR1 of the selecting memory element is turned on, the potential corresponding to the data of the EEPROM cell appeares on a DRAM cell and on the bit line. Then, the MOS transistor TR2 for transfering the data of the selecting memory element is turned off, the differential amplification of potential differ ence of bit line Bj, th inverse of Bj is started. In such a manner, the memory device having large bit line potential difference and small layout area is obtained.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is applicable to semiconductor memory devices, particularly DRAM cells and EEP
The present invention relates to a nonvolatile semiconductor memory device in which ROM cells are combined into one cell.

<Prior Art> FIG. 4 shows a conventional circuit configuration of a nonvolatile semiconductor memory device (hereinafter referred to as rNVRAMJ) in which a DRAM cell and an EEPROM cell are combined into one cell, and FIG. 5 shows conventional operation timing waveforms. NVRAM DRAM cells MC3 and E
EPROM cells MC4 are combined to form one memory cell, and during power-on operation, only the DRAM cell operates, and the data in the DRAM cell is transferred to the EEFROM cell.
Alternatively, the EEPROM cell operates only when reading data from the EEPROM cell to the DRAM cell.

Once the data in the DRAM cell is transferred to the EEPROM cell, the DRAM data will remain in the EEPROM even if the power is turned off.
The data in the EEPROM cell can be read into the DRAM after the power is turned on again.

<Problems to be Solved by the Invention> However, in the conventional circuit, one cell is lined up on a bit line pair (control gate line CG, bit line B), which doubles the layout area. In addition, the MOS transistor Tr1
Since the source side of 4 is connected to VCC, the EEFR
It takes time to read the VTH (low) level of the OM cell, and the potential difference appearing on the bit line is small.

The present invention has been made in view of the problems of the conventional circuit described above, and provides an NVRAM in which data is read from an EEPROM cell to a DRAM cell at high speed, has a large bit line potential difference, and has a small layout area. It is.

<Means for Solving the Problems> The semiconductor memory device of the present invention has a plurality of bit lines to which a plurality of memory elements in which a DRAM cell and an EEPROM cell are combined into one cell are connected, and a common line for each memory element. A semiconductor memory device having a memory array consisting of a plurality of word lines functioning as word electrodes and MOS transistors used during data transfer between DRAM cells and EEFROM cells, characterized by meeting the following requirements: This is a semiconductor memory device that uses

+11 E E F Control gate electrode of floating gate transistor and DRA that constitute ROM cell
A common capacitor electrode is connected to the bit line side of the M cells and is made of polysilicon.

+21 E E F ROM cell data to DRAM
When data is transferred to a cell, the source side of the floating gate transistor constituting the EEPROM cell is set to the ground potential.

+3] EEPROM cell data kDRAM
When transferring to a cell, the potential of the bit line on the side of the bit line pair to which the selected memory element is connected is set to the power supply potential or a potential near it, and the potential of the bit line on the other side is set to the power supply potential or a potential near it. After the potential is set to an intermediate potential, the EEPROM cell of the first selected memory element and the bit line are connected, and then the EEPROM cell and the bit line are separated, and differential amplification of the potential difference between the bit line pair is performed.

Further, the semiconductor memory device of the present invention includes a plurality of bit lines to which a plurality of memory elements each formed by combining a DRAM cell and an EEPROM cell into one cell are connected, and a plurality of bit lines which function as a common word electrode of each memory element. A semiconductor memory device having a memory array composed of word lines and MO8I-transistors used for data transfer between DRAM cells and EEPROM cells, which is characterized by meeting the following requirements. .

ill E E F Control gate electrode of floating gate transistor and DRA constituting ROM cell
A common capacitor electrode is connected to the bit line side of the M cells and is made of polysilicon.

[2] Transfer data from EEPROM cells to DRAM
When data is transferred to a cell, the source side of the floating gate transistor constituting the EEPROM cell is set to the ground potential.

[31 When data in an EEPROM cell is transferred to a DRAM cell, after all DRAM cells are set to the power supply potential or a potential near it, the MOS transistor is turned off.

<Example> FIG. 1 shows a circuit configuration of an example of the present invention, and FIG. 2 shows operation timing waveforms.

Further, a cross-sectional structural diagram of the memory cell is shown in FIG.

A plurality of memory elements MC in which a DRAM cell MCz and an EEPROM cell MC2 are combined into one cell.

... are connected to a plurality of bit lines Bj, Bj (j=
1, . . .] and a plurality of first word lines wli(i-1, .
) and a MOS transistor Tr2 used for data transfer between DRAM cells and EEPROM cells.

Note that W2i (i=1...) is a second word line that functions as a common second word electrode for each memory element.

Control gate w pole CG and DRA of floating gate transistor Tr3 configured in EEPROM cell MC2
The capacitor electrode CP1 connected to the bit line Bj side of the M cell MCI is common and is made of polysilicon. Tr
l is the access transistor of the DRAM cell, C□ is the DR
AM capacitor, CF2 is a capacitor electrode. FG
is a floating gate, and TO is a tunnel oxide film.

When data is transferred from the EEFROM cell to the DRAM cell, the source S side of the floating gate transistor Tr3 constituting the EEFROM cell is set to the ground potential GND.

When transferring data from an EEPROM cell to a DRAM cell, bit line pair Bj is activated during precharge time.

Bj is set to intermediate potential %VCC (φPR+)I, M
OS transistor Tr6. Tr7, Trs on), then the MOS transistor Tr4 whose source is connected to the bit line Bj to which the selected memory element is connected and whose drain is connected to V(c (power supply potential)) is turned on (φ2→H).
, the transistor is turned off after the potential of the bit line Bj is raised to a potential near the power supply potential. Subsequently, the access transistor Tr1 of the selected memory element turns on.
i-+H), a potential corresponding to the data of the EEPROM cell appears on the DRAM cell and the bit line. Thereafter, the MO5+- transistor Tr2 for data transfer of the selected memory element is turned off (W2i-)L), and differential amplification of the potential difference between the shoulders of the bit line pair Bj is started (φx+H, MO5)-transistor Tr9* Trlo is turned on, SA : Differential amplifier circuit). The data transfer transistor Tr2 of the selected memory element is turned on from when the transistor Tr is turned on until the access transistor Tr1 is turned on. and,
It is turned off before starting the differential amplification operation of the potential difference between the bit line pair.

In addition, DRAM data parameters 1'', 0'' and EEPROM
The correspondence between cells and VTR levels high and low is shown in the table below.

The following method is also possible for the operation timing of data transfer (recall) to the DRAM cell.

■ Make periodic wire pair B j, B j ft, 3AVcc.

■ Selected bit line potential rise and access transistor T
rl on.

■ Bit line potential increase transistor Tr4 (Trs)
is turned off and the data transfer transistor Tr2 is turned on to change the potential of the bit line.

(2) Turn off the data transfer transistor Tr2 and start differential amplification operation.

In the above method, if two-layer metal is used, the second word line W21
This is possible because the time constant of is reduced.

During recall operation, V is applied to the first word line W1□ and the second word line W21. By applying a boost voltage of C or higher, the bit line charge can easily escape from the EEFROM cell,
Recall operation time can be shortened.

In the above embodiment, the transistors T rg , T r
The on/off of 7°Trs, Tr4 (Tr5), and Tr2 and the operation of the differential amplifier circuit SA connected to the bit line pair are as follows:
Since it is repeated every time for each word line, it takes time to read data from the EEPROM cell to the DRAM cell. Another embodiment of the present invention that improves this point will be described below. The circuit configuration and memory cell structure are the same as in the above embodiment.

When data in the EEPROM cell is transferred to the DRAM cell 'i, the source S side of the floating gate transistor Tr3 constituting the EEpRoM cell is set to the ground potential.

When transferring data from an EEPROM cell to a DRAM cell, bit line pair Bj is activated during precharge time.

Bj is set near the VCC level (φ2.φ3→H,
Transistors Tra, Trs are turned on), and then the access transistor Tr1 of the selected memory element is turned on (Wl).
i+H), the DRAM cell is set near the Vcc level. Thereafter, the access transistor Tr□ of the 1 selected memory element is turned off (W1i→L). During this time, the data transfer transistor Tr2 is off (W2 t
=L). Repeat the same operation until all DRAM cells'
After setting near the fcVcc level, the data transfer transistors Tr2i of all memory elements are turned on simultaneously or sequentially in predetermined block units, and the potential of the DRAM cell is set to a potential corresponding to the vTH level of the EEPROM cell. , finish the transfer. When transferring data from an EEPROM cell to a DRAM cell, the charge on the bit line pair is
Do not pull out in direction D.

<Effects of the Invention> As is clear from the above description, according to the present invention, an extremely useful semiconductor memory device that solves the conventional problems is proposed.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is an operation timing waveform diagram, FIG. 8 is a cross-sectional structure diagram of a memory cell, and FIG.
The figure is a circuit configuration diagram of a conventional NVRAM, and FIG. 5 is an operation timing waveform diagram. Explanation of symbols MC: Memory element, MC□: DRAM cell, MCz
:EEPROM cell, Bj, BJ: bit line, Wli
: first word line, W21: second word line, Try: access transistor, Tr2: data transfer transistor, Tr3: floating gate transistor, C1
:DRAM capacitor. CGCCP□・): DRAM capacitor electrode in front of control gate electrode of floating gate transistor, Tr,
, -, Trl (1: MOS transistor. SA: differential amplifier circuit.

Claims (1)

[Scope of Claims] 1. A plurality of bit lines to which a plurality of memory elements in which a DRAM cell and an EEPROM cell are combined into one cell are connected, and a plurality of word lines that function as a common word electrode for each memory element. and a semiconductor memory device having a memory array constituted by MOS transistors used during data transfer between DRAM cells and EEPROM cells, characterized in that the semiconductor memory device has the following requirements. (1) The control gate electrode of the floating gate transistor constituting the EEPROM cell and the capacitor electrode connected to the bit line side of the DRAM cell are common and are made of polysilicon. (2) When transferring data from the EEPROM cell to the DRAM cell, the source side of the floating gate transistor constituting the EEPROM cell is set to the ground potential. (3) When transferring data from an EEPROM cell to a DRAM cell, the potential of the bit line on the side of the bit line pair to which the selected memory element is connected is set to the power supply potential or a potential near it, and the bit line on the other side After the potential of the line is set to an intermediate potential, the EEPROM cell of the selected memory element and the bit line are connected, and then the EEPROM cell and the bit line are separated, and differential amplification of the potential difference between the bit line pair is performed. be exposed. 2. A plurality of bit lines to which a plurality of memory elements in which a DRAM cell and an EEPROM cell are combined into one cell are connected, a plurality of word lines that function as a common word electrode of each memory element, and a DRAM cell and an EEPROM cell. A semiconductor memory device having a memory array constituted by MOS transistors used during data transfer between cells, characterized in that the semiconductor memory device has the following requirements. (1) The control gate electrode of the floating gate transistor constituting the EEPROM cell and the capacitor electrode connected to the bit line side of the DRAM cell are common and are made of polysilicon. (2) When transferring data from the EEPROM cell to the DRAM cell, the source side of the floating gate transistor constituting the EEPROM cell is set to the ground potential. (3) When transferring data from an EEPROM cell to a DRAM cell, the MOS transistor is turned on after all DRAM cells are set to the power supply potential or a potential near it.